1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 42 #include "amdgpu_ras.h" 43 #include "amdgpu_securedisplay.h" 44 #include "amdgpu_atomfirmware.h" 45 46 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 47 48 static int psp_load_smu_fw(struct psp_context *psp); 49 static int psp_rap_terminate(struct psp_context *psp); 50 static int psp_securedisplay_terminate(struct psp_context *psp); 51 52 static int psp_ring_init(struct psp_context *psp, 53 enum psp_ring_type ring_type) 54 { 55 int ret = 0; 56 struct psp_ring *ring; 57 struct amdgpu_device *adev = psp->adev; 58 59 ring = &psp->km_ring; 60 61 ring->ring_type = ring_type; 62 63 /* allocate 4k Page of Local Frame Buffer memory for ring */ 64 ring->ring_size = 0x1000; 65 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 66 AMDGPU_GEM_DOMAIN_VRAM | 67 AMDGPU_GEM_DOMAIN_GTT, 68 &adev->firmware.rbuf, 69 &ring->ring_mem_mc_addr, 70 (void **)&ring->ring_mem); 71 if (ret) { 72 ring->ring_size = 0; 73 return ret; 74 } 75 76 return 0; 77 } 78 79 /* 80 * Due to DF Cstate management centralized to PMFW, the firmware 81 * loading sequence will be updated as below: 82 * - Load KDB 83 * - Load SYS_DRV 84 * - Load tOS 85 * - Load PMFW 86 * - Setup TMR 87 * - Load other non-psp fw 88 * - Load ASD 89 * - Load XGMI/RAS/HDCP/DTM TA if any 90 * 91 * This new sequence is required for 92 * - Arcturus and onwards 93 */ 94 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 95 { 96 struct amdgpu_device *adev = psp->adev; 97 98 if (amdgpu_sriov_vf(adev)) { 99 psp->pmfw_centralized_cstate_management = false; 100 return; 101 } 102 103 switch (adev->ip_versions[MP0_HWIP][0]) { 104 case IP_VERSION(11, 0, 0): 105 case IP_VERSION(11, 0, 4): 106 case IP_VERSION(11, 0, 5): 107 case IP_VERSION(11, 0, 7): 108 case IP_VERSION(11, 0, 9): 109 case IP_VERSION(11, 0, 11): 110 case IP_VERSION(11, 0, 12): 111 case IP_VERSION(11, 0, 13): 112 case IP_VERSION(13, 0, 0): 113 case IP_VERSION(13, 0, 2): 114 case IP_VERSION(13, 0, 7): 115 psp->pmfw_centralized_cstate_management = true; 116 break; 117 default: 118 psp->pmfw_centralized_cstate_management = false; 119 break; 120 } 121 } 122 123 static int psp_init_sriov_microcode(struct psp_context *psp) 124 { 125 struct amdgpu_device *adev = psp->adev; 126 char ucode_prefix[30]; 127 int ret = 0; 128 129 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 130 131 switch (adev->ip_versions[MP0_HWIP][0]) { 132 case IP_VERSION(9, 0, 0): 133 case IP_VERSION(11, 0, 7): 134 case IP_VERSION(11, 0, 9): 135 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 136 ret = psp_init_cap_microcode(psp, ucode_prefix); 137 break; 138 case IP_VERSION(13, 0, 2): 139 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 140 ret = psp_init_cap_microcode(psp, ucode_prefix); 141 ret &= psp_init_ta_microcode(psp, ucode_prefix); 142 break; 143 case IP_VERSION(13, 0, 0): 144 adev->virt.autoload_ucode_id = 0; 145 break; 146 case IP_VERSION(13, 0, 6): 147 ret = psp_init_cap_microcode(psp, ucode_prefix); 148 break; 149 case IP_VERSION(13, 0, 10): 150 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 151 ret = psp_init_cap_microcode(psp, ucode_prefix); 152 break; 153 default: 154 return -EINVAL; 155 } 156 return ret; 157 } 158 159 static int psp_early_init(void *handle) 160 { 161 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 162 struct psp_context *psp = &adev->psp; 163 164 switch (adev->ip_versions[MP0_HWIP][0]) { 165 case IP_VERSION(9, 0, 0): 166 psp_v3_1_set_psp_funcs(psp); 167 psp->autoload_supported = false; 168 break; 169 case IP_VERSION(10, 0, 0): 170 case IP_VERSION(10, 0, 1): 171 psp_v10_0_set_psp_funcs(psp); 172 psp->autoload_supported = false; 173 break; 174 case IP_VERSION(11, 0, 2): 175 case IP_VERSION(11, 0, 4): 176 psp_v11_0_set_psp_funcs(psp); 177 psp->autoload_supported = false; 178 break; 179 case IP_VERSION(11, 0, 0): 180 case IP_VERSION(11, 0, 7): 181 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev); 182 fallthrough; 183 case IP_VERSION(11, 0, 5): 184 case IP_VERSION(11, 0, 9): 185 case IP_VERSION(11, 0, 11): 186 case IP_VERSION(11, 5, 0): 187 case IP_VERSION(11, 0, 12): 188 case IP_VERSION(11, 0, 13): 189 psp_v11_0_set_psp_funcs(psp); 190 psp->autoload_supported = true; 191 break; 192 case IP_VERSION(11, 0, 3): 193 case IP_VERSION(12, 0, 1): 194 psp_v12_0_set_psp_funcs(psp); 195 break; 196 case IP_VERSION(13, 0, 2): 197 case IP_VERSION(13, 0, 6): 198 psp_v13_0_set_psp_funcs(psp); 199 break; 200 case IP_VERSION(13, 0, 1): 201 case IP_VERSION(13, 0, 3): 202 case IP_VERSION(13, 0, 5): 203 case IP_VERSION(13, 0, 8): 204 case IP_VERSION(13, 0, 11): 205 case IP_VERSION(14, 0, 0): 206 psp_v13_0_set_psp_funcs(psp); 207 psp->autoload_supported = true; 208 break; 209 case IP_VERSION(11, 0, 8): 210 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 211 psp_v11_0_8_set_psp_funcs(psp); 212 psp->autoload_supported = false; 213 } 214 break; 215 case IP_VERSION(13, 0, 0): 216 case IP_VERSION(13, 0, 7): 217 case IP_VERSION(13, 0, 10): 218 psp_v13_0_set_psp_funcs(psp); 219 psp->autoload_supported = true; 220 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 221 break; 222 case IP_VERSION(13, 0, 4): 223 psp_v13_0_4_set_psp_funcs(psp); 224 psp->autoload_supported = true; 225 break; 226 default: 227 return -EINVAL; 228 } 229 230 psp->adev = adev; 231 232 psp_check_pmfw_centralized_cstate_management(psp); 233 234 if (amdgpu_sriov_vf(adev)) 235 return psp_init_sriov_microcode(psp); 236 else 237 return psp_init_microcode(psp); 238 } 239 240 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 241 { 242 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 243 &mem_ctx->shared_buf); 244 mem_ctx->shared_bo = NULL; 245 } 246 247 static void psp_free_shared_bufs(struct psp_context *psp) 248 { 249 void *tmr_buf; 250 void **pptr; 251 252 /* free TMR memory buffer */ 253 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 254 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 255 psp->tmr_bo = NULL; 256 257 /* free xgmi shared memory */ 258 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 259 260 /* free ras shared memory */ 261 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 262 263 /* free hdcp shared memory */ 264 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 265 266 /* free dtm shared memory */ 267 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 268 269 /* free rap shared memory */ 270 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 271 272 /* free securedisplay shared memory */ 273 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 274 275 276 } 277 278 static void psp_memory_training_fini(struct psp_context *psp) 279 { 280 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 281 282 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 283 kfree(ctx->sys_cache); 284 ctx->sys_cache = NULL; 285 } 286 287 static int psp_memory_training_init(struct psp_context *psp) 288 { 289 int ret; 290 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 291 292 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 293 DRM_DEBUG("memory training is not supported!\n"); 294 return 0; 295 } 296 297 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 298 if (ctx->sys_cache == NULL) { 299 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 300 ret = -ENOMEM; 301 goto Err_out; 302 } 303 304 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 305 ctx->train_data_size, 306 ctx->p2c_train_data_offset, 307 ctx->c2p_train_data_offset); 308 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 309 return 0; 310 311 Err_out: 312 psp_memory_training_fini(psp); 313 return ret; 314 } 315 316 /* 317 * Helper funciton to query psp runtime database entry 318 * 319 * @adev: amdgpu_device pointer 320 * @entry_type: the type of psp runtime database entry 321 * @db_entry: runtime database entry pointer 322 * 323 * Return false if runtime database doesn't exit or entry is invalid 324 * or true if the specific database entry is found, and copy to @db_entry 325 */ 326 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 327 enum psp_runtime_entry_type entry_type, 328 void *db_entry) 329 { 330 uint64_t db_header_pos, db_dir_pos; 331 struct psp_runtime_data_header db_header = {0}; 332 struct psp_runtime_data_directory db_dir = {0}; 333 bool ret = false; 334 int i; 335 336 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6)) 337 return false; 338 339 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 340 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 341 342 /* read runtime db header from vram */ 343 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 344 sizeof(struct psp_runtime_data_header), false); 345 346 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 347 /* runtime db doesn't exist, exit */ 348 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 349 return false; 350 } 351 352 /* read runtime database entry from vram */ 353 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 354 sizeof(struct psp_runtime_data_directory), false); 355 356 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 357 /* invalid db entry count, exit */ 358 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 359 return false; 360 } 361 362 /* look up for requested entry type */ 363 for (i = 0; i < db_dir.entry_count && !ret; i++) { 364 if (db_dir.entry_list[i].entry_type == entry_type) { 365 switch (entry_type) { 366 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 367 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 368 /* invalid db entry size */ 369 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 370 return false; 371 } 372 /* read runtime database entry */ 373 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 374 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 375 ret = true; 376 break; 377 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 378 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 379 /* invalid db entry size */ 380 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 381 return false; 382 } 383 /* read runtime database entry */ 384 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 385 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 386 ret = true; 387 break; 388 default: 389 ret = false; 390 break; 391 } 392 } 393 } 394 395 return ret; 396 } 397 398 static int psp_sw_init(void *handle) 399 { 400 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 401 struct psp_context *psp = &adev->psp; 402 int ret; 403 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 404 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 405 struct psp_runtime_scpm_entry scpm_entry; 406 407 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 408 if (!psp->cmd) { 409 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 410 ret = -ENOMEM; 411 } 412 413 adev->psp.xgmi_context.supports_extended_data = 414 !adev->gmc.xgmi.connected_to_cpu && 415 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 416 417 memset(&scpm_entry, 0, sizeof(scpm_entry)); 418 if ((psp_get_runtime_db_entry(adev, 419 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 420 &scpm_entry)) && 421 (scpm_entry.scpm_status != SCPM_DISABLE)) { 422 adev->scpm_enabled = true; 423 adev->scpm_status = scpm_entry.scpm_status; 424 } else { 425 adev->scpm_enabled = false; 426 adev->scpm_status = SCPM_DISABLE; 427 } 428 429 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 430 431 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 432 if (psp_get_runtime_db_entry(adev, 433 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 434 &boot_cfg_entry)) { 435 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 436 if ((psp->boot_cfg_bitmask) & 437 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 438 /* If psp runtime database exists, then 439 * only enable two stage memory training 440 * when TWO_STAGE_DRAM_TRAINING bit is set 441 * in runtime database 442 */ 443 mem_training_ctx->enable_mem_training = true; 444 } 445 446 } else { 447 /* If psp runtime database doesn't exist or is 448 * invalid, force enable two stage memory training 449 */ 450 mem_training_ctx->enable_mem_training = true; 451 } 452 453 if (mem_training_ctx->enable_mem_training) { 454 ret = psp_memory_training_init(psp); 455 if (ret) { 456 DRM_ERROR("Failed to initialize memory training!\n"); 457 return ret; 458 } 459 460 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 461 if (ret) { 462 DRM_ERROR("Failed to process memory training!\n"); 463 return ret; 464 } 465 } 466 467 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 468 amdgpu_sriov_vf(adev) ? 469 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 470 &psp->fw_pri_bo, 471 &psp->fw_pri_mc_addr, 472 &psp->fw_pri_buf); 473 if (ret) 474 return ret; 475 476 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 477 AMDGPU_GEM_DOMAIN_VRAM | 478 AMDGPU_GEM_DOMAIN_GTT, 479 &psp->fence_buf_bo, 480 &psp->fence_buf_mc_addr, 481 &psp->fence_buf); 482 if (ret) 483 goto failed1; 484 485 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 486 AMDGPU_GEM_DOMAIN_VRAM | 487 AMDGPU_GEM_DOMAIN_GTT, 488 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 489 (void **)&psp->cmd_buf_mem); 490 if (ret) 491 goto failed2; 492 493 return 0; 494 495 failed2: 496 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 497 &psp->fence_buf_mc_addr, &psp->fence_buf); 498 failed1: 499 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 500 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 501 return ret; 502 } 503 504 static int psp_sw_fini(void *handle) 505 { 506 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 507 struct psp_context *psp = &adev->psp; 508 struct psp_gfx_cmd_resp *cmd = psp->cmd; 509 510 psp_memory_training_fini(psp); 511 512 amdgpu_ucode_release(&psp->sos_fw); 513 amdgpu_ucode_release(&psp->asd_fw); 514 amdgpu_ucode_release(&psp->ta_fw); 515 amdgpu_ucode_release(&psp->cap_fw); 516 amdgpu_ucode_release(&psp->toc_fw); 517 518 kfree(cmd); 519 cmd = NULL; 520 521 psp_free_shared_bufs(psp); 522 523 if (psp->km_ring.ring_mem) 524 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 525 &psp->km_ring.ring_mem_mc_addr, 526 (void **)&psp->km_ring.ring_mem); 527 528 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 529 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 530 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 531 &psp->fence_buf_mc_addr, &psp->fence_buf); 532 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 533 (void **)&psp->cmd_buf_mem); 534 535 return 0; 536 } 537 538 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 539 uint32_t reg_val, uint32_t mask, bool check_changed) 540 { 541 uint32_t val; 542 int i; 543 struct amdgpu_device *adev = psp->adev; 544 545 if (psp->adev->no_hw_access) 546 return 0; 547 548 for (i = 0; i < adev->usec_timeout; i++) { 549 val = RREG32(reg_index); 550 if (check_changed) { 551 if (val != reg_val) 552 return 0; 553 } else { 554 if ((val & mask) == reg_val) 555 return 0; 556 } 557 udelay(1); 558 } 559 560 return -ETIME; 561 } 562 563 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 564 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout) 565 { 566 uint32_t val; 567 int i; 568 struct amdgpu_device *adev = psp->adev; 569 570 if (psp->adev->no_hw_access) 571 return 0; 572 573 for (i = 0; i < msec_timeout; i++) { 574 val = RREG32(reg_index); 575 if ((val & mask) == reg_val) 576 return 0; 577 msleep(1); 578 } 579 580 return -ETIME; 581 } 582 583 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 584 { 585 switch (cmd_id) { 586 case GFX_CMD_ID_LOAD_TA: 587 return "LOAD_TA"; 588 case GFX_CMD_ID_UNLOAD_TA: 589 return "UNLOAD_TA"; 590 case GFX_CMD_ID_INVOKE_CMD: 591 return "INVOKE_CMD"; 592 case GFX_CMD_ID_LOAD_ASD: 593 return "LOAD_ASD"; 594 case GFX_CMD_ID_SETUP_TMR: 595 return "SETUP_TMR"; 596 case GFX_CMD_ID_LOAD_IP_FW: 597 return "LOAD_IP_FW"; 598 case GFX_CMD_ID_DESTROY_TMR: 599 return "DESTROY_TMR"; 600 case GFX_CMD_ID_SAVE_RESTORE: 601 return "SAVE_RESTORE_IP_FW"; 602 case GFX_CMD_ID_SETUP_VMR: 603 return "SETUP_VMR"; 604 case GFX_CMD_ID_DESTROY_VMR: 605 return "DESTROY_VMR"; 606 case GFX_CMD_ID_PROG_REG: 607 return "PROG_REG"; 608 case GFX_CMD_ID_GET_FW_ATTESTATION: 609 return "GET_FW_ATTESTATION"; 610 case GFX_CMD_ID_LOAD_TOC: 611 return "ID_LOAD_TOC"; 612 case GFX_CMD_ID_AUTOLOAD_RLC: 613 return "AUTOLOAD_RLC"; 614 case GFX_CMD_ID_BOOT_CFG: 615 return "BOOT_CFG"; 616 default: 617 return "UNKNOWN CMD"; 618 } 619 } 620 621 static int 622 psp_cmd_submit_buf(struct psp_context *psp, 623 struct amdgpu_firmware_info *ucode, 624 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 625 { 626 int ret; 627 int index; 628 int timeout = 20000; 629 bool ras_intr = false; 630 bool skip_unsupport = false; 631 632 if (psp->adev->no_hw_access) 633 return 0; 634 635 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 636 637 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 638 639 index = atomic_inc_return(&psp->fence_value); 640 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 641 if (ret) { 642 atomic_dec(&psp->fence_value); 643 goto exit; 644 } 645 646 amdgpu_device_invalidate_hdp(psp->adev, NULL); 647 while (*((unsigned int *)psp->fence_buf) != index) { 648 if (--timeout == 0) 649 break; 650 /* 651 * Shouldn't wait for timeout when err_event_athub occurs, 652 * because gpu reset thread triggered and lock resource should 653 * be released for psp resume sequence. 654 */ 655 ras_intr = amdgpu_ras_intr_triggered(); 656 if (ras_intr) 657 break; 658 usleep_range(10, 100); 659 amdgpu_device_invalidate_hdp(psp->adev, NULL); 660 } 661 662 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 663 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 664 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 665 666 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 667 668 /* In some cases, psp response status is not 0 even there is no 669 * problem while the command is submitted. Some version of PSP FW 670 * doesn't write 0 to that field. 671 * So here we would like to only print a warning instead of an error 672 * during psp initialization to avoid breaking hw_init and it doesn't 673 * return -EINVAL. 674 */ 675 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 676 if (ucode) 677 DRM_WARN("failed to load ucode %s(0x%X) ", 678 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 679 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 680 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 681 psp->cmd_buf_mem->resp.status); 682 /* If any firmware (including CAP) load fails under SRIOV, it should 683 * return failure to stop the VF from initializing. 684 * Also return failure in case of timeout 685 */ 686 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 687 ret = -EINVAL; 688 goto exit; 689 } 690 } 691 692 if (ucode) { 693 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 694 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 695 } 696 697 exit: 698 return ret; 699 } 700 701 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 702 { 703 struct psp_gfx_cmd_resp *cmd = psp->cmd; 704 705 mutex_lock(&psp->mutex); 706 707 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 708 709 return cmd; 710 } 711 712 static void release_psp_cmd_buf(struct psp_context *psp) 713 { 714 mutex_unlock(&psp->mutex); 715 } 716 717 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 718 struct psp_gfx_cmd_resp *cmd, 719 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 720 { 721 struct amdgpu_device *adev = psp->adev; 722 uint32_t size = 0; 723 uint64_t tmr_pa = 0; 724 725 if (tmr_bo) { 726 size = amdgpu_bo_size(tmr_bo); 727 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 728 } 729 730 if (amdgpu_sriov_vf(psp->adev)) 731 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 732 else 733 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 734 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 735 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 736 cmd->cmd.cmd_setup_tmr.buf_size = size; 737 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 738 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 739 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 740 } 741 742 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 743 uint64_t pri_buf_mc, uint32_t size) 744 { 745 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 746 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 747 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 748 cmd->cmd.cmd_load_toc.toc_size = size; 749 } 750 751 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 752 static int psp_load_toc(struct psp_context *psp, 753 uint32_t *tmr_size) 754 { 755 int ret; 756 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 757 758 /* Copy toc to psp firmware private buffer */ 759 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 760 761 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 762 763 ret = psp_cmd_submit_buf(psp, NULL, cmd, 764 psp->fence_buf_mc_addr); 765 if (!ret) 766 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 767 768 release_psp_cmd_buf(psp); 769 770 return ret; 771 } 772 773 static bool psp_boottime_tmr(struct psp_context *psp) 774 { 775 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 776 case IP_VERSION(13, 0, 6): 777 return true; 778 default: 779 return false; 780 } 781 } 782 783 /* Set up Trusted Memory Region */ 784 static int psp_tmr_init(struct psp_context *psp) 785 { 786 int ret = 0; 787 int tmr_size; 788 void *tmr_buf; 789 void **pptr; 790 791 /* 792 * According to HW engineer, they prefer the TMR address be "naturally 793 * aligned" , e.g. the start address be an integer divide of TMR size. 794 * 795 * Note: this memory need be reserved till the driver 796 * uninitializes. 797 */ 798 tmr_size = PSP_TMR_SIZE(psp->adev); 799 800 /* For ASICs support RLC autoload, psp will parse the toc 801 * and calculate the total size of TMR needed 802 */ 803 if (!amdgpu_sriov_vf(psp->adev) && 804 psp->toc.start_addr && 805 psp->toc.size_bytes && 806 psp->fw_pri_buf) { 807 ret = psp_load_toc(psp, &tmr_size); 808 if (ret) { 809 DRM_ERROR("Failed to load toc\n"); 810 return ret; 811 } 812 } 813 814 if (!psp->tmr_bo) { 815 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 816 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 817 PSP_TMR_ALIGNMENT, 818 AMDGPU_HAS_VRAM(psp->adev) ? 819 AMDGPU_GEM_DOMAIN_VRAM : 820 AMDGPU_GEM_DOMAIN_GTT, 821 &psp->tmr_bo, &psp->tmr_mc_addr, 822 pptr); 823 } 824 825 return ret; 826 } 827 828 static bool psp_skip_tmr(struct psp_context *psp) 829 { 830 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 831 case IP_VERSION(11, 0, 9): 832 case IP_VERSION(11, 0, 7): 833 case IP_VERSION(13, 0, 2): 834 case IP_VERSION(13, 0, 6): 835 case IP_VERSION(13, 0, 10): 836 return true; 837 default: 838 return false; 839 } 840 } 841 842 static int psp_tmr_load(struct psp_context *psp) 843 { 844 int ret; 845 struct psp_gfx_cmd_resp *cmd; 846 847 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 848 * Already set up by host driver. 849 */ 850 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 851 return 0; 852 853 cmd = acquire_psp_cmd_buf(psp); 854 855 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 856 if (psp->tmr_bo) 857 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 858 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 859 860 ret = psp_cmd_submit_buf(psp, NULL, cmd, 861 psp->fence_buf_mc_addr); 862 863 release_psp_cmd_buf(psp); 864 865 return ret; 866 } 867 868 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 869 struct psp_gfx_cmd_resp *cmd) 870 { 871 if (amdgpu_sriov_vf(psp->adev)) 872 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 873 else 874 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 875 } 876 877 static int psp_tmr_unload(struct psp_context *psp) 878 { 879 int ret; 880 struct psp_gfx_cmd_resp *cmd; 881 882 /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV, 883 * as TMR is not loaded at all 884 */ 885 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 886 return 0; 887 888 cmd = acquire_psp_cmd_buf(psp); 889 890 psp_prep_tmr_unload_cmd_buf(psp, cmd); 891 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 892 893 ret = psp_cmd_submit_buf(psp, NULL, cmd, 894 psp->fence_buf_mc_addr); 895 896 release_psp_cmd_buf(psp); 897 898 return ret; 899 } 900 901 static int psp_tmr_terminate(struct psp_context *psp) 902 { 903 return psp_tmr_unload(psp); 904 } 905 906 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 907 uint64_t *output_ptr) 908 { 909 int ret; 910 struct psp_gfx_cmd_resp *cmd; 911 912 if (!output_ptr) 913 return -EINVAL; 914 915 if (amdgpu_sriov_vf(psp->adev)) 916 return 0; 917 918 cmd = acquire_psp_cmd_buf(psp); 919 920 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 921 922 ret = psp_cmd_submit_buf(psp, NULL, cmd, 923 psp->fence_buf_mc_addr); 924 925 if (!ret) { 926 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 927 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 928 } 929 930 release_psp_cmd_buf(psp); 931 932 return ret; 933 } 934 935 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 936 { 937 struct psp_context *psp = &adev->psp; 938 struct psp_gfx_cmd_resp *cmd; 939 int ret; 940 941 if (amdgpu_sriov_vf(adev)) 942 return 0; 943 944 cmd = acquire_psp_cmd_buf(psp); 945 946 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 947 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 948 949 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 950 if (!ret) { 951 *boot_cfg = 952 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 953 } 954 955 release_psp_cmd_buf(psp); 956 957 return ret; 958 } 959 960 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 961 { 962 int ret; 963 struct psp_context *psp = &adev->psp; 964 struct psp_gfx_cmd_resp *cmd; 965 966 if (amdgpu_sriov_vf(adev)) 967 return 0; 968 969 cmd = acquire_psp_cmd_buf(psp); 970 971 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 972 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 973 cmd->cmd.boot_cfg.boot_config = boot_cfg; 974 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 975 976 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 977 978 release_psp_cmd_buf(psp); 979 980 return ret; 981 } 982 983 static int psp_rl_load(struct amdgpu_device *adev) 984 { 985 int ret; 986 struct psp_context *psp = &adev->psp; 987 struct psp_gfx_cmd_resp *cmd; 988 989 if (!is_psp_fw_valid(psp->rl)) 990 return 0; 991 992 cmd = acquire_psp_cmd_buf(psp); 993 994 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 995 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 996 997 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 998 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 999 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 1000 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 1001 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 1002 1003 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1004 1005 release_psp_cmd_buf(psp); 1006 1007 return ret; 1008 } 1009 1010 int psp_spatial_partition(struct psp_context *psp, int mode) 1011 { 1012 struct psp_gfx_cmd_resp *cmd; 1013 int ret; 1014 1015 if (amdgpu_sriov_vf(psp->adev)) 1016 return 0; 1017 1018 cmd = acquire_psp_cmd_buf(psp); 1019 1020 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART; 1021 cmd->cmd.cmd_spatial_part.mode = mode; 1022 1023 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode); 1024 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1025 1026 release_psp_cmd_buf(psp); 1027 1028 return ret; 1029 } 1030 1031 static int psp_asd_initialize(struct psp_context *psp) 1032 { 1033 int ret; 1034 1035 /* If PSP version doesn't match ASD version, asd loading will be failed. 1036 * add workaround to bypass it for sriov now. 1037 * TODO: add version check to make it common 1038 */ 1039 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 1040 return 0; 1041 1042 psp->asd_context.mem_context.shared_mc_addr = 0; 1043 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 1044 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 1045 1046 ret = psp_ta_load(psp, &psp->asd_context); 1047 if (!ret) 1048 psp->asd_context.initialized = true; 1049 1050 return ret; 1051 } 1052 1053 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1054 uint32_t session_id) 1055 { 1056 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1057 cmd->cmd.cmd_unload_ta.session_id = session_id; 1058 } 1059 1060 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1061 { 1062 int ret; 1063 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1064 1065 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1066 1067 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1068 1069 context->resp_status = cmd->resp.status; 1070 1071 release_psp_cmd_buf(psp); 1072 1073 return ret; 1074 } 1075 1076 static int psp_asd_terminate(struct psp_context *psp) 1077 { 1078 int ret; 1079 1080 if (amdgpu_sriov_vf(psp->adev)) 1081 return 0; 1082 1083 if (!psp->asd_context.initialized) 1084 return 0; 1085 1086 ret = psp_ta_unload(psp, &psp->asd_context); 1087 if (!ret) 1088 psp->asd_context.initialized = false; 1089 1090 return ret; 1091 } 1092 1093 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1094 uint32_t id, uint32_t value) 1095 { 1096 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1097 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1098 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1099 } 1100 1101 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1102 uint32_t value) 1103 { 1104 struct psp_gfx_cmd_resp *cmd; 1105 int ret = 0; 1106 1107 if (reg >= PSP_REG_LAST) 1108 return -EINVAL; 1109 1110 cmd = acquire_psp_cmd_buf(psp); 1111 1112 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1113 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1114 if (ret) 1115 DRM_ERROR("PSP failed to program reg id %d", reg); 1116 1117 release_psp_cmd_buf(psp); 1118 1119 return ret; 1120 } 1121 1122 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1123 uint64_t ta_bin_mc, 1124 struct ta_context *context) 1125 { 1126 cmd->cmd_id = context->ta_load_type; 1127 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1128 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1129 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1130 1131 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1132 lower_32_bits(context->mem_context.shared_mc_addr); 1133 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1134 upper_32_bits(context->mem_context.shared_mc_addr); 1135 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1136 } 1137 1138 int psp_ta_init_shared_buf(struct psp_context *psp, 1139 struct ta_mem_context *mem_ctx) 1140 { 1141 /* 1142 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1143 * physical) for ta to host memory 1144 */ 1145 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1146 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1147 AMDGPU_GEM_DOMAIN_GTT, 1148 &mem_ctx->shared_bo, 1149 &mem_ctx->shared_mc_addr, 1150 &mem_ctx->shared_buf); 1151 } 1152 1153 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1154 uint32_t ta_cmd_id, 1155 uint32_t session_id) 1156 { 1157 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1158 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1159 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1160 } 1161 1162 int psp_ta_invoke(struct psp_context *psp, 1163 uint32_t ta_cmd_id, 1164 struct ta_context *context) 1165 { 1166 int ret; 1167 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1168 1169 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1170 1171 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1172 psp->fence_buf_mc_addr); 1173 1174 context->resp_status = cmd->resp.status; 1175 1176 release_psp_cmd_buf(psp); 1177 1178 return ret; 1179 } 1180 1181 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1182 { 1183 int ret; 1184 struct psp_gfx_cmd_resp *cmd; 1185 1186 cmd = acquire_psp_cmd_buf(psp); 1187 1188 psp_copy_fw(psp, context->bin_desc.start_addr, 1189 context->bin_desc.size_bytes); 1190 1191 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1192 1193 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1194 psp->fence_buf_mc_addr); 1195 1196 context->resp_status = cmd->resp.status; 1197 1198 if (!ret) 1199 context->session_id = cmd->resp.session_id; 1200 1201 release_psp_cmd_buf(psp); 1202 1203 return ret; 1204 } 1205 1206 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1207 { 1208 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1209 } 1210 1211 int psp_xgmi_terminate(struct psp_context *psp) 1212 { 1213 int ret; 1214 struct amdgpu_device *adev = psp->adev; 1215 1216 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1217 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1218 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1219 adev->gmc.xgmi.connected_to_cpu)) 1220 return 0; 1221 1222 if (!psp->xgmi_context.context.initialized) 1223 return 0; 1224 1225 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1226 1227 psp->xgmi_context.context.initialized = false; 1228 1229 return ret; 1230 } 1231 1232 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1233 { 1234 struct ta_xgmi_shared_memory *xgmi_cmd; 1235 int ret; 1236 1237 if (!psp->ta_fw || 1238 !psp->xgmi_context.context.bin_desc.size_bytes || 1239 !psp->xgmi_context.context.bin_desc.start_addr) 1240 return -ENOENT; 1241 1242 if (!load_ta) 1243 goto invoke; 1244 1245 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1246 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1247 1248 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1249 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1250 if (ret) 1251 return ret; 1252 } 1253 1254 /* Load XGMI TA */ 1255 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1256 if (!ret) 1257 psp->xgmi_context.context.initialized = true; 1258 else 1259 return ret; 1260 1261 invoke: 1262 /* Initialize XGMI session */ 1263 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1264 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1265 xgmi_cmd->flag_extend_link_record = set_extended_data; 1266 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1267 1268 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1269 1270 return ret; 1271 } 1272 1273 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1274 { 1275 struct ta_xgmi_shared_memory *xgmi_cmd; 1276 int ret; 1277 1278 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1279 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1280 1281 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1282 1283 /* Invoke xgmi ta to get hive id */ 1284 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1285 if (ret) 1286 return ret; 1287 1288 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1289 1290 return 0; 1291 } 1292 1293 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1294 { 1295 struct ta_xgmi_shared_memory *xgmi_cmd; 1296 int ret; 1297 1298 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1299 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1300 1301 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1302 1303 /* Invoke xgmi ta to get the node id */ 1304 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1305 if (ret) 1306 return ret; 1307 1308 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1309 1310 return 0; 1311 } 1312 1313 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1314 { 1315 return (psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1316 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) || 1317 psp->adev->ip_versions[MP0_HWIP][0] >= IP_VERSION(13, 0, 6); 1318 } 1319 1320 /* 1321 * Chips that support extended topology information require the driver to 1322 * reflect topology information in the opposite direction. This is 1323 * because the TA has already exceeded its link record limit and if the 1324 * TA holds bi-directional information, the driver would have to do 1325 * multiple fetches instead of just two. 1326 */ 1327 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1328 struct psp_xgmi_node_info node_info) 1329 { 1330 struct amdgpu_device *mirror_adev; 1331 struct amdgpu_hive_info *hive; 1332 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1333 uint64_t dst_node_id = node_info.node_id; 1334 uint8_t dst_num_hops = node_info.num_hops; 1335 uint8_t dst_num_links = node_info.num_links; 1336 1337 hive = amdgpu_get_xgmi_hive(psp->adev); 1338 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1339 struct psp_xgmi_topology_info *mirror_top_info; 1340 int j; 1341 1342 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1343 continue; 1344 1345 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1346 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1347 if (mirror_top_info->nodes[j].node_id != src_node_id) 1348 continue; 1349 1350 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1351 /* 1352 * prevent 0 num_links value re-reflection since reflection 1353 * criteria is based on num_hops (direct or indirect). 1354 * 1355 */ 1356 if (dst_num_links) 1357 mirror_top_info->nodes[j].num_links = dst_num_links; 1358 1359 break; 1360 } 1361 1362 break; 1363 } 1364 1365 amdgpu_put_xgmi_hive(hive); 1366 } 1367 1368 int psp_xgmi_get_topology_info(struct psp_context *psp, 1369 int number_devices, 1370 struct psp_xgmi_topology_info *topology, 1371 bool get_extended_data) 1372 { 1373 struct ta_xgmi_shared_memory *xgmi_cmd; 1374 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1375 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1376 int i; 1377 int ret; 1378 1379 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1380 return -EINVAL; 1381 1382 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1383 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1384 xgmi_cmd->flag_extend_link_record = get_extended_data; 1385 1386 /* Fill in the shared memory with topology information as input */ 1387 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1388 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1389 topology_info_input->num_nodes = number_devices; 1390 1391 for (i = 0; i < topology_info_input->num_nodes; i++) { 1392 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1393 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1394 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1395 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1396 } 1397 1398 /* Invoke xgmi ta to get the topology information */ 1399 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1400 if (ret) 1401 return ret; 1402 1403 /* Read the output topology information from the shared memory */ 1404 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1405 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1406 for (i = 0; i < topology->num_nodes; i++) { 1407 /* extended data will either be 0 or equal to non-extended data */ 1408 if (topology_info_output->nodes[i].num_hops) 1409 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1410 1411 /* non-extended data gets everything here so no need to update */ 1412 if (!get_extended_data) { 1413 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1414 topology->nodes[i].is_sharing_enabled = 1415 topology_info_output->nodes[i].is_sharing_enabled; 1416 topology->nodes[i].sdma_engine = 1417 topology_info_output->nodes[i].sdma_engine; 1418 } 1419 1420 } 1421 1422 /* Invoke xgmi ta again to get the link information */ 1423 if (psp_xgmi_peer_link_info_supported(psp)) { 1424 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1425 bool requires_reflection = 1426 (psp->xgmi_context.supports_extended_data && get_extended_data) || 1427 psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6); 1428 1429 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1430 1431 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1432 1433 if (ret) 1434 return ret; 1435 1436 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1437 for (i = 0; i < topology->num_nodes; i++) { 1438 /* accumulate num_links on extended data */ 1439 topology->nodes[i].num_links = get_extended_data ? 1440 topology->nodes[i].num_links + 1441 link_info_output->nodes[i].num_links : 1442 ((requires_reflection && topology->nodes[i].num_links) ? topology->nodes[i].num_links : 1443 link_info_output->nodes[i].num_links); 1444 1445 /* reflect the topology information for bi-directionality */ 1446 if (requires_reflection && topology->nodes[i].num_hops) 1447 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1448 } 1449 } 1450 1451 return 0; 1452 } 1453 1454 int psp_xgmi_set_topology_info(struct psp_context *psp, 1455 int number_devices, 1456 struct psp_xgmi_topology_info *topology) 1457 { 1458 struct ta_xgmi_shared_memory *xgmi_cmd; 1459 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1460 int i; 1461 1462 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1463 return -EINVAL; 1464 1465 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1466 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1467 1468 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1469 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1470 topology_info_input->num_nodes = number_devices; 1471 1472 for (i = 0; i < topology_info_input->num_nodes; i++) { 1473 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1474 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1475 topology_info_input->nodes[i].is_sharing_enabled = 1; 1476 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1477 } 1478 1479 /* Invoke xgmi ta to set topology information */ 1480 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1481 } 1482 1483 // ras begin 1484 static void psp_ras_ta_check_status(struct psp_context *psp) 1485 { 1486 struct ta_ras_shared_memory *ras_cmd = 1487 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1488 1489 switch (ras_cmd->ras_status) { 1490 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1491 dev_warn(psp->adev->dev, 1492 "RAS WARNING: cmd failed due to unsupported ip\n"); 1493 break; 1494 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1495 dev_warn(psp->adev->dev, 1496 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1497 break; 1498 case TA_RAS_STATUS__SUCCESS: 1499 break; 1500 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1501 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1502 dev_warn(psp->adev->dev, 1503 "RAS WARNING: Inject error to critical region is not allowed\n"); 1504 break; 1505 default: 1506 dev_warn(psp->adev->dev, 1507 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1508 break; 1509 } 1510 } 1511 1512 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1513 { 1514 struct ta_ras_shared_memory *ras_cmd; 1515 int ret; 1516 1517 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1518 1519 /* 1520 * TODO: bypass the loading in sriov for now 1521 */ 1522 if (amdgpu_sriov_vf(psp->adev)) 1523 return 0; 1524 1525 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1526 1527 if (amdgpu_ras_intr_triggered()) 1528 return ret; 1529 1530 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 1531 DRM_WARN("RAS: Unsupported Interface"); 1532 return -EINVAL; 1533 } 1534 1535 if (!ret) { 1536 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1537 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1538 1539 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1540 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1541 dev_warn(psp->adev->dev, 1542 "RAS internal register access blocked\n"); 1543 1544 psp_ras_ta_check_status(psp); 1545 } 1546 1547 return ret; 1548 } 1549 1550 int psp_ras_enable_features(struct psp_context *psp, 1551 union ta_ras_cmd_input *info, bool enable) 1552 { 1553 struct ta_ras_shared_memory *ras_cmd; 1554 int ret; 1555 1556 if (!psp->ras_context.context.initialized) 1557 return -EINVAL; 1558 1559 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1560 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1561 1562 if (enable) 1563 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1564 else 1565 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1566 1567 ras_cmd->ras_in_message = *info; 1568 1569 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1570 if (ret) 1571 return -EINVAL; 1572 1573 return 0; 1574 } 1575 1576 int psp_ras_terminate(struct psp_context *psp) 1577 { 1578 int ret; 1579 1580 /* 1581 * TODO: bypass the terminate in sriov for now 1582 */ 1583 if (amdgpu_sriov_vf(psp->adev)) 1584 return 0; 1585 1586 if (!psp->ras_context.context.initialized) 1587 return 0; 1588 1589 ret = psp_ta_unload(psp, &psp->ras_context.context); 1590 1591 psp->ras_context.context.initialized = false; 1592 1593 return ret; 1594 } 1595 1596 int psp_ras_initialize(struct psp_context *psp) 1597 { 1598 int ret; 1599 uint32_t boot_cfg = 0xFF; 1600 struct amdgpu_device *adev = psp->adev; 1601 struct ta_ras_shared_memory *ras_cmd; 1602 1603 /* 1604 * TODO: bypass the initialize in sriov for now 1605 */ 1606 if (amdgpu_sriov_vf(adev)) 1607 return 0; 1608 1609 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1610 !adev->psp.ras_context.context.bin_desc.start_addr) { 1611 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1612 return 0; 1613 } 1614 1615 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1616 /* query GECC enablement status from boot config 1617 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1618 */ 1619 ret = psp_boot_config_get(adev, &boot_cfg); 1620 if (ret) 1621 dev_warn(adev->dev, "PSP get boot config failed\n"); 1622 1623 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1624 if (!boot_cfg) { 1625 dev_info(adev->dev, "GECC is disabled\n"); 1626 } else { 1627 /* disable GECC in next boot cycle if ras is 1628 * disabled by module parameter amdgpu_ras_enable 1629 * and/or amdgpu_ras_mask, or boot_config_get call 1630 * is failed 1631 */ 1632 ret = psp_boot_config_set(adev, 0); 1633 if (ret) 1634 dev_warn(adev->dev, "PSP set boot config failed\n"); 1635 else 1636 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1637 } 1638 } else { 1639 if (boot_cfg == 1) { 1640 dev_info(adev->dev, "GECC is enabled\n"); 1641 } else { 1642 /* enable GECC in next boot cycle if it is disabled 1643 * in boot config, or force enable GECC if failed to 1644 * get boot configuration 1645 */ 1646 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1647 if (ret) 1648 dev_warn(adev->dev, "PSP set boot config failed\n"); 1649 else 1650 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1651 } 1652 } 1653 } 1654 1655 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1656 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1657 1658 if (!psp->ras_context.context.mem_context.shared_buf) { 1659 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1660 if (ret) 1661 return ret; 1662 } 1663 1664 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1665 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1666 1667 if (amdgpu_ras_is_poison_mode_supported(adev)) 1668 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1669 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1670 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1671 ras_cmd->ras_in_message.init_flags.xcc_mask = 1672 adev->gfx.xcc_mask; 1673 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; 1674 1675 ret = psp_ta_load(psp, &psp->ras_context.context); 1676 1677 if (!ret && !ras_cmd->ras_status) 1678 psp->ras_context.context.initialized = true; 1679 else { 1680 if (ras_cmd->ras_status) 1681 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1682 1683 /* fail to load RAS TA */ 1684 psp->ras_context.context.initialized = false; 1685 } 1686 1687 return ret; 1688 } 1689 1690 int psp_ras_trigger_error(struct psp_context *psp, 1691 struct ta_ras_trigger_error_input *info, uint32_t instance_mask) 1692 { 1693 struct ta_ras_shared_memory *ras_cmd; 1694 struct amdgpu_device *adev = psp->adev; 1695 int ret; 1696 uint32_t dev_mask; 1697 1698 if (!psp->ras_context.context.initialized) 1699 return -EINVAL; 1700 1701 switch (info->block_id) { 1702 case TA_RAS_BLOCK__GFX: 1703 dev_mask = GET_MASK(GC, instance_mask); 1704 break; 1705 case TA_RAS_BLOCK__SDMA: 1706 dev_mask = GET_MASK(SDMA0, instance_mask); 1707 break; 1708 case TA_RAS_BLOCK__VCN: 1709 case TA_RAS_BLOCK__JPEG: 1710 dev_mask = GET_MASK(VCN, instance_mask); 1711 break; 1712 default: 1713 dev_mask = instance_mask; 1714 break; 1715 } 1716 1717 /* reuse sub_block_index for backward compatibility */ 1718 dev_mask <<= AMDGPU_RAS_INST_SHIFT; 1719 dev_mask &= AMDGPU_RAS_INST_MASK; 1720 info->sub_block_index |= dev_mask; 1721 1722 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1723 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1724 1725 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1726 ras_cmd->ras_in_message.trigger_error = *info; 1727 1728 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1729 if (ret) 1730 return -EINVAL; 1731 1732 /* If err_event_athub occurs error inject was successful, however 1733 * return status from TA is no long reliable 1734 */ 1735 if (amdgpu_ras_intr_triggered()) 1736 return 0; 1737 1738 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1739 return -EACCES; 1740 else if (ras_cmd->ras_status) 1741 return -EINVAL; 1742 1743 return 0; 1744 } 1745 // ras end 1746 1747 // HDCP start 1748 static int psp_hdcp_initialize(struct psp_context *psp) 1749 { 1750 int ret; 1751 1752 /* 1753 * TODO: bypass the initialize in sriov for now 1754 */ 1755 if (amdgpu_sriov_vf(psp->adev)) 1756 return 0; 1757 1758 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1759 !psp->hdcp_context.context.bin_desc.start_addr) { 1760 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1761 return 0; 1762 } 1763 1764 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1765 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1766 1767 if (!psp->hdcp_context.context.mem_context.shared_buf) { 1768 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1769 if (ret) 1770 return ret; 1771 } 1772 1773 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1774 if (!ret) { 1775 psp->hdcp_context.context.initialized = true; 1776 mutex_init(&psp->hdcp_context.mutex); 1777 } 1778 1779 return ret; 1780 } 1781 1782 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1783 { 1784 /* 1785 * TODO: bypass the loading in sriov for now 1786 */ 1787 if (amdgpu_sriov_vf(psp->adev)) 1788 return 0; 1789 1790 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1791 } 1792 1793 static int psp_hdcp_terminate(struct psp_context *psp) 1794 { 1795 int ret; 1796 1797 /* 1798 * TODO: bypass the terminate in sriov for now 1799 */ 1800 if (amdgpu_sriov_vf(psp->adev)) 1801 return 0; 1802 1803 if (!psp->hdcp_context.context.initialized) 1804 return 0; 1805 1806 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1807 1808 psp->hdcp_context.context.initialized = false; 1809 1810 return ret; 1811 } 1812 // HDCP end 1813 1814 // DTM start 1815 static int psp_dtm_initialize(struct psp_context *psp) 1816 { 1817 int ret; 1818 1819 /* 1820 * TODO: bypass the initialize in sriov for now 1821 */ 1822 if (amdgpu_sriov_vf(psp->adev)) 1823 return 0; 1824 1825 if (!psp->dtm_context.context.bin_desc.size_bytes || 1826 !psp->dtm_context.context.bin_desc.start_addr) { 1827 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1828 return 0; 1829 } 1830 1831 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1832 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1833 1834 if (!psp->dtm_context.context.mem_context.shared_buf) { 1835 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1836 if (ret) 1837 return ret; 1838 } 1839 1840 ret = psp_ta_load(psp, &psp->dtm_context.context); 1841 if (!ret) { 1842 psp->dtm_context.context.initialized = true; 1843 mutex_init(&psp->dtm_context.mutex); 1844 } 1845 1846 return ret; 1847 } 1848 1849 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1850 { 1851 /* 1852 * TODO: bypass the loading in sriov for now 1853 */ 1854 if (amdgpu_sriov_vf(psp->adev)) 1855 return 0; 1856 1857 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1858 } 1859 1860 static int psp_dtm_terminate(struct psp_context *psp) 1861 { 1862 int ret; 1863 1864 /* 1865 * TODO: bypass the terminate in sriov for now 1866 */ 1867 if (amdgpu_sriov_vf(psp->adev)) 1868 return 0; 1869 1870 if (!psp->dtm_context.context.initialized) 1871 return 0; 1872 1873 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1874 1875 psp->dtm_context.context.initialized = false; 1876 1877 return ret; 1878 } 1879 // DTM end 1880 1881 // RAP start 1882 static int psp_rap_initialize(struct psp_context *psp) 1883 { 1884 int ret; 1885 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1886 1887 /* 1888 * TODO: bypass the initialize in sriov for now 1889 */ 1890 if (amdgpu_sriov_vf(psp->adev)) 1891 return 0; 1892 1893 if (!psp->rap_context.context.bin_desc.size_bytes || 1894 !psp->rap_context.context.bin_desc.start_addr) { 1895 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1896 return 0; 1897 } 1898 1899 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1900 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1901 1902 if (!psp->rap_context.context.mem_context.shared_buf) { 1903 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1904 if (ret) 1905 return ret; 1906 } 1907 1908 ret = psp_ta_load(psp, &psp->rap_context.context); 1909 if (!ret) { 1910 psp->rap_context.context.initialized = true; 1911 mutex_init(&psp->rap_context.mutex); 1912 } else 1913 return ret; 1914 1915 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1916 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1917 psp_rap_terminate(psp); 1918 /* free rap shared memory */ 1919 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1920 1921 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1922 ret, status); 1923 1924 return ret; 1925 } 1926 1927 return 0; 1928 } 1929 1930 static int psp_rap_terminate(struct psp_context *psp) 1931 { 1932 int ret; 1933 1934 if (!psp->rap_context.context.initialized) 1935 return 0; 1936 1937 ret = psp_ta_unload(psp, &psp->rap_context.context); 1938 1939 psp->rap_context.context.initialized = false; 1940 1941 return ret; 1942 } 1943 1944 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1945 { 1946 struct ta_rap_shared_memory *rap_cmd; 1947 int ret = 0; 1948 1949 if (!psp->rap_context.context.initialized) 1950 return 0; 1951 1952 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1953 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1954 return -EINVAL; 1955 1956 mutex_lock(&psp->rap_context.mutex); 1957 1958 rap_cmd = (struct ta_rap_shared_memory *) 1959 psp->rap_context.context.mem_context.shared_buf; 1960 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1961 1962 rap_cmd->cmd_id = ta_cmd_id; 1963 rap_cmd->validation_method_id = METHOD_A; 1964 1965 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1966 if (ret) 1967 goto out_unlock; 1968 1969 if (status) 1970 *status = rap_cmd->rap_status; 1971 1972 out_unlock: 1973 mutex_unlock(&psp->rap_context.mutex); 1974 1975 return ret; 1976 } 1977 // RAP end 1978 1979 /* securedisplay start */ 1980 static int psp_securedisplay_initialize(struct psp_context *psp) 1981 { 1982 int ret; 1983 struct ta_securedisplay_cmd *securedisplay_cmd; 1984 1985 /* 1986 * TODO: bypass the initialize in sriov for now 1987 */ 1988 if (amdgpu_sriov_vf(psp->adev)) 1989 return 0; 1990 1991 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1992 !psp->securedisplay_context.context.bin_desc.start_addr) { 1993 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1994 return 0; 1995 } 1996 1997 psp->securedisplay_context.context.mem_context.shared_mem_size = 1998 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1999 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2000 2001 if (!psp->securedisplay_context.context.initialized) { 2002 ret = psp_ta_init_shared_buf(psp, 2003 &psp->securedisplay_context.context.mem_context); 2004 if (ret) 2005 return ret; 2006 } 2007 2008 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 2009 if (!ret) { 2010 psp->securedisplay_context.context.initialized = true; 2011 mutex_init(&psp->securedisplay_context.mutex); 2012 } else 2013 return ret; 2014 2015 mutex_lock(&psp->securedisplay_context.mutex); 2016 2017 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2018 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2019 2020 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2021 2022 mutex_unlock(&psp->securedisplay_context.mutex); 2023 2024 if (ret) { 2025 psp_securedisplay_terminate(psp); 2026 /* free securedisplay shared memory */ 2027 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 2028 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2029 return -EINVAL; 2030 } 2031 2032 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2033 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2034 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2035 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2036 /* don't try again */ 2037 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2038 } 2039 2040 return 0; 2041 } 2042 2043 static int psp_securedisplay_terminate(struct psp_context *psp) 2044 { 2045 int ret; 2046 2047 /* 2048 * TODO:bypass the terminate in sriov for now 2049 */ 2050 if (amdgpu_sriov_vf(psp->adev)) 2051 return 0; 2052 2053 if (!psp->securedisplay_context.context.initialized) 2054 return 0; 2055 2056 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 2057 2058 psp->securedisplay_context.context.initialized = false; 2059 2060 return ret; 2061 } 2062 2063 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2064 { 2065 int ret; 2066 2067 if (!psp->securedisplay_context.context.initialized) 2068 return -EINVAL; 2069 2070 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2071 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 2072 return -EINVAL; 2073 2074 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2075 2076 return ret; 2077 } 2078 /* SECUREDISPLAY end */ 2079 2080 static int psp_hw_start(struct psp_context *psp) 2081 { 2082 struct amdgpu_device *adev = psp->adev; 2083 int ret; 2084 2085 if (!amdgpu_sriov_vf(adev)) { 2086 if ((is_psp_fw_valid(psp->kdb)) && 2087 (psp->funcs->bootloader_load_kdb != NULL)) { 2088 ret = psp_bootloader_load_kdb(psp); 2089 if (ret) { 2090 DRM_ERROR("PSP load kdb failed!\n"); 2091 return ret; 2092 } 2093 } 2094 2095 if ((is_psp_fw_valid(psp->spl)) && 2096 (psp->funcs->bootloader_load_spl != NULL)) { 2097 ret = psp_bootloader_load_spl(psp); 2098 if (ret) { 2099 DRM_ERROR("PSP load spl failed!\n"); 2100 return ret; 2101 } 2102 } 2103 2104 if ((is_psp_fw_valid(psp->sys)) && 2105 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2106 ret = psp_bootloader_load_sysdrv(psp); 2107 if (ret) { 2108 DRM_ERROR("PSP load sys drv failed!\n"); 2109 return ret; 2110 } 2111 } 2112 2113 if ((is_psp_fw_valid(psp->soc_drv)) && 2114 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2115 ret = psp_bootloader_load_soc_drv(psp); 2116 if (ret) { 2117 DRM_ERROR("PSP load soc drv failed!\n"); 2118 return ret; 2119 } 2120 } 2121 2122 if ((is_psp_fw_valid(psp->intf_drv)) && 2123 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2124 ret = psp_bootloader_load_intf_drv(psp); 2125 if (ret) { 2126 DRM_ERROR("PSP load intf drv failed!\n"); 2127 return ret; 2128 } 2129 } 2130 2131 if ((is_psp_fw_valid(psp->dbg_drv)) && 2132 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2133 ret = psp_bootloader_load_dbg_drv(psp); 2134 if (ret) { 2135 DRM_ERROR("PSP load dbg drv failed!\n"); 2136 return ret; 2137 } 2138 } 2139 2140 if ((is_psp_fw_valid(psp->ras_drv)) && 2141 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2142 ret = psp_bootloader_load_ras_drv(psp); 2143 if (ret) { 2144 DRM_ERROR("PSP load ras_drv failed!\n"); 2145 return ret; 2146 } 2147 } 2148 2149 if ((is_psp_fw_valid(psp->sos)) && 2150 (psp->funcs->bootloader_load_sos != NULL)) { 2151 ret = psp_bootloader_load_sos(psp); 2152 if (ret) { 2153 DRM_ERROR("PSP load sos failed!\n"); 2154 return ret; 2155 } 2156 } 2157 } 2158 2159 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2160 if (ret) { 2161 DRM_ERROR("PSP create ring failed!\n"); 2162 return ret; 2163 } 2164 2165 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2166 goto skip_pin_bo; 2167 2168 if (!psp_boottime_tmr(psp)) { 2169 ret = psp_tmr_init(psp); 2170 if (ret) { 2171 DRM_ERROR("PSP tmr init failed!\n"); 2172 return ret; 2173 } 2174 } 2175 2176 skip_pin_bo: 2177 /* 2178 * For ASICs with DF Cstate management centralized 2179 * to PMFW, TMR setup should be performed after PMFW 2180 * loaded and before other non-psp firmware loaded. 2181 */ 2182 if (psp->pmfw_centralized_cstate_management) { 2183 ret = psp_load_smu_fw(psp); 2184 if (ret) 2185 return ret; 2186 } 2187 2188 ret = psp_tmr_load(psp); 2189 if (ret) { 2190 DRM_ERROR("PSP load tmr failed!\n"); 2191 return ret; 2192 } 2193 2194 return 0; 2195 } 2196 2197 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2198 enum psp_gfx_fw_type *type) 2199 { 2200 switch (ucode->ucode_id) { 2201 case AMDGPU_UCODE_ID_CAP: 2202 *type = GFX_FW_TYPE_CAP; 2203 break; 2204 case AMDGPU_UCODE_ID_SDMA0: 2205 *type = GFX_FW_TYPE_SDMA0; 2206 break; 2207 case AMDGPU_UCODE_ID_SDMA1: 2208 *type = GFX_FW_TYPE_SDMA1; 2209 break; 2210 case AMDGPU_UCODE_ID_SDMA2: 2211 *type = GFX_FW_TYPE_SDMA2; 2212 break; 2213 case AMDGPU_UCODE_ID_SDMA3: 2214 *type = GFX_FW_TYPE_SDMA3; 2215 break; 2216 case AMDGPU_UCODE_ID_SDMA4: 2217 *type = GFX_FW_TYPE_SDMA4; 2218 break; 2219 case AMDGPU_UCODE_ID_SDMA5: 2220 *type = GFX_FW_TYPE_SDMA5; 2221 break; 2222 case AMDGPU_UCODE_ID_SDMA6: 2223 *type = GFX_FW_TYPE_SDMA6; 2224 break; 2225 case AMDGPU_UCODE_ID_SDMA7: 2226 *type = GFX_FW_TYPE_SDMA7; 2227 break; 2228 case AMDGPU_UCODE_ID_CP_MES: 2229 *type = GFX_FW_TYPE_CP_MES; 2230 break; 2231 case AMDGPU_UCODE_ID_CP_MES_DATA: 2232 *type = GFX_FW_TYPE_MES_STACK; 2233 break; 2234 case AMDGPU_UCODE_ID_CP_MES1: 2235 *type = GFX_FW_TYPE_CP_MES_KIQ; 2236 break; 2237 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2238 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2239 break; 2240 case AMDGPU_UCODE_ID_CP_CE: 2241 *type = GFX_FW_TYPE_CP_CE; 2242 break; 2243 case AMDGPU_UCODE_ID_CP_PFP: 2244 *type = GFX_FW_TYPE_CP_PFP; 2245 break; 2246 case AMDGPU_UCODE_ID_CP_ME: 2247 *type = GFX_FW_TYPE_CP_ME; 2248 break; 2249 case AMDGPU_UCODE_ID_CP_MEC1: 2250 *type = GFX_FW_TYPE_CP_MEC; 2251 break; 2252 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2253 *type = GFX_FW_TYPE_CP_MEC_ME1; 2254 break; 2255 case AMDGPU_UCODE_ID_CP_MEC2: 2256 *type = GFX_FW_TYPE_CP_MEC; 2257 break; 2258 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2259 *type = GFX_FW_TYPE_CP_MEC_ME2; 2260 break; 2261 case AMDGPU_UCODE_ID_RLC_P: 2262 *type = GFX_FW_TYPE_RLC_P; 2263 break; 2264 case AMDGPU_UCODE_ID_RLC_V: 2265 *type = GFX_FW_TYPE_RLC_V; 2266 break; 2267 case AMDGPU_UCODE_ID_RLC_G: 2268 *type = GFX_FW_TYPE_RLC_G; 2269 break; 2270 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2271 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2272 break; 2273 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2274 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2275 break; 2276 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2277 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2278 break; 2279 case AMDGPU_UCODE_ID_RLC_IRAM: 2280 *type = GFX_FW_TYPE_RLC_IRAM; 2281 break; 2282 case AMDGPU_UCODE_ID_RLC_DRAM: 2283 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2284 break; 2285 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2286 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2287 break; 2288 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2289 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2290 break; 2291 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2292 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2293 break; 2294 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2295 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2296 break; 2297 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2298 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2299 break; 2300 case AMDGPU_UCODE_ID_SMC: 2301 *type = GFX_FW_TYPE_SMU; 2302 break; 2303 case AMDGPU_UCODE_ID_PPTABLE: 2304 *type = GFX_FW_TYPE_PPTABLE; 2305 break; 2306 case AMDGPU_UCODE_ID_UVD: 2307 *type = GFX_FW_TYPE_UVD; 2308 break; 2309 case AMDGPU_UCODE_ID_UVD1: 2310 *type = GFX_FW_TYPE_UVD1; 2311 break; 2312 case AMDGPU_UCODE_ID_VCE: 2313 *type = GFX_FW_TYPE_VCE; 2314 break; 2315 case AMDGPU_UCODE_ID_VCN: 2316 *type = GFX_FW_TYPE_VCN; 2317 break; 2318 case AMDGPU_UCODE_ID_VCN1: 2319 *type = GFX_FW_TYPE_VCN1; 2320 break; 2321 case AMDGPU_UCODE_ID_DMCU_ERAM: 2322 *type = GFX_FW_TYPE_DMCU_ERAM; 2323 break; 2324 case AMDGPU_UCODE_ID_DMCU_INTV: 2325 *type = GFX_FW_TYPE_DMCU_ISR; 2326 break; 2327 case AMDGPU_UCODE_ID_VCN0_RAM: 2328 *type = GFX_FW_TYPE_VCN0_RAM; 2329 break; 2330 case AMDGPU_UCODE_ID_VCN1_RAM: 2331 *type = GFX_FW_TYPE_VCN1_RAM; 2332 break; 2333 case AMDGPU_UCODE_ID_DMCUB: 2334 *type = GFX_FW_TYPE_DMUB; 2335 break; 2336 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2337 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2338 break; 2339 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2340 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2341 break; 2342 case AMDGPU_UCODE_ID_IMU_I: 2343 *type = GFX_FW_TYPE_IMU_I; 2344 break; 2345 case AMDGPU_UCODE_ID_IMU_D: 2346 *type = GFX_FW_TYPE_IMU_D; 2347 break; 2348 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2349 *type = GFX_FW_TYPE_RS64_PFP; 2350 break; 2351 case AMDGPU_UCODE_ID_CP_RS64_ME: 2352 *type = GFX_FW_TYPE_RS64_ME; 2353 break; 2354 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2355 *type = GFX_FW_TYPE_RS64_MEC; 2356 break; 2357 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2358 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2359 break; 2360 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2361 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2362 break; 2363 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2364 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2365 break; 2366 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2367 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2368 break; 2369 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2370 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2371 break; 2372 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2373 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2374 break; 2375 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2376 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2377 break; 2378 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2379 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2380 break; 2381 case AMDGPU_UCODE_ID_MAXIMUM: 2382 default: 2383 return -EINVAL; 2384 } 2385 2386 return 0; 2387 } 2388 2389 static void psp_print_fw_hdr(struct psp_context *psp, 2390 struct amdgpu_firmware_info *ucode) 2391 { 2392 struct amdgpu_device *adev = psp->adev; 2393 struct common_firmware_header *hdr; 2394 2395 switch (ucode->ucode_id) { 2396 case AMDGPU_UCODE_ID_SDMA0: 2397 case AMDGPU_UCODE_ID_SDMA1: 2398 case AMDGPU_UCODE_ID_SDMA2: 2399 case AMDGPU_UCODE_ID_SDMA3: 2400 case AMDGPU_UCODE_ID_SDMA4: 2401 case AMDGPU_UCODE_ID_SDMA5: 2402 case AMDGPU_UCODE_ID_SDMA6: 2403 case AMDGPU_UCODE_ID_SDMA7: 2404 hdr = (struct common_firmware_header *) 2405 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2406 amdgpu_ucode_print_sdma_hdr(hdr); 2407 break; 2408 case AMDGPU_UCODE_ID_CP_CE: 2409 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2410 amdgpu_ucode_print_gfx_hdr(hdr); 2411 break; 2412 case AMDGPU_UCODE_ID_CP_PFP: 2413 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2414 amdgpu_ucode_print_gfx_hdr(hdr); 2415 break; 2416 case AMDGPU_UCODE_ID_CP_ME: 2417 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2418 amdgpu_ucode_print_gfx_hdr(hdr); 2419 break; 2420 case AMDGPU_UCODE_ID_CP_MEC1: 2421 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2422 amdgpu_ucode_print_gfx_hdr(hdr); 2423 break; 2424 case AMDGPU_UCODE_ID_RLC_G: 2425 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2426 amdgpu_ucode_print_rlc_hdr(hdr); 2427 break; 2428 case AMDGPU_UCODE_ID_SMC: 2429 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2430 amdgpu_ucode_print_smc_hdr(hdr); 2431 break; 2432 default: 2433 break; 2434 } 2435 } 2436 2437 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2438 struct psp_gfx_cmd_resp *cmd) 2439 { 2440 int ret; 2441 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2442 2443 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2444 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2445 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2446 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2447 2448 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2449 if (ret) 2450 DRM_ERROR("Unknown firmware type\n"); 2451 2452 return ret; 2453 } 2454 2455 int psp_execute_ip_fw_load(struct psp_context *psp, 2456 struct amdgpu_firmware_info *ucode) 2457 { 2458 int ret = 0; 2459 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2460 2461 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2462 if (!ret) { 2463 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2464 psp->fence_buf_mc_addr); 2465 } 2466 2467 release_psp_cmd_buf(psp); 2468 2469 return ret; 2470 } 2471 2472 static int psp_load_smu_fw(struct psp_context *psp) 2473 { 2474 int ret; 2475 struct amdgpu_device *adev = psp->adev; 2476 struct amdgpu_firmware_info *ucode = 2477 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2478 struct amdgpu_ras *ras = psp->ras_context.ras; 2479 2480 /* 2481 * Skip SMU FW reloading in case of using BACO for runpm only, 2482 * as SMU is always alive. 2483 */ 2484 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)) 2485 return 0; 2486 2487 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2488 return 0; 2489 2490 if ((amdgpu_in_reset(adev) && 2491 ras && adev->ras_enabled && 2492 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2493 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2494 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2495 if (ret) 2496 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2497 } 2498 2499 ret = psp_execute_ip_fw_load(psp, ucode); 2500 2501 if (ret) 2502 DRM_ERROR("PSP load smu failed!\n"); 2503 2504 return ret; 2505 } 2506 2507 static bool fw_load_skip_check(struct psp_context *psp, 2508 struct amdgpu_firmware_info *ucode) 2509 { 2510 if (!ucode->fw || !ucode->ucode_size) 2511 return true; 2512 2513 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2514 (psp_smu_reload_quirk(psp) || 2515 psp->autoload_supported || 2516 psp->pmfw_centralized_cstate_management)) 2517 return true; 2518 2519 if (amdgpu_sriov_vf(psp->adev) && 2520 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 2521 return true; 2522 2523 if (psp->autoload_supported && 2524 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2525 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2526 /* skip mec JT when autoload is enabled */ 2527 return true; 2528 2529 return false; 2530 } 2531 2532 int psp_load_fw_list(struct psp_context *psp, 2533 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2534 { 2535 int ret = 0, i; 2536 struct amdgpu_firmware_info *ucode; 2537 2538 for (i = 0; i < ucode_count; ++i) { 2539 ucode = ucode_list[i]; 2540 psp_print_fw_hdr(psp, ucode); 2541 ret = psp_execute_ip_fw_load(psp, ucode); 2542 if (ret) 2543 return ret; 2544 } 2545 return ret; 2546 } 2547 2548 static int psp_load_non_psp_fw(struct psp_context *psp) 2549 { 2550 int i, ret; 2551 struct amdgpu_firmware_info *ucode; 2552 struct amdgpu_device *adev = psp->adev; 2553 2554 if (psp->autoload_supported && 2555 !psp->pmfw_centralized_cstate_management) { 2556 ret = psp_load_smu_fw(psp); 2557 if (ret) 2558 return ret; 2559 } 2560 2561 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2562 ucode = &adev->firmware.ucode[i]; 2563 2564 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2565 !fw_load_skip_check(psp, ucode)) { 2566 ret = psp_load_smu_fw(psp); 2567 if (ret) 2568 return ret; 2569 continue; 2570 } 2571 2572 if (fw_load_skip_check(psp, ucode)) 2573 continue; 2574 2575 if (psp->autoload_supported && 2576 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2577 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2578 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2579 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2580 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2581 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2582 /* PSP only receive one SDMA fw for sienna_cichlid, 2583 * as all four sdma fw are same 2584 */ 2585 continue; 2586 2587 psp_print_fw_hdr(psp, ucode); 2588 2589 ret = psp_execute_ip_fw_load(psp, ucode); 2590 if (ret) 2591 return ret; 2592 2593 /* Start rlc autoload after psp recieved all the gfx firmware */ 2594 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2595 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 2596 ret = psp_rlc_autoload_start(psp); 2597 if (ret) { 2598 DRM_ERROR("Failed to start rlc autoload\n"); 2599 return ret; 2600 } 2601 } 2602 } 2603 2604 return 0; 2605 } 2606 2607 static int psp_load_fw(struct amdgpu_device *adev) 2608 { 2609 int ret; 2610 struct psp_context *psp = &adev->psp; 2611 2612 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2613 /* should not destroy ring, only stop */ 2614 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2615 } else { 2616 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2617 2618 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2619 if (ret) { 2620 DRM_ERROR("PSP ring init failed!\n"); 2621 goto failed; 2622 } 2623 } 2624 2625 ret = psp_hw_start(psp); 2626 if (ret) 2627 goto failed; 2628 2629 ret = psp_load_non_psp_fw(psp); 2630 if (ret) 2631 goto failed1; 2632 2633 ret = psp_asd_initialize(psp); 2634 if (ret) { 2635 DRM_ERROR("PSP load asd failed!\n"); 2636 goto failed1; 2637 } 2638 2639 ret = psp_rl_load(adev); 2640 if (ret) { 2641 DRM_ERROR("PSP load RL failed!\n"); 2642 goto failed1; 2643 } 2644 2645 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2646 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2647 ret = psp_xgmi_initialize(psp, false, true); 2648 /* Warning the XGMI seesion initialize failure 2649 * Instead of stop driver initialization 2650 */ 2651 if (ret) 2652 dev_err(psp->adev->dev, 2653 "XGMI: Failed to initialize XGMI session\n"); 2654 } 2655 } 2656 2657 if (psp->ta_fw) { 2658 ret = psp_ras_initialize(psp); 2659 if (ret) 2660 dev_err(psp->adev->dev, 2661 "RAS: Failed to initialize RAS\n"); 2662 2663 ret = psp_hdcp_initialize(psp); 2664 if (ret) 2665 dev_err(psp->adev->dev, 2666 "HDCP: Failed to initialize HDCP\n"); 2667 2668 ret = psp_dtm_initialize(psp); 2669 if (ret) 2670 dev_err(psp->adev->dev, 2671 "DTM: Failed to initialize DTM\n"); 2672 2673 ret = psp_rap_initialize(psp); 2674 if (ret) 2675 dev_err(psp->adev->dev, 2676 "RAP: Failed to initialize RAP\n"); 2677 2678 ret = psp_securedisplay_initialize(psp); 2679 if (ret) 2680 dev_err(psp->adev->dev, 2681 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2682 } 2683 2684 return 0; 2685 2686 failed1: 2687 psp_free_shared_bufs(psp); 2688 failed: 2689 /* 2690 * all cleanup jobs (xgmi terminate, ras terminate, 2691 * ring destroy, cmd/fence/fw buffers destory, 2692 * psp->cmd destory) are delayed to psp_hw_fini 2693 */ 2694 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2695 return ret; 2696 } 2697 2698 static int psp_hw_init(void *handle) 2699 { 2700 int ret; 2701 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2702 2703 mutex_lock(&adev->firmware.mutex); 2704 /* 2705 * This sequence is just used on hw_init only once, no need on 2706 * resume. 2707 */ 2708 ret = amdgpu_ucode_init_bo(adev); 2709 if (ret) 2710 goto failed; 2711 2712 ret = psp_load_fw(adev); 2713 if (ret) { 2714 DRM_ERROR("PSP firmware loading failed\n"); 2715 goto failed; 2716 } 2717 2718 mutex_unlock(&adev->firmware.mutex); 2719 return 0; 2720 2721 failed: 2722 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2723 mutex_unlock(&adev->firmware.mutex); 2724 return -EINVAL; 2725 } 2726 2727 static int psp_hw_fini(void *handle) 2728 { 2729 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2730 struct psp_context *psp = &adev->psp; 2731 2732 if (psp->ta_fw) { 2733 psp_ras_terminate(psp); 2734 psp_securedisplay_terminate(psp); 2735 psp_rap_terminate(psp); 2736 psp_dtm_terminate(psp); 2737 psp_hdcp_terminate(psp); 2738 2739 if (adev->gmc.xgmi.num_physical_nodes > 1) 2740 psp_xgmi_terminate(psp); 2741 } 2742 2743 psp_asd_terminate(psp); 2744 psp_tmr_terminate(psp); 2745 2746 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2747 2748 return 0; 2749 } 2750 2751 static int psp_suspend(void *handle) 2752 { 2753 int ret = 0; 2754 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2755 struct psp_context *psp = &adev->psp; 2756 2757 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2758 psp->xgmi_context.context.initialized) { 2759 ret = psp_xgmi_terminate(psp); 2760 if (ret) { 2761 DRM_ERROR("Failed to terminate xgmi ta\n"); 2762 goto out; 2763 } 2764 } 2765 2766 if (psp->ta_fw) { 2767 ret = psp_ras_terminate(psp); 2768 if (ret) { 2769 DRM_ERROR("Failed to terminate ras ta\n"); 2770 goto out; 2771 } 2772 ret = psp_hdcp_terminate(psp); 2773 if (ret) { 2774 DRM_ERROR("Failed to terminate hdcp ta\n"); 2775 goto out; 2776 } 2777 ret = psp_dtm_terminate(psp); 2778 if (ret) { 2779 DRM_ERROR("Failed to terminate dtm ta\n"); 2780 goto out; 2781 } 2782 ret = psp_rap_terminate(psp); 2783 if (ret) { 2784 DRM_ERROR("Failed to terminate rap ta\n"); 2785 goto out; 2786 } 2787 ret = psp_securedisplay_terminate(psp); 2788 if (ret) { 2789 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2790 goto out; 2791 } 2792 } 2793 2794 ret = psp_asd_terminate(psp); 2795 if (ret) { 2796 DRM_ERROR("Failed to terminate asd\n"); 2797 goto out; 2798 } 2799 2800 ret = psp_tmr_terminate(psp); 2801 if (ret) { 2802 DRM_ERROR("Failed to terminate tmr\n"); 2803 goto out; 2804 } 2805 2806 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2807 if (ret) 2808 DRM_ERROR("PSP ring stop failed\n"); 2809 2810 out: 2811 return ret; 2812 } 2813 2814 static int psp_resume(void *handle) 2815 { 2816 int ret; 2817 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2818 struct psp_context *psp = &adev->psp; 2819 2820 DRM_INFO("PSP is resuming...\n"); 2821 2822 if (psp->mem_train_ctx.enable_mem_training) { 2823 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2824 if (ret) { 2825 DRM_ERROR("Failed to process memory training!\n"); 2826 return ret; 2827 } 2828 } 2829 2830 mutex_lock(&adev->firmware.mutex); 2831 2832 ret = psp_hw_start(psp); 2833 if (ret) 2834 goto failed; 2835 2836 ret = psp_load_non_psp_fw(psp); 2837 if (ret) 2838 goto failed; 2839 2840 ret = psp_asd_initialize(psp); 2841 if (ret) { 2842 DRM_ERROR("PSP load asd failed!\n"); 2843 goto failed; 2844 } 2845 2846 ret = psp_rl_load(adev); 2847 if (ret) { 2848 dev_err(adev->dev, "PSP load RL failed!\n"); 2849 goto failed; 2850 } 2851 2852 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2853 ret = psp_xgmi_initialize(psp, false, true); 2854 /* Warning the XGMI seesion initialize failure 2855 * Instead of stop driver initialization 2856 */ 2857 if (ret) 2858 dev_err(psp->adev->dev, 2859 "XGMI: Failed to initialize XGMI session\n"); 2860 } 2861 2862 if (psp->ta_fw) { 2863 ret = psp_ras_initialize(psp); 2864 if (ret) 2865 dev_err(psp->adev->dev, 2866 "RAS: Failed to initialize RAS\n"); 2867 2868 ret = psp_hdcp_initialize(psp); 2869 if (ret) 2870 dev_err(psp->adev->dev, 2871 "HDCP: Failed to initialize HDCP\n"); 2872 2873 ret = psp_dtm_initialize(psp); 2874 if (ret) 2875 dev_err(psp->adev->dev, 2876 "DTM: Failed to initialize DTM\n"); 2877 2878 ret = psp_rap_initialize(psp); 2879 if (ret) 2880 dev_err(psp->adev->dev, 2881 "RAP: Failed to initialize RAP\n"); 2882 2883 ret = psp_securedisplay_initialize(psp); 2884 if (ret) 2885 dev_err(psp->adev->dev, 2886 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2887 } 2888 2889 mutex_unlock(&adev->firmware.mutex); 2890 2891 return 0; 2892 2893 failed: 2894 DRM_ERROR("PSP resume failed\n"); 2895 mutex_unlock(&adev->firmware.mutex); 2896 return ret; 2897 } 2898 2899 int psp_gpu_reset(struct amdgpu_device *adev) 2900 { 2901 int ret; 2902 2903 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2904 return 0; 2905 2906 mutex_lock(&adev->psp.mutex); 2907 ret = psp_mode1_reset(&adev->psp); 2908 mutex_unlock(&adev->psp.mutex); 2909 2910 return ret; 2911 } 2912 2913 int psp_rlc_autoload_start(struct psp_context *psp) 2914 { 2915 int ret; 2916 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2917 2918 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2919 2920 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2921 psp->fence_buf_mc_addr); 2922 2923 release_psp_cmd_buf(psp); 2924 2925 return ret; 2926 } 2927 2928 int psp_ring_cmd_submit(struct psp_context *psp, 2929 uint64_t cmd_buf_mc_addr, 2930 uint64_t fence_mc_addr, 2931 int index) 2932 { 2933 unsigned int psp_write_ptr_reg = 0; 2934 struct psp_gfx_rb_frame *write_frame; 2935 struct psp_ring *ring = &psp->km_ring; 2936 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2937 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2938 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2939 struct amdgpu_device *adev = psp->adev; 2940 uint32_t ring_size_dw = ring->ring_size / 4; 2941 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2942 2943 /* KM (GPCOM) prepare write pointer */ 2944 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2945 2946 /* Update KM RB frame pointer to new frame */ 2947 /* write_frame ptr increments by size of rb_frame in bytes */ 2948 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2949 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2950 write_frame = ring_buffer_start; 2951 else 2952 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2953 /* Check invalid write_frame ptr address */ 2954 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2955 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2956 ring_buffer_start, ring_buffer_end, write_frame); 2957 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2958 return -EINVAL; 2959 } 2960 2961 /* Initialize KM RB frame */ 2962 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2963 2964 /* Update KM RB frame */ 2965 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2966 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2967 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2968 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2969 write_frame->fence_value = index; 2970 amdgpu_device_flush_hdp(adev, NULL); 2971 2972 /* Update the write Pointer in DWORDs */ 2973 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2974 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2975 return 0; 2976 } 2977 2978 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 2979 { 2980 struct amdgpu_device *adev = psp->adev; 2981 char fw_name[PSP_FW_NAME_LEN]; 2982 const struct psp_firmware_header_v1_0 *asd_hdr; 2983 int err = 0; 2984 2985 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2986 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name); 2987 if (err) 2988 goto out; 2989 2990 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2991 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2992 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2993 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2994 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2995 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2996 return 0; 2997 out: 2998 amdgpu_ucode_release(&adev->psp.asd_fw); 2999 return err; 3000 } 3001 3002 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 3003 { 3004 struct amdgpu_device *adev = psp->adev; 3005 char fw_name[PSP_FW_NAME_LEN]; 3006 const struct psp_firmware_header_v1_0 *toc_hdr; 3007 int err = 0; 3008 3009 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 3010 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name); 3011 if (err) 3012 goto out; 3013 3014 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3015 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3016 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3017 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3018 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3019 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3020 return 0; 3021 out: 3022 amdgpu_ucode_release(&adev->psp.toc_fw); 3023 return err; 3024 } 3025 3026 static int parse_sos_bin_descriptor(struct psp_context *psp, 3027 const struct psp_fw_bin_desc *desc, 3028 const struct psp_firmware_header_v2_0 *sos_hdr) 3029 { 3030 uint8_t *ucode_start_addr = NULL; 3031 3032 if (!psp || !desc || !sos_hdr) 3033 return -EINVAL; 3034 3035 ucode_start_addr = (uint8_t *)sos_hdr + 3036 le32_to_cpu(desc->offset_bytes) + 3037 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3038 3039 switch (desc->fw_type) { 3040 case PSP_FW_TYPE_PSP_SOS: 3041 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3042 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3043 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3044 psp->sos.start_addr = ucode_start_addr; 3045 break; 3046 case PSP_FW_TYPE_PSP_SYS_DRV: 3047 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3048 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3049 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3050 psp->sys.start_addr = ucode_start_addr; 3051 break; 3052 case PSP_FW_TYPE_PSP_KDB: 3053 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3054 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3055 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3056 psp->kdb.start_addr = ucode_start_addr; 3057 break; 3058 case PSP_FW_TYPE_PSP_TOC: 3059 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3060 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3061 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3062 psp->toc.start_addr = ucode_start_addr; 3063 break; 3064 case PSP_FW_TYPE_PSP_SPL: 3065 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3066 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3067 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3068 psp->spl.start_addr = ucode_start_addr; 3069 break; 3070 case PSP_FW_TYPE_PSP_RL: 3071 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3072 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3073 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3074 psp->rl.start_addr = ucode_start_addr; 3075 break; 3076 case PSP_FW_TYPE_PSP_SOC_DRV: 3077 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3078 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3079 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3080 psp->soc_drv.start_addr = ucode_start_addr; 3081 break; 3082 case PSP_FW_TYPE_PSP_INTF_DRV: 3083 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3084 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3085 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3086 psp->intf_drv.start_addr = ucode_start_addr; 3087 break; 3088 case PSP_FW_TYPE_PSP_DBG_DRV: 3089 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3090 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3091 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3092 psp->dbg_drv.start_addr = ucode_start_addr; 3093 break; 3094 case PSP_FW_TYPE_PSP_RAS_DRV: 3095 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3096 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3097 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3098 psp->ras_drv.start_addr = ucode_start_addr; 3099 break; 3100 default: 3101 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3102 break; 3103 } 3104 3105 return 0; 3106 } 3107 3108 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3109 { 3110 const struct psp_firmware_header_v1_0 *sos_hdr; 3111 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3112 uint8_t *ucode_array_start_addr; 3113 3114 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3115 ucode_array_start_addr = (uint8_t *)sos_hdr + 3116 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3117 3118 if (adev->gmc.xgmi.connected_to_cpu || 3119 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3120 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3121 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3122 3123 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3124 adev->psp.sys.start_addr = ucode_array_start_addr; 3125 3126 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3127 adev->psp.sos.start_addr = ucode_array_start_addr + 3128 le32_to_cpu(sos_hdr->sos.offset_bytes); 3129 } else { 3130 /* Load alternate PSP SOS FW */ 3131 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3132 3133 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3134 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3135 3136 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3137 adev->psp.sys.start_addr = ucode_array_start_addr + 3138 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3139 3140 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3141 adev->psp.sos.start_addr = ucode_array_start_addr + 3142 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3143 } 3144 3145 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3146 dev_warn(adev->dev, "PSP SOS FW not available"); 3147 return -EINVAL; 3148 } 3149 3150 return 0; 3151 } 3152 3153 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 3154 { 3155 struct amdgpu_device *adev = psp->adev; 3156 char fw_name[PSP_FW_NAME_LEN]; 3157 const struct psp_firmware_header_v1_0 *sos_hdr; 3158 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3159 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3160 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3161 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3162 int err = 0; 3163 uint8_t *ucode_array_start_addr; 3164 int fw_index = 0; 3165 3166 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3167 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name); 3168 if (err) 3169 goto out; 3170 3171 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3172 ucode_array_start_addr = (uint8_t *)sos_hdr + 3173 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3174 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3175 3176 switch (sos_hdr->header.header_version_major) { 3177 case 1: 3178 err = psp_init_sos_base_fw(adev); 3179 if (err) 3180 goto out; 3181 3182 if (sos_hdr->header.header_version_minor == 1) { 3183 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3184 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3185 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3186 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3187 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3188 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3189 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3190 } 3191 if (sos_hdr->header.header_version_minor == 2) { 3192 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3193 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3194 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3195 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3196 } 3197 if (sos_hdr->header.header_version_minor == 3) { 3198 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3199 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3200 adev->psp.toc.start_addr = ucode_array_start_addr + 3201 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3202 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3203 adev->psp.kdb.start_addr = ucode_array_start_addr + 3204 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3205 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3206 adev->psp.spl.start_addr = ucode_array_start_addr + 3207 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3208 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3209 adev->psp.rl.start_addr = ucode_array_start_addr + 3210 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3211 } 3212 break; 3213 case 2: 3214 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3215 3216 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3217 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3218 err = -EINVAL; 3219 goto out; 3220 } 3221 3222 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3223 err = parse_sos_bin_descriptor(psp, 3224 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3225 sos_hdr_v2_0); 3226 if (err) 3227 goto out; 3228 } 3229 break; 3230 default: 3231 dev_err(adev->dev, 3232 "unsupported psp sos firmware\n"); 3233 err = -EINVAL; 3234 goto out; 3235 } 3236 3237 return 0; 3238 out: 3239 amdgpu_ucode_release(&adev->psp.sos_fw); 3240 3241 return err; 3242 } 3243 3244 static int parse_ta_bin_descriptor(struct psp_context *psp, 3245 const struct psp_fw_bin_desc *desc, 3246 const struct ta_firmware_header_v2_0 *ta_hdr) 3247 { 3248 uint8_t *ucode_start_addr = NULL; 3249 3250 if (!psp || !desc || !ta_hdr) 3251 return -EINVAL; 3252 3253 ucode_start_addr = (uint8_t *)ta_hdr + 3254 le32_to_cpu(desc->offset_bytes) + 3255 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3256 3257 switch (desc->fw_type) { 3258 case TA_FW_TYPE_PSP_ASD: 3259 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3260 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3261 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3262 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3263 break; 3264 case TA_FW_TYPE_PSP_XGMI: 3265 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3266 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3267 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3268 break; 3269 case TA_FW_TYPE_PSP_RAS: 3270 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3271 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3272 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3273 break; 3274 case TA_FW_TYPE_PSP_HDCP: 3275 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3276 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3277 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3278 break; 3279 case TA_FW_TYPE_PSP_DTM: 3280 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3281 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3282 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3283 break; 3284 case TA_FW_TYPE_PSP_RAP: 3285 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3286 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3287 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3288 break; 3289 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3290 psp->securedisplay_context.context.bin_desc.fw_version = 3291 le32_to_cpu(desc->fw_version); 3292 psp->securedisplay_context.context.bin_desc.size_bytes = 3293 le32_to_cpu(desc->size_bytes); 3294 psp->securedisplay_context.context.bin_desc.start_addr = 3295 ucode_start_addr; 3296 break; 3297 default: 3298 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3299 break; 3300 } 3301 3302 return 0; 3303 } 3304 3305 static int parse_ta_v1_microcode(struct psp_context *psp) 3306 { 3307 const struct ta_firmware_header_v1_0 *ta_hdr; 3308 struct amdgpu_device *adev = psp->adev; 3309 3310 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 3311 3312 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 3313 return -EINVAL; 3314 3315 adev->psp.xgmi_context.context.bin_desc.fw_version = 3316 le32_to_cpu(ta_hdr->xgmi.fw_version); 3317 adev->psp.xgmi_context.context.bin_desc.size_bytes = 3318 le32_to_cpu(ta_hdr->xgmi.size_bytes); 3319 adev->psp.xgmi_context.context.bin_desc.start_addr = 3320 (uint8_t *)ta_hdr + 3321 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3322 3323 adev->psp.ras_context.context.bin_desc.fw_version = 3324 le32_to_cpu(ta_hdr->ras.fw_version); 3325 adev->psp.ras_context.context.bin_desc.size_bytes = 3326 le32_to_cpu(ta_hdr->ras.size_bytes); 3327 adev->psp.ras_context.context.bin_desc.start_addr = 3328 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 3329 le32_to_cpu(ta_hdr->ras.offset_bytes); 3330 3331 adev->psp.hdcp_context.context.bin_desc.fw_version = 3332 le32_to_cpu(ta_hdr->hdcp.fw_version); 3333 adev->psp.hdcp_context.context.bin_desc.size_bytes = 3334 le32_to_cpu(ta_hdr->hdcp.size_bytes); 3335 adev->psp.hdcp_context.context.bin_desc.start_addr = 3336 (uint8_t *)ta_hdr + 3337 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3338 3339 adev->psp.dtm_context.context.bin_desc.fw_version = 3340 le32_to_cpu(ta_hdr->dtm.fw_version); 3341 adev->psp.dtm_context.context.bin_desc.size_bytes = 3342 le32_to_cpu(ta_hdr->dtm.size_bytes); 3343 adev->psp.dtm_context.context.bin_desc.start_addr = 3344 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3345 le32_to_cpu(ta_hdr->dtm.offset_bytes); 3346 3347 adev->psp.securedisplay_context.context.bin_desc.fw_version = 3348 le32_to_cpu(ta_hdr->securedisplay.fw_version); 3349 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 3350 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 3351 adev->psp.securedisplay_context.context.bin_desc.start_addr = 3352 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3353 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 3354 3355 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 3356 3357 return 0; 3358 } 3359 3360 static int parse_ta_v2_microcode(struct psp_context *psp) 3361 { 3362 const struct ta_firmware_header_v2_0 *ta_hdr; 3363 struct amdgpu_device *adev = psp->adev; 3364 int err = 0; 3365 int ta_index = 0; 3366 3367 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3368 3369 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 3370 return -EINVAL; 3371 3372 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3373 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3374 return -EINVAL; 3375 } 3376 3377 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3378 err = parse_ta_bin_descriptor(psp, 3379 &ta_hdr->ta_fw_bin[ta_index], 3380 ta_hdr); 3381 if (err) 3382 return err; 3383 } 3384 3385 return 0; 3386 } 3387 3388 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 3389 { 3390 const struct common_firmware_header *hdr; 3391 struct amdgpu_device *adev = psp->adev; 3392 char fw_name[PSP_FW_NAME_LEN]; 3393 int err; 3394 3395 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3396 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name); 3397 if (err) 3398 return err; 3399 3400 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 3401 switch (le16_to_cpu(hdr->header_version_major)) { 3402 case 1: 3403 err = parse_ta_v1_microcode(psp); 3404 break; 3405 case 2: 3406 err = parse_ta_v2_microcode(psp); 3407 break; 3408 default: 3409 dev_err(adev->dev, "unsupported TA header version\n"); 3410 err = -EINVAL; 3411 } 3412 3413 if (err) 3414 amdgpu_ucode_release(&adev->psp.ta_fw); 3415 3416 return err; 3417 } 3418 3419 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 3420 { 3421 struct amdgpu_device *adev = psp->adev; 3422 char fw_name[PSP_FW_NAME_LEN]; 3423 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3424 struct amdgpu_firmware_info *info = NULL; 3425 int err = 0; 3426 3427 if (!amdgpu_sriov_vf(adev)) { 3428 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3429 return -EINVAL; 3430 } 3431 3432 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3433 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name); 3434 if (err) { 3435 if (err == -ENODEV) { 3436 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3437 err = 0; 3438 goto out; 3439 } 3440 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3441 } 3442 3443 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3444 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3445 info->fw = adev->psp.cap_fw; 3446 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3447 adev->psp.cap_fw->data; 3448 adev->firmware.fw_size += ALIGN( 3449 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3450 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3451 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3452 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3453 3454 return 0; 3455 3456 out: 3457 amdgpu_ucode_release(&adev->psp.cap_fw); 3458 return err; 3459 } 3460 3461 static int psp_set_clockgating_state(void *handle, 3462 enum amd_clockgating_state state) 3463 { 3464 return 0; 3465 } 3466 3467 static int psp_set_powergating_state(void *handle, 3468 enum amd_powergating_state state) 3469 { 3470 return 0; 3471 } 3472 3473 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3474 struct device_attribute *attr, 3475 char *buf) 3476 { 3477 struct drm_device *ddev = dev_get_drvdata(dev); 3478 struct amdgpu_device *adev = drm_to_adev(ddev); 3479 uint32_t fw_ver; 3480 int ret; 3481 3482 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3483 DRM_INFO("PSP block is not ready yet."); 3484 return -EBUSY; 3485 } 3486 3487 mutex_lock(&adev->psp.mutex); 3488 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3489 mutex_unlock(&adev->psp.mutex); 3490 3491 if (ret) { 3492 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3493 return ret; 3494 } 3495 3496 return sysfs_emit(buf, "%x\n", fw_ver); 3497 } 3498 3499 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3500 struct device_attribute *attr, 3501 const char *buf, 3502 size_t count) 3503 { 3504 struct drm_device *ddev = dev_get_drvdata(dev); 3505 struct amdgpu_device *adev = drm_to_adev(ddev); 3506 int ret, idx; 3507 char fw_name[100]; 3508 const struct firmware *usbc_pd_fw; 3509 struct amdgpu_bo *fw_buf_bo = NULL; 3510 uint64_t fw_pri_mc_addr; 3511 void *fw_pri_cpu_addr; 3512 3513 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3514 DRM_INFO("PSP block is not ready yet."); 3515 return -EBUSY; 3516 } 3517 3518 if (!drm_dev_enter(ddev, &idx)) 3519 return -ENODEV; 3520 3521 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3522 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3523 if (ret) 3524 goto fail; 3525 3526 /* LFB address which is aligned to 1MB boundary per PSP request */ 3527 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3528 AMDGPU_GEM_DOMAIN_VRAM | 3529 AMDGPU_GEM_DOMAIN_GTT, 3530 &fw_buf_bo, &fw_pri_mc_addr, 3531 &fw_pri_cpu_addr); 3532 if (ret) 3533 goto rel_buf; 3534 3535 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3536 3537 mutex_lock(&adev->psp.mutex); 3538 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3539 mutex_unlock(&adev->psp.mutex); 3540 3541 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3542 3543 rel_buf: 3544 release_firmware(usbc_pd_fw); 3545 fail: 3546 if (ret) { 3547 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3548 count = ret; 3549 } 3550 3551 drm_dev_exit(idx); 3552 return count; 3553 } 3554 3555 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3556 { 3557 int idx; 3558 3559 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3560 return; 3561 3562 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3563 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3564 3565 drm_dev_exit(idx); 3566 } 3567 3568 /** 3569 * DOC: usbc_pd_fw 3570 * Reading from this file will retrieve the USB-C PD firmware version. Writing to 3571 * this file will trigger the update process. 3572 */ 3573 static DEVICE_ATTR(usbc_pd_fw, 0644, 3574 psp_usbc_pd_fw_sysfs_read, 3575 psp_usbc_pd_fw_sysfs_write); 3576 3577 int is_psp_fw_valid(struct psp_bin_desc bin) 3578 { 3579 return bin.size_bytes; 3580 } 3581 3582 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3583 struct bin_attribute *bin_attr, 3584 char *buffer, loff_t pos, size_t count) 3585 { 3586 struct device *dev = kobj_to_dev(kobj); 3587 struct drm_device *ddev = dev_get_drvdata(dev); 3588 struct amdgpu_device *adev = drm_to_adev(ddev); 3589 3590 adev->psp.vbflash_done = false; 3591 3592 /* Safeguard against memory drain */ 3593 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3594 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B); 3595 kvfree(adev->psp.vbflash_tmp_buf); 3596 adev->psp.vbflash_tmp_buf = NULL; 3597 adev->psp.vbflash_image_size = 0; 3598 return -ENOMEM; 3599 } 3600 3601 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3602 if (!adev->psp.vbflash_tmp_buf) { 3603 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3604 if (!adev->psp.vbflash_tmp_buf) 3605 return -ENOMEM; 3606 } 3607 3608 mutex_lock(&adev->psp.mutex); 3609 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3610 adev->psp.vbflash_image_size += count; 3611 mutex_unlock(&adev->psp.mutex); 3612 3613 dev_dbg(adev->dev, "IFWI staged for update"); 3614 3615 return count; 3616 } 3617 3618 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3619 struct bin_attribute *bin_attr, char *buffer, 3620 loff_t pos, size_t count) 3621 { 3622 struct device *dev = kobj_to_dev(kobj); 3623 struct drm_device *ddev = dev_get_drvdata(dev); 3624 struct amdgpu_device *adev = drm_to_adev(ddev); 3625 struct amdgpu_bo *fw_buf_bo = NULL; 3626 uint64_t fw_pri_mc_addr; 3627 void *fw_pri_cpu_addr; 3628 int ret; 3629 3630 if (adev->psp.vbflash_image_size == 0) 3631 return -EINVAL; 3632 3633 dev_dbg(adev->dev, "PSP IFWI flash process initiated"); 3634 3635 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3636 AMDGPU_GPU_PAGE_SIZE, 3637 AMDGPU_GEM_DOMAIN_VRAM, 3638 &fw_buf_bo, 3639 &fw_pri_mc_addr, 3640 &fw_pri_cpu_addr); 3641 if (ret) 3642 goto rel_buf; 3643 3644 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3645 3646 mutex_lock(&adev->psp.mutex); 3647 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3648 mutex_unlock(&adev->psp.mutex); 3649 3650 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3651 3652 rel_buf: 3653 kvfree(adev->psp.vbflash_tmp_buf); 3654 adev->psp.vbflash_tmp_buf = NULL; 3655 adev->psp.vbflash_image_size = 0; 3656 3657 if (ret) { 3658 dev_err(adev->dev, "Failed to load IFWI, err = %d", ret); 3659 return ret; 3660 } 3661 3662 dev_dbg(adev->dev, "PSP IFWI flash process done"); 3663 return 0; 3664 } 3665 3666 /** 3667 * DOC: psp_vbflash 3668 * Writing to this file will stage an IFWI for update. Reading from this file 3669 * will trigger the update process. 3670 */ 3671 static struct bin_attribute psp_vbflash_bin_attr = { 3672 .attr = {.name = "psp_vbflash", .mode = 0660}, 3673 .size = 0, 3674 .write = amdgpu_psp_vbflash_write, 3675 .read = amdgpu_psp_vbflash_read, 3676 }; 3677 3678 /** 3679 * DOC: psp_vbflash_status 3680 * The status of the flash process. 3681 * 0: IFWI flash not complete. 3682 * 1: IFWI flash complete. 3683 */ 3684 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 3685 struct device_attribute *attr, 3686 char *buf) 3687 { 3688 struct drm_device *ddev = dev_get_drvdata(dev); 3689 struct amdgpu_device *adev = drm_to_adev(ddev); 3690 uint32_t vbflash_status; 3691 3692 vbflash_status = psp_vbflash_status(&adev->psp); 3693 if (!adev->psp.vbflash_done) 3694 vbflash_status = 0; 3695 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 3696 vbflash_status = 1; 3697 3698 return sysfs_emit(buf, "0x%x\n", vbflash_status); 3699 } 3700 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 3701 3702 static struct bin_attribute *bin_flash_attrs[] = { 3703 &psp_vbflash_bin_attr, 3704 NULL 3705 }; 3706 3707 static struct attribute *flash_attrs[] = { 3708 &dev_attr_psp_vbflash_status.attr, 3709 &dev_attr_usbc_pd_fw.attr, 3710 NULL 3711 }; 3712 3713 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 3714 { 3715 struct device *dev = kobj_to_dev(kobj); 3716 struct drm_device *ddev = dev_get_drvdata(dev); 3717 struct amdgpu_device *adev = drm_to_adev(ddev); 3718 3719 if (attr == &dev_attr_usbc_pd_fw.attr) 3720 return adev->psp.sup_pd_fw_up ? 0660 : 0; 3721 3722 return adev->psp.sup_ifwi_up ? 0440 : 0; 3723 } 3724 3725 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, 3726 struct bin_attribute *attr, 3727 int idx) 3728 { 3729 struct device *dev = kobj_to_dev(kobj); 3730 struct drm_device *ddev = dev_get_drvdata(dev); 3731 struct amdgpu_device *adev = drm_to_adev(ddev); 3732 3733 return adev->psp.sup_ifwi_up ? 0660 : 0; 3734 } 3735 3736 const struct attribute_group amdgpu_flash_attr_group = { 3737 .attrs = flash_attrs, 3738 .bin_attrs = bin_flash_attrs, 3739 .is_bin_visible = amdgpu_bin_flash_attr_is_visible, 3740 .is_visible = amdgpu_flash_attr_is_visible, 3741 }; 3742 3743 const struct amd_ip_funcs psp_ip_funcs = { 3744 .name = "psp", 3745 .early_init = psp_early_init, 3746 .late_init = NULL, 3747 .sw_init = psp_sw_init, 3748 .sw_fini = psp_sw_fini, 3749 .hw_init = psp_hw_init, 3750 .hw_fini = psp_hw_fini, 3751 .suspend = psp_suspend, 3752 .resume = psp_resume, 3753 .is_idle = NULL, 3754 .check_soft_reset = NULL, 3755 .wait_for_idle = NULL, 3756 .soft_reset = NULL, 3757 .set_clockgating_state = psp_set_clockgating_state, 3758 .set_powergating_state = psp_set_powergating_state, 3759 }; 3760 3761 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 3762 .type = AMD_IP_BLOCK_TYPE_PSP, 3763 .major = 3, 3764 .minor = 1, 3765 .rev = 0, 3766 .funcs = &psp_ip_funcs, 3767 }; 3768 3769 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 3770 .type = AMD_IP_BLOCK_TYPE_PSP, 3771 .major = 10, 3772 .minor = 0, 3773 .rev = 0, 3774 .funcs = &psp_ip_funcs, 3775 }; 3776 3777 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 3778 .type = AMD_IP_BLOCK_TYPE_PSP, 3779 .major = 11, 3780 .minor = 0, 3781 .rev = 0, 3782 .funcs = &psp_ip_funcs, 3783 }; 3784 3785 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3786 .type = AMD_IP_BLOCK_TYPE_PSP, 3787 .major = 11, 3788 .minor = 0, 3789 .rev = 8, 3790 .funcs = &psp_ip_funcs, 3791 }; 3792 3793 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 3794 .type = AMD_IP_BLOCK_TYPE_PSP, 3795 .major = 12, 3796 .minor = 0, 3797 .rev = 0, 3798 .funcs = &psp_ip_funcs, 3799 }; 3800 3801 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3802 .type = AMD_IP_BLOCK_TYPE_PSP, 3803 .major = 13, 3804 .minor = 0, 3805 .rev = 0, 3806 .funcs = &psp_ip_funcs, 3807 }; 3808 3809 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 3810 .type = AMD_IP_BLOCK_TYPE_PSP, 3811 .major = 13, 3812 .minor = 0, 3813 .rev = 4, 3814 .funcs = &psp_ip_funcs, 3815 }; 3816