1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 42 #include "amdgpu_ras.h" 43 #include "amdgpu_securedisplay.h" 44 #include "amdgpu_atomfirmware.h" 45 46 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 47 48 static int psp_load_smu_fw(struct psp_context *psp); 49 static int psp_rap_terminate(struct psp_context *psp); 50 static int psp_securedisplay_terminate(struct psp_context *psp); 51 52 static int psp_ring_init(struct psp_context *psp, 53 enum psp_ring_type ring_type) 54 { 55 int ret = 0; 56 struct psp_ring *ring; 57 struct amdgpu_device *adev = psp->adev; 58 59 ring = &psp->km_ring; 60 61 ring->ring_type = ring_type; 62 63 /* allocate 4k Page of Local Frame Buffer memory for ring */ 64 ring->ring_size = 0x1000; 65 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 66 AMDGPU_GEM_DOMAIN_VRAM | 67 AMDGPU_GEM_DOMAIN_GTT, 68 &adev->firmware.rbuf, 69 &ring->ring_mem_mc_addr, 70 (void **)&ring->ring_mem); 71 if (ret) { 72 ring->ring_size = 0; 73 return ret; 74 } 75 76 return 0; 77 } 78 79 /* 80 * Due to DF Cstate management centralized to PMFW, the firmware 81 * loading sequence will be updated as below: 82 * - Load KDB 83 * - Load SYS_DRV 84 * - Load tOS 85 * - Load PMFW 86 * - Setup TMR 87 * - Load other non-psp fw 88 * - Load ASD 89 * - Load XGMI/RAS/HDCP/DTM TA if any 90 * 91 * This new sequence is required for 92 * - Arcturus and onwards 93 */ 94 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 95 { 96 struct amdgpu_device *adev = psp->adev; 97 98 if (amdgpu_sriov_vf(adev)) { 99 psp->pmfw_centralized_cstate_management = false; 100 return; 101 } 102 103 switch (adev->ip_versions[MP0_HWIP][0]) { 104 case IP_VERSION(11, 0, 0): 105 case IP_VERSION(11, 0, 4): 106 case IP_VERSION(11, 0, 5): 107 case IP_VERSION(11, 0, 7): 108 case IP_VERSION(11, 0, 9): 109 case IP_VERSION(11, 0, 11): 110 case IP_VERSION(11, 0, 12): 111 case IP_VERSION(11, 0, 13): 112 case IP_VERSION(13, 0, 0): 113 case IP_VERSION(13, 0, 2): 114 case IP_VERSION(13, 0, 7): 115 psp->pmfw_centralized_cstate_management = true; 116 break; 117 default: 118 psp->pmfw_centralized_cstate_management = false; 119 break; 120 } 121 } 122 123 static int psp_init_sriov_microcode(struct psp_context *psp) 124 { 125 struct amdgpu_device *adev = psp->adev; 126 char ucode_prefix[30]; 127 int ret = 0; 128 129 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 130 131 switch (adev->ip_versions[MP0_HWIP][0]) { 132 case IP_VERSION(9, 0, 0): 133 case IP_VERSION(11, 0, 7): 134 case IP_VERSION(11, 0, 9): 135 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 136 ret = psp_init_cap_microcode(psp, ucode_prefix); 137 break; 138 case IP_VERSION(13, 0, 2): 139 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 140 ret = psp_init_cap_microcode(psp, ucode_prefix); 141 ret &= psp_init_ta_microcode(psp, ucode_prefix); 142 break; 143 case IP_VERSION(13, 0, 0): 144 adev->virt.autoload_ucode_id = 0; 145 break; 146 case IP_VERSION(13, 0, 6): 147 ret = psp_init_cap_microcode(psp, ucode_prefix); 148 ret &= psp_init_ta_microcode(psp, ucode_prefix); 149 break; 150 case IP_VERSION(13, 0, 10): 151 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 152 ret = psp_init_cap_microcode(psp, ucode_prefix); 153 break; 154 default: 155 return -EINVAL; 156 } 157 return ret; 158 } 159 160 static int psp_early_init(void *handle) 161 { 162 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 163 struct psp_context *psp = &adev->psp; 164 165 switch (adev->ip_versions[MP0_HWIP][0]) { 166 case IP_VERSION(9, 0, 0): 167 psp_v3_1_set_psp_funcs(psp); 168 psp->autoload_supported = false; 169 break; 170 case IP_VERSION(10, 0, 0): 171 case IP_VERSION(10, 0, 1): 172 psp_v10_0_set_psp_funcs(psp); 173 psp->autoload_supported = false; 174 break; 175 case IP_VERSION(11, 0, 2): 176 case IP_VERSION(11, 0, 4): 177 psp_v11_0_set_psp_funcs(psp); 178 psp->autoload_supported = false; 179 break; 180 case IP_VERSION(11, 0, 0): 181 case IP_VERSION(11, 0, 7): 182 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev); 183 fallthrough; 184 case IP_VERSION(11, 0, 5): 185 case IP_VERSION(11, 0, 9): 186 case IP_VERSION(11, 0, 11): 187 case IP_VERSION(11, 5, 0): 188 case IP_VERSION(11, 0, 12): 189 case IP_VERSION(11, 0, 13): 190 psp_v11_0_set_psp_funcs(psp); 191 psp->autoload_supported = true; 192 break; 193 case IP_VERSION(11, 0, 3): 194 case IP_VERSION(12, 0, 1): 195 psp_v12_0_set_psp_funcs(psp); 196 break; 197 case IP_VERSION(13, 0, 2): 198 case IP_VERSION(13, 0, 6): 199 psp_v13_0_set_psp_funcs(psp); 200 break; 201 case IP_VERSION(13, 0, 1): 202 case IP_VERSION(13, 0, 3): 203 case IP_VERSION(13, 0, 5): 204 case IP_VERSION(13, 0, 8): 205 case IP_VERSION(13, 0, 11): 206 case IP_VERSION(14, 0, 0): 207 psp_v13_0_set_psp_funcs(psp); 208 psp->autoload_supported = true; 209 break; 210 case IP_VERSION(11, 0, 8): 211 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 212 psp_v11_0_8_set_psp_funcs(psp); 213 psp->autoload_supported = false; 214 } 215 break; 216 case IP_VERSION(13, 0, 0): 217 case IP_VERSION(13, 0, 7): 218 case IP_VERSION(13, 0, 10): 219 psp_v13_0_set_psp_funcs(psp); 220 psp->autoload_supported = true; 221 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 222 break; 223 case IP_VERSION(13, 0, 4): 224 psp_v13_0_4_set_psp_funcs(psp); 225 psp->autoload_supported = true; 226 break; 227 default: 228 return -EINVAL; 229 } 230 231 psp->adev = adev; 232 233 psp_check_pmfw_centralized_cstate_management(psp); 234 235 if (amdgpu_sriov_vf(adev)) 236 return psp_init_sriov_microcode(psp); 237 else 238 return psp_init_microcode(psp); 239 } 240 241 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 242 { 243 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 244 &mem_ctx->shared_buf); 245 mem_ctx->shared_bo = NULL; 246 } 247 248 static void psp_free_shared_bufs(struct psp_context *psp) 249 { 250 void *tmr_buf; 251 void **pptr; 252 253 /* free TMR memory buffer */ 254 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 255 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 256 psp->tmr_bo = NULL; 257 258 /* free xgmi shared memory */ 259 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 260 261 /* free ras shared memory */ 262 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 263 264 /* free hdcp shared memory */ 265 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 266 267 /* free dtm shared memory */ 268 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 269 270 /* free rap shared memory */ 271 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 272 273 /* free securedisplay shared memory */ 274 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 275 276 277 } 278 279 static void psp_memory_training_fini(struct psp_context *psp) 280 { 281 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 282 283 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 284 kfree(ctx->sys_cache); 285 ctx->sys_cache = NULL; 286 } 287 288 static int psp_memory_training_init(struct psp_context *psp) 289 { 290 int ret; 291 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 292 293 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 294 DRM_DEBUG("memory training is not supported!\n"); 295 return 0; 296 } 297 298 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 299 if (ctx->sys_cache == NULL) { 300 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 301 ret = -ENOMEM; 302 goto Err_out; 303 } 304 305 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 306 ctx->train_data_size, 307 ctx->p2c_train_data_offset, 308 ctx->c2p_train_data_offset); 309 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 310 return 0; 311 312 Err_out: 313 psp_memory_training_fini(psp); 314 return ret; 315 } 316 317 /* 318 * Helper funciton to query psp runtime database entry 319 * 320 * @adev: amdgpu_device pointer 321 * @entry_type: the type of psp runtime database entry 322 * @db_entry: runtime database entry pointer 323 * 324 * Return false if runtime database doesn't exit or entry is invalid 325 * or true if the specific database entry is found, and copy to @db_entry 326 */ 327 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 328 enum psp_runtime_entry_type entry_type, 329 void *db_entry) 330 { 331 uint64_t db_header_pos, db_dir_pos; 332 struct psp_runtime_data_header db_header = {0}; 333 struct psp_runtime_data_directory db_dir = {0}; 334 bool ret = false; 335 int i; 336 337 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6)) 338 return false; 339 340 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 341 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 342 343 /* read runtime db header from vram */ 344 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 345 sizeof(struct psp_runtime_data_header), false); 346 347 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 348 /* runtime db doesn't exist, exit */ 349 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 350 return false; 351 } 352 353 /* read runtime database entry from vram */ 354 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 355 sizeof(struct psp_runtime_data_directory), false); 356 357 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 358 /* invalid db entry count, exit */ 359 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 360 return false; 361 } 362 363 /* look up for requested entry type */ 364 for (i = 0; i < db_dir.entry_count && !ret; i++) { 365 if (db_dir.entry_list[i].entry_type == entry_type) { 366 switch (entry_type) { 367 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 368 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 369 /* invalid db entry size */ 370 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 371 return false; 372 } 373 /* read runtime database entry */ 374 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 375 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 376 ret = true; 377 break; 378 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 379 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 380 /* invalid db entry size */ 381 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 382 return false; 383 } 384 /* read runtime database entry */ 385 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 386 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 387 ret = true; 388 break; 389 default: 390 ret = false; 391 break; 392 } 393 } 394 } 395 396 return ret; 397 } 398 399 static int psp_sw_init(void *handle) 400 { 401 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 402 struct psp_context *psp = &adev->psp; 403 int ret; 404 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 405 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 406 struct psp_runtime_scpm_entry scpm_entry; 407 408 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 409 if (!psp->cmd) { 410 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 411 ret = -ENOMEM; 412 } 413 414 adev->psp.xgmi_context.supports_extended_data = 415 !adev->gmc.xgmi.connected_to_cpu && 416 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 417 418 memset(&scpm_entry, 0, sizeof(scpm_entry)); 419 if ((psp_get_runtime_db_entry(adev, 420 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 421 &scpm_entry)) && 422 (scpm_entry.scpm_status != SCPM_DISABLE)) { 423 adev->scpm_enabled = true; 424 adev->scpm_status = scpm_entry.scpm_status; 425 } else { 426 adev->scpm_enabled = false; 427 adev->scpm_status = SCPM_DISABLE; 428 } 429 430 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 431 432 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 433 if (psp_get_runtime_db_entry(adev, 434 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 435 &boot_cfg_entry)) { 436 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 437 if ((psp->boot_cfg_bitmask) & 438 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 439 /* If psp runtime database exists, then 440 * only enable two stage memory training 441 * when TWO_STAGE_DRAM_TRAINING bit is set 442 * in runtime database 443 */ 444 mem_training_ctx->enable_mem_training = true; 445 } 446 447 } else { 448 /* If psp runtime database doesn't exist or is 449 * invalid, force enable two stage memory training 450 */ 451 mem_training_ctx->enable_mem_training = true; 452 } 453 454 if (mem_training_ctx->enable_mem_training) { 455 ret = psp_memory_training_init(psp); 456 if (ret) { 457 DRM_ERROR("Failed to initialize memory training!\n"); 458 return ret; 459 } 460 461 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 462 if (ret) { 463 DRM_ERROR("Failed to process memory training!\n"); 464 return ret; 465 } 466 } 467 468 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 469 amdgpu_sriov_vf(adev) ? 470 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 471 &psp->fw_pri_bo, 472 &psp->fw_pri_mc_addr, 473 &psp->fw_pri_buf); 474 if (ret) 475 return ret; 476 477 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 478 AMDGPU_GEM_DOMAIN_VRAM | 479 AMDGPU_GEM_DOMAIN_GTT, 480 &psp->fence_buf_bo, 481 &psp->fence_buf_mc_addr, 482 &psp->fence_buf); 483 if (ret) 484 goto failed1; 485 486 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 487 AMDGPU_GEM_DOMAIN_VRAM | 488 AMDGPU_GEM_DOMAIN_GTT, 489 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 490 (void **)&psp->cmd_buf_mem); 491 if (ret) 492 goto failed2; 493 494 return 0; 495 496 failed2: 497 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 498 &psp->fence_buf_mc_addr, &psp->fence_buf); 499 failed1: 500 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 501 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 502 return ret; 503 } 504 505 static int psp_sw_fini(void *handle) 506 { 507 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 508 struct psp_context *psp = &adev->psp; 509 struct psp_gfx_cmd_resp *cmd = psp->cmd; 510 511 psp_memory_training_fini(psp); 512 513 amdgpu_ucode_release(&psp->sos_fw); 514 amdgpu_ucode_release(&psp->asd_fw); 515 amdgpu_ucode_release(&psp->ta_fw); 516 amdgpu_ucode_release(&psp->cap_fw); 517 amdgpu_ucode_release(&psp->toc_fw); 518 519 kfree(cmd); 520 cmd = NULL; 521 522 psp_free_shared_bufs(psp); 523 524 if (psp->km_ring.ring_mem) 525 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 526 &psp->km_ring.ring_mem_mc_addr, 527 (void **)&psp->km_ring.ring_mem); 528 529 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 530 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 531 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 532 &psp->fence_buf_mc_addr, &psp->fence_buf); 533 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 534 (void **)&psp->cmd_buf_mem); 535 536 return 0; 537 } 538 539 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 540 uint32_t reg_val, uint32_t mask, bool check_changed) 541 { 542 uint32_t val; 543 int i; 544 struct amdgpu_device *adev = psp->adev; 545 546 if (psp->adev->no_hw_access) 547 return 0; 548 549 for (i = 0; i < adev->usec_timeout; i++) { 550 val = RREG32(reg_index); 551 if (check_changed) { 552 if (val != reg_val) 553 return 0; 554 } else { 555 if ((val & mask) == reg_val) 556 return 0; 557 } 558 udelay(1); 559 } 560 561 return -ETIME; 562 } 563 564 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 565 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout) 566 { 567 uint32_t val; 568 int i; 569 struct amdgpu_device *adev = psp->adev; 570 571 if (psp->adev->no_hw_access) 572 return 0; 573 574 for (i = 0; i < msec_timeout; i++) { 575 val = RREG32(reg_index); 576 if ((val & mask) == reg_val) 577 return 0; 578 msleep(1); 579 } 580 581 return -ETIME; 582 } 583 584 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 585 { 586 switch (cmd_id) { 587 case GFX_CMD_ID_LOAD_TA: 588 return "LOAD_TA"; 589 case GFX_CMD_ID_UNLOAD_TA: 590 return "UNLOAD_TA"; 591 case GFX_CMD_ID_INVOKE_CMD: 592 return "INVOKE_CMD"; 593 case GFX_CMD_ID_LOAD_ASD: 594 return "LOAD_ASD"; 595 case GFX_CMD_ID_SETUP_TMR: 596 return "SETUP_TMR"; 597 case GFX_CMD_ID_LOAD_IP_FW: 598 return "LOAD_IP_FW"; 599 case GFX_CMD_ID_DESTROY_TMR: 600 return "DESTROY_TMR"; 601 case GFX_CMD_ID_SAVE_RESTORE: 602 return "SAVE_RESTORE_IP_FW"; 603 case GFX_CMD_ID_SETUP_VMR: 604 return "SETUP_VMR"; 605 case GFX_CMD_ID_DESTROY_VMR: 606 return "DESTROY_VMR"; 607 case GFX_CMD_ID_PROG_REG: 608 return "PROG_REG"; 609 case GFX_CMD_ID_GET_FW_ATTESTATION: 610 return "GET_FW_ATTESTATION"; 611 case GFX_CMD_ID_LOAD_TOC: 612 return "ID_LOAD_TOC"; 613 case GFX_CMD_ID_AUTOLOAD_RLC: 614 return "AUTOLOAD_RLC"; 615 case GFX_CMD_ID_BOOT_CFG: 616 return "BOOT_CFG"; 617 default: 618 return "UNKNOWN CMD"; 619 } 620 } 621 622 static int 623 psp_cmd_submit_buf(struct psp_context *psp, 624 struct amdgpu_firmware_info *ucode, 625 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 626 { 627 int ret; 628 int index; 629 int timeout = 20000; 630 bool ras_intr = false; 631 bool skip_unsupport = false; 632 633 if (psp->adev->no_hw_access) 634 return 0; 635 636 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 637 638 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 639 640 index = atomic_inc_return(&psp->fence_value); 641 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 642 if (ret) { 643 atomic_dec(&psp->fence_value); 644 goto exit; 645 } 646 647 amdgpu_device_invalidate_hdp(psp->adev, NULL); 648 while (*((unsigned int *)psp->fence_buf) != index) { 649 if (--timeout == 0) 650 break; 651 /* 652 * Shouldn't wait for timeout when err_event_athub occurs, 653 * because gpu reset thread triggered and lock resource should 654 * be released for psp resume sequence. 655 */ 656 ras_intr = amdgpu_ras_intr_triggered(); 657 if (ras_intr) 658 break; 659 usleep_range(10, 100); 660 amdgpu_device_invalidate_hdp(psp->adev, NULL); 661 } 662 663 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 664 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 665 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 666 667 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 668 669 /* In some cases, psp response status is not 0 even there is no 670 * problem while the command is submitted. Some version of PSP FW 671 * doesn't write 0 to that field. 672 * So here we would like to only print a warning instead of an error 673 * during psp initialization to avoid breaking hw_init and it doesn't 674 * return -EINVAL. 675 */ 676 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 677 if (ucode) 678 DRM_WARN("failed to load ucode %s(0x%X) ", 679 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 680 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 681 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 682 psp->cmd_buf_mem->resp.status); 683 /* If any firmware (including CAP) load fails under SRIOV, it should 684 * return failure to stop the VF from initializing. 685 * Also return failure in case of timeout 686 */ 687 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 688 ret = -EINVAL; 689 goto exit; 690 } 691 } 692 693 if (ucode) { 694 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 695 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 696 } 697 698 exit: 699 return ret; 700 } 701 702 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 703 { 704 struct psp_gfx_cmd_resp *cmd = psp->cmd; 705 706 mutex_lock(&psp->mutex); 707 708 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 709 710 return cmd; 711 } 712 713 static void release_psp_cmd_buf(struct psp_context *psp) 714 { 715 mutex_unlock(&psp->mutex); 716 } 717 718 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 719 struct psp_gfx_cmd_resp *cmd, 720 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 721 { 722 struct amdgpu_device *adev = psp->adev; 723 uint32_t size = 0; 724 uint64_t tmr_pa = 0; 725 726 if (tmr_bo) { 727 size = amdgpu_bo_size(tmr_bo); 728 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 729 } 730 731 if (amdgpu_sriov_vf(psp->adev)) 732 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 733 else 734 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 735 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 736 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 737 cmd->cmd.cmd_setup_tmr.buf_size = size; 738 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 739 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 740 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 741 } 742 743 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 744 uint64_t pri_buf_mc, uint32_t size) 745 { 746 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 747 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 748 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 749 cmd->cmd.cmd_load_toc.toc_size = size; 750 } 751 752 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 753 static int psp_load_toc(struct psp_context *psp, 754 uint32_t *tmr_size) 755 { 756 int ret; 757 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 758 759 /* Copy toc to psp firmware private buffer */ 760 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 761 762 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 763 764 ret = psp_cmd_submit_buf(psp, NULL, cmd, 765 psp->fence_buf_mc_addr); 766 if (!ret) 767 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 768 769 release_psp_cmd_buf(psp); 770 771 return ret; 772 } 773 774 static bool psp_boottime_tmr(struct psp_context *psp) 775 { 776 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 777 case IP_VERSION(13, 0, 6): 778 return true; 779 default: 780 return false; 781 } 782 } 783 784 /* Set up Trusted Memory Region */ 785 static int psp_tmr_init(struct psp_context *psp) 786 { 787 int ret = 0; 788 int tmr_size; 789 void *tmr_buf; 790 void **pptr; 791 792 /* 793 * According to HW engineer, they prefer the TMR address be "naturally 794 * aligned" , e.g. the start address be an integer divide of TMR size. 795 * 796 * Note: this memory need be reserved till the driver 797 * uninitializes. 798 */ 799 tmr_size = PSP_TMR_SIZE(psp->adev); 800 801 /* For ASICs support RLC autoload, psp will parse the toc 802 * and calculate the total size of TMR needed 803 */ 804 if (!amdgpu_sriov_vf(psp->adev) && 805 psp->toc.start_addr && 806 psp->toc.size_bytes && 807 psp->fw_pri_buf) { 808 ret = psp_load_toc(psp, &tmr_size); 809 if (ret) { 810 DRM_ERROR("Failed to load toc\n"); 811 return ret; 812 } 813 } 814 815 if (!psp->tmr_bo) { 816 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 817 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 818 PSP_TMR_ALIGNMENT, 819 AMDGPU_HAS_VRAM(psp->adev) ? 820 AMDGPU_GEM_DOMAIN_VRAM : 821 AMDGPU_GEM_DOMAIN_GTT, 822 &psp->tmr_bo, &psp->tmr_mc_addr, 823 pptr); 824 } 825 826 return ret; 827 } 828 829 static bool psp_skip_tmr(struct psp_context *psp) 830 { 831 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 832 case IP_VERSION(11, 0, 9): 833 case IP_VERSION(11, 0, 7): 834 case IP_VERSION(13, 0, 2): 835 case IP_VERSION(13, 0, 6): 836 case IP_VERSION(13, 0, 10): 837 return true; 838 default: 839 return false; 840 } 841 } 842 843 static int psp_tmr_load(struct psp_context *psp) 844 { 845 int ret; 846 struct psp_gfx_cmd_resp *cmd; 847 848 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 849 * Already set up by host driver. 850 */ 851 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 852 return 0; 853 854 cmd = acquire_psp_cmd_buf(psp); 855 856 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 857 if (psp->tmr_bo) 858 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 859 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 860 861 ret = psp_cmd_submit_buf(psp, NULL, cmd, 862 psp->fence_buf_mc_addr); 863 864 release_psp_cmd_buf(psp); 865 866 return ret; 867 } 868 869 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 870 struct psp_gfx_cmd_resp *cmd) 871 { 872 if (amdgpu_sriov_vf(psp->adev)) 873 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 874 else 875 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 876 } 877 878 static int psp_tmr_unload(struct psp_context *psp) 879 { 880 int ret; 881 struct psp_gfx_cmd_resp *cmd; 882 883 /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV, 884 * as TMR is not loaded at all 885 */ 886 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 887 return 0; 888 889 cmd = acquire_psp_cmd_buf(psp); 890 891 psp_prep_tmr_unload_cmd_buf(psp, cmd); 892 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 893 894 ret = psp_cmd_submit_buf(psp, NULL, cmd, 895 psp->fence_buf_mc_addr); 896 897 release_psp_cmd_buf(psp); 898 899 return ret; 900 } 901 902 static int psp_tmr_terminate(struct psp_context *psp) 903 { 904 return psp_tmr_unload(psp); 905 } 906 907 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 908 uint64_t *output_ptr) 909 { 910 int ret; 911 struct psp_gfx_cmd_resp *cmd; 912 913 if (!output_ptr) 914 return -EINVAL; 915 916 if (amdgpu_sriov_vf(psp->adev)) 917 return 0; 918 919 cmd = acquire_psp_cmd_buf(psp); 920 921 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 922 923 ret = psp_cmd_submit_buf(psp, NULL, cmd, 924 psp->fence_buf_mc_addr); 925 926 if (!ret) { 927 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 928 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 929 } 930 931 release_psp_cmd_buf(psp); 932 933 return ret; 934 } 935 936 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 937 { 938 struct psp_context *psp = &adev->psp; 939 struct psp_gfx_cmd_resp *cmd; 940 int ret; 941 942 if (amdgpu_sriov_vf(adev)) 943 return 0; 944 945 cmd = acquire_psp_cmd_buf(psp); 946 947 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 948 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 949 950 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 951 if (!ret) { 952 *boot_cfg = 953 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 954 } 955 956 release_psp_cmd_buf(psp); 957 958 return ret; 959 } 960 961 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 962 { 963 int ret; 964 struct psp_context *psp = &adev->psp; 965 struct psp_gfx_cmd_resp *cmd; 966 967 if (amdgpu_sriov_vf(adev)) 968 return 0; 969 970 cmd = acquire_psp_cmd_buf(psp); 971 972 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 973 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 974 cmd->cmd.boot_cfg.boot_config = boot_cfg; 975 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 976 977 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 978 979 release_psp_cmd_buf(psp); 980 981 return ret; 982 } 983 984 static int psp_rl_load(struct amdgpu_device *adev) 985 { 986 int ret; 987 struct psp_context *psp = &adev->psp; 988 struct psp_gfx_cmd_resp *cmd; 989 990 if (!is_psp_fw_valid(psp->rl)) 991 return 0; 992 993 cmd = acquire_psp_cmd_buf(psp); 994 995 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 996 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 997 998 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 999 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 1000 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 1001 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 1002 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 1003 1004 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1005 1006 release_psp_cmd_buf(psp); 1007 1008 return ret; 1009 } 1010 1011 int psp_spatial_partition(struct psp_context *psp, int mode) 1012 { 1013 struct psp_gfx_cmd_resp *cmd; 1014 int ret; 1015 1016 if (amdgpu_sriov_vf(psp->adev)) 1017 return 0; 1018 1019 cmd = acquire_psp_cmd_buf(psp); 1020 1021 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART; 1022 cmd->cmd.cmd_spatial_part.mode = mode; 1023 1024 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode); 1025 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1026 1027 release_psp_cmd_buf(psp); 1028 1029 return ret; 1030 } 1031 1032 static int psp_asd_initialize(struct psp_context *psp) 1033 { 1034 int ret; 1035 1036 /* If PSP version doesn't match ASD version, asd loading will be failed. 1037 * add workaround to bypass it for sriov now. 1038 * TODO: add version check to make it common 1039 */ 1040 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 1041 return 0; 1042 1043 psp->asd_context.mem_context.shared_mc_addr = 0; 1044 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 1045 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 1046 1047 ret = psp_ta_load(psp, &psp->asd_context); 1048 if (!ret) 1049 psp->asd_context.initialized = true; 1050 1051 return ret; 1052 } 1053 1054 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1055 uint32_t session_id) 1056 { 1057 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1058 cmd->cmd.cmd_unload_ta.session_id = session_id; 1059 } 1060 1061 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1062 { 1063 int ret; 1064 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1065 1066 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1067 1068 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1069 1070 context->resp_status = cmd->resp.status; 1071 1072 release_psp_cmd_buf(psp); 1073 1074 return ret; 1075 } 1076 1077 static int psp_asd_terminate(struct psp_context *psp) 1078 { 1079 int ret; 1080 1081 if (amdgpu_sriov_vf(psp->adev)) 1082 return 0; 1083 1084 if (!psp->asd_context.initialized) 1085 return 0; 1086 1087 ret = psp_ta_unload(psp, &psp->asd_context); 1088 if (!ret) 1089 psp->asd_context.initialized = false; 1090 1091 return ret; 1092 } 1093 1094 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1095 uint32_t id, uint32_t value) 1096 { 1097 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1098 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1099 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1100 } 1101 1102 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1103 uint32_t value) 1104 { 1105 struct psp_gfx_cmd_resp *cmd; 1106 int ret = 0; 1107 1108 if (reg >= PSP_REG_LAST) 1109 return -EINVAL; 1110 1111 cmd = acquire_psp_cmd_buf(psp); 1112 1113 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1114 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1115 if (ret) 1116 DRM_ERROR("PSP failed to program reg id %d", reg); 1117 1118 release_psp_cmd_buf(psp); 1119 1120 return ret; 1121 } 1122 1123 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1124 uint64_t ta_bin_mc, 1125 struct ta_context *context) 1126 { 1127 cmd->cmd_id = context->ta_load_type; 1128 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1129 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1130 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1131 1132 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1133 lower_32_bits(context->mem_context.shared_mc_addr); 1134 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1135 upper_32_bits(context->mem_context.shared_mc_addr); 1136 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1137 } 1138 1139 int psp_ta_init_shared_buf(struct psp_context *psp, 1140 struct ta_mem_context *mem_ctx) 1141 { 1142 /* 1143 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1144 * physical) for ta to host memory 1145 */ 1146 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1147 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1148 AMDGPU_GEM_DOMAIN_GTT, 1149 &mem_ctx->shared_bo, 1150 &mem_ctx->shared_mc_addr, 1151 &mem_ctx->shared_buf); 1152 } 1153 1154 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1155 uint32_t ta_cmd_id, 1156 uint32_t session_id) 1157 { 1158 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1159 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1160 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1161 } 1162 1163 int psp_ta_invoke(struct psp_context *psp, 1164 uint32_t ta_cmd_id, 1165 struct ta_context *context) 1166 { 1167 int ret; 1168 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1169 1170 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1171 1172 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1173 psp->fence_buf_mc_addr); 1174 1175 context->resp_status = cmd->resp.status; 1176 1177 release_psp_cmd_buf(psp); 1178 1179 return ret; 1180 } 1181 1182 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1183 { 1184 int ret; 1185 struct psp_gfx_cmd_resp *cmd; 1186 1187 cmd = acquire_psp_cmd_buf(psp); 1188 1189 psp_copy_fw(psp, context->bin_desc.start_addr, 1190 context->bin_desc.size_bytes); 1191 1192 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1193 1194 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1195 psp->fence_buf_mc_addr); 1196 1197 context->resp_status = cmd->resp.status; 1198 1199 if (!ret) 1200 context->session_id = cmd->resp.session_id; 1201 1202 release_psp_cmd_buf(psp); 1203 1204 return ret; 1205 } 1206 1207 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1208 { 1209 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1210 } 1211 1212 int psp_xgmi_terminate(struct psp_context *psp) 1213 { 1214 int ret; 1215 struct amdgpu_device *adev = psp->adev; 1216 1217 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1218 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1219 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1220 adev->gmc.xgmi.connected_to_cpu)) 1221 return 0; 1222 1223 if (!psp->xgmi_context.context.initialized) 1224 return 0; 1225 1226 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1227 1228 psp->xgmi_context.context.initialized = false; 1229 1230 return ret; 1231 } 1232 1233 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1234 { 1235 struct ta_xgmi_shared_memory *xgmi_cmd; 1236 int ret; 1237 1238 if (!psp->ta_fw || 1239 !psp->xgmi_context.context.bin_desc.size_bytes || 1240 !psp->xgmi_context.context.bin_desc.start_addr) 1241 return -ENOENT; 1242 1243 if (!load_ta) 1244 goto invoke; 1245 1246 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1247 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1248 1249 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1250 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1251 if (ret) 1252 return ret; 1253 } 1254 1255 /* Load XGMI TA */ 1256 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1257 if (!ret) 1258 psp->xgmi_context.context.initialized = true; 1259 else 1260 return ret; 1261 1262 invoke: 1263 /* Initialize XGMI session */ 1264 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1265 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1266 xgmi_cmd->flag_extend_link_record = set_extended_data; 1267 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1268 1269 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1270 1271 return ret; 1272 } 1273 1274 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1275 { 1276 struct ta_xgmi_shared_memory *xgmi_cmd; 1277 int ret; 1278 1279 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1280 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1281 1282 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1283 1284 /* Invoke xgmi ta to get hive id */ 1285 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1286 if (ret) 1287 return ret; 1288 1289 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1290 1291 return 0; 1292 } 1293 1294 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1295 { 1296 struct ta_xgmi_shared_memory *xgmi_cmd; 1297 int ret; 1298 1299 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1300 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1301 1302 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1303 1304 /* Invoke xgmi ta to get the node id */ 1305 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1306 if (ret) 1307 return ret; 1308 1309 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1310 1311 return 0; 1312 } 1313 1314 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1315 { 1316 return (psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1317 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) || 1318 psp->adev->ip_versions[MP0_HWIP][0] >= IP_VERSION(13, 0, 6); 1319 } 1320 1321 /* 1322 * Chips that support extended topology information require the driver to 1323 * reflect topology information in the opposite direction. This is 1324 * because the TA has already exceeded its link record limit and if the 1325 * TA holds bi-directional information, the driver would have to do 1326 * multiple fetches instead of just two. 1327 */ 1328 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1329 struct psp_xgmi_node_info node_info) 1330 { 1331 struct amdgpu_device *mirror_adev; 1332 struct amdgpu_hive_info *hive; 1333 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1334 uint64_t dst_node_id = node_info.node_id; 1335 uint8_t dst_num_hops = node_info.num_hops; 1336 uint8_t dst_num_links = node_info.num_links; 1337 1338 hive = amdgpu_get_xgmi_hive(psp->adev); 1339 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1340 struct psp_xgmi_topology_info *mirror_top_info; 1341 int j; 1342 1343 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1344 continue; 1345 1346 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1347 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1348 if (mirror_top_info->nodes[j].node_id != src_node_id) 1349 continue; 1350 1351 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1352 /* 1353 * prevent 0 num_links value re-reflection since reflection 1354 * criteria is based on num_hops (direct or indirect). 1355 * 1356 */ 1357 if (dst_num_links) 1358 mirror_top_info->nodes[j].num_links = dst_num_links; 1359 1360 break; 1361 } 1362 1363 break; 1364 } 1365 1366 amdgpu_put_xgmi_hive(hive); 1367 } 1368 1369 int psp_xgmi_get_topology_info(struct psp_context *psp, 1370 int number_devices, 1371 struct psp_xgmi_topology_info *topology, 1372 bool get_extended_data) 1373 { 1374 struct ta_xgmi_shared_memory *xgmi_cmd; 1375 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1376 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1377 int i; 1378 int ret; 1379 1380 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1381 return -EINVAL; 1382 1383 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1384 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1385 xgmi_cmd->flag_extend_link_record = get_extended_data; 1386 1387 /* Fill in the shared memory with topology information as input */ 1388 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1389 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1390 topology_info_input->num_nodes = number_devices; 1391 1392 for (i = 0; i < topology_info_input->num_nodes; i++) { 1393 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1394 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1395 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1396 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1397 } 1398 1399 /* Invoke xgmi ta to get the topology information */ 1400 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1401 if (ret) 1402 return ret; 1403 1404 /* Read the output topology information from the shared memory */ 1405 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1406 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1407 for (i = 0; i < topology->num_nodes; i++) { 1408 /* extended data will either be 0 or equal to non-extended data */ 1409 if (topology_info_output->nodes[i].num_hops) 1410 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1411 1412 /* non-extended data gets everything here so no need to update */ 1413 if (!get_extended_data) { 1414 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1415 topology->nodes[i].is_sharing_enabled = 1416 topology_info_output->nodes[i].is_sharing_enabled; 1417 topology->nodes[i].sdma_engine = 1418 topology_info_output->nodes[i].sdma_engine; 1419 } 1420 1421 } 1422 1423 /* Invoke xgmi ta again to get the link information */ 1424 if (psp_xgmi_peer_link_info_supported(psp)) { 1425 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1426 bool requires_reflection = 1427 (psp->xgmi_context.supports_extended_data && get_extended_data) || 1428 psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6); 1429 1430 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1431 1432 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1433 1434 if (ret) 1435 return ret; 1436 1437 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1438 for (i = 0; i < topology->num_nodes; i++) { 1439 /* accumulate num_links on extended data */ 1440 topology->nodes[i].num_links = get_extended_data ? 1441 topology->nodes[i].num_links + 1442 link_info_output->nodes[i].num_links : 1443 ((requires_reflection && topology->nodes[i].num_links) ? topology->nodes[i].num_links : 1444 link_info_output->nodes[i].num_links); 1445 1446 /* reflect the topology information for bi-directionality */ 1447 if (requires_reflection && topology->nodes[i].num_hops) 1448 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1449 } 1450 } 1451 1452 return 0; 1453 } 1454 1455 int psp_xgmi_set_topology_info(struct psp_context *psp, 1456 int number_devices, 1457 struct psp_xgmi_topology_info *topology) 1458 { 1459 struct ta_xgmi_shared_memory *xgmi_cmd; 1460 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1461 int i; 1462 1463 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1464 return -EINVAL; 1465 1466 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1467 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1468 1469 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1470 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1471 topology_info_input->num_nodes = number_devices; 1472 1473 for (i = 0; i < topology_info_input->num_nodes; i++) { 1474 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1475 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1476 topology_info_input->nodes[i].is_sharing_enabled = 1; 1477 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1478 } 1479 1480 /* Invoke xgmi ta to set topology information */ 1481 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1482 } 1483 1484 // ras begin 1485 static void psp_ras_ta_check_status(struct psp_context *psp) 1486 { 1487 struct ta_ras_shared_memory *ras_cmd = 1488 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1489 1490 switch (ras_cmd->ras_status) { 1491 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1492 dev_warn(psp->adev->dev, 1493 "RAS WARNING: cmd failed due to unsupported ip\n"); 1494 break; 1495 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1496 dev_warn(psp->adev->dev, 1497 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1498 break; 1499 case TA_RAS_STATUS__SUCCESS: 1500 break; 1501 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1502 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1503 dev_warn(psp->adev->dev, 1504 "RAS WARNING: Inject error to critical region is not allowed\n"); 1505 break; 1506 default: 1507 dev_warn(psp->adev->dev, 1508 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1509 break; 1510 } 1511 } 1512 1513 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1514 { 1515 struct ta_ras_shared_memory *ras_cmd; 1516 int ret; 1517 1518 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1519 1520 /* 1521 * TODO: bypass the loading in sriov for now 1522 */ 1523 if (amdgpu_sriov_vf(psp->adev)) 1524 return 0; 1525 1526 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1527 1528 if (amdgpu_ras_intr_triggered()) 1529 return ret; 1530 1531 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 1532 DRM_WARN("RAS: Unsupported Interface"); 1533 return -EINVAL; 1534 } 1535 1536 if (!ret) { 1537 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1538 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1539 1540 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1541 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1542 dev_warn(psp->adev->dev, 1543 "RAS internal register access blocked\n"); 1544 1545 psp_ras_ta_check_status(psp); 1546 } 1547 1548 return ret; 1549 } 1550 1551 int psp_ras_enable_features(struct psp_context *psp, 1552 union ta_ras_cmd_input *info, bool enable) 1553 { 1554 struct ta_ras_shared_memory *ras_cmd; 1555 int ret; 1556 1557 if (!psp->ras_context.context.initialized) 1558 return -EINVAL; 1559 1560 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1561 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1562 1563 if (enable) 1564 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1565 else 1566 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1567 1568 ras_cmd->ras_in_message = *info; 1569 1570 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1571 if (ret) 1572 return -EINVAL; 1573 1574 return 0; 1575 } 1576 1577 int psp_ras_terminate(struct psp_context *psp) 1578 { 1579 int ret; 1580 1581 /* 1582 * TODO: bypass the terminate in sriov for now 1583 */ 1584 if (amdgpu_sriov_vf(psp->adev)) 1585 return 0; 1586 1587 if (!psp->ras_context.context.initialized) 1588 return 0; 1589 1590 ret = psp_ta_unload(psp, &psp->ras_context.context); 1591 1592 psp->ras_context.context.initialized = false; 1593 1594 return ret; 1595 } 1596 1597 int psp_ras_initialize(struct psp_context *psp) 1598 { 1599 int ret; 1600 uint32_t boot_cfg = 0xFF; 1601 struct amdgpu_device *adev = psp->adev; 1602 struct ta_ras_shared_memory *ras_cmd; 1603 1604 /* 1605 * TODO: bypass the initialize in sriov for now 1606 */ 1607 if (amdgpu_sriov_vf(adev)) 1608 return 0; 1609 1610 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1611 !adev->psp.ras_context.context.bin_desc.start_addr) { 1612 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1613 return 0; 1614 } 1615 1616 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1617 /* query GECC enablement status from boot config 1618 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1619 */ 1620 ret = psp_boot_config_get(adev, &boot_cfg); 1621 if (ret) 1622 dev_warn(adev->dev, "PSP get boot config failed\n"); 1623 1624 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1625 if (!boot_cfg) { 1626 dev_info(adev->dev, "GECC is disabled\n"); 1627 } else { 1628 /* disable GECC in next boot cycle if ras is 1629 * disabled by module parameter amdgpu_ras_enable 1630 * and/or amdgpu_ras_mask, or boot_config_get call 1631 * is failed 1632 */ 1633 ret = psp_boot_config_set(adev, 0); 1634 if (ret) 1635 dev_warn(adev->dev, "PSP set boot config failed\n"); 1636 else 1637 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1638 } 1639 } else { 1640 if (boot_cfg == 1) { 1641 dev_info(adev->dev, "GECC is enabled\n"); 1642 } else { 1643 /* enable GECC in next boot cycle if it is disabled 1644 * in boot config, or force enable GECC if failed to 1645 * get boot configuration 1646 */ 1647 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1648 if (ret) 1649 dev_warn(adev->dev, "PSP set boot config failed\n"); 1650 else 1651 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1652 } 1653 } 1654 } 1655 1656 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1657 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1658 1659 if (!psp->ras_context.context.mem_context.shared_buf) { 1660 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1661 if (ret) 1662 return ret; 1663 } 1664 1665 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1666 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1667 1668 if (amdgpu_ras_is_poison_mode_supported(adev)) 1669 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1670 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1671 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1672 ras_cmd->ras_in_message.init_flags.xcc_mask = 1673 adev->gfx.xcc_mask; 1674 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; 1675 1676 ret = psp_ta_load(psp, &psp->ras_context.context); 1677 1678 if (!ret && !ras_cmd->ras_status) 1679 psp->ras_context.context.initialized = true; 1680 else { 1681 if (ras_cmd->ras_status) 1682 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1683 1684 /* fail to load RAS TA */ 1685 psp->ras_context.context.initialized = false; 1686 } 1687 1688 return ret; 1689 } 1690 1691 int psp_ras_trigger_error(struct psp_context *psp, 1692 struct ta_ras_trigger_error_input *info, uint32_t instance_mask) 1693 { 1694 struct ta_ras_shared_memory *ras_cmd; 1695 struct amdgpu_device *adev = psp->adev; 1696 int ret; 1697 uint32_t dev_mask; 1698 1699 if (!psp->ras_context.context.initialized) 1700 return -EINVAL; 1701 1702 switch (info->block_id) { 1703 case TA_RAS_BLOCK__GFX: 1704 dev_mask = GET_MASK(GC, instance_mask); 1705 break; 1706 case TA_RAS_BLOCK__SDMA: 1707 dev_mask = GET_MASK(SDMA0, instance_mask); 1708 break; 1709 case TA_RAS_BLOCK__VCN: 1710 case TA_RAS_BLOCK__JPEG: 1711 dev_mask = GET_MASK(VCN, instance_mask); 1712 break; 1713 default: 1714 dev_mask = instance_mask; 1715 break; 1716 } 1717 1718 /* reuse sub_block_index for backward compatibility */ 1719 dev_mask <<= AMDGPU_RAS_INST_SHIFT; 1720 dev_mask &= AMDGPU_RAS_INST_MASK; 1721 info->sub_block_index |= dev_mask; 1722 1723 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1724 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1725 1726 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1727 ras_cmd->ras_in_message.trigger_error = *info; 1728 1729 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1730 if (ret) 1731 return -EINVAL; 1732 1733 /* If err_event_athub occurs error inject was successful, however 1734 * return status from TA is no long reliable 1735 */ 1736 if (amdgpu_ras_intr_triggered()) 1737 return 0; 1738 1739 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1740 return -EACCES; 1741 else if (ras_cmd->ras_status) 1742 return -EINVAL; 1743 1744 return 0; 1745 } 1746 // ras end 1747 1748 // HDCP start 1749 static int psp_hdcp_initialize(struct psp_context *psp) 1750 { 1751 int ret; 1752 1753 /* 1754 * TODO: bypass the initialize in sriov for now 1755 */ 1756 if (amdgpu_sriov_vf(psp->adev)) 1757 return 0; 1758 1759 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1760 !psp->hdcp_context.context.bin_desc.start_addr) { 1761 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1762 return 0; 1763 } 1764 1765 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1766 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1767 1768 if (!psp->hdcp_context.context.mem_context.shared_buf) { 1769 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1770 if (ret) 1771 return ret; 1772 } 1773 1774 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1775 if (!ret) { 1776 psp->hdcp_context.context.initialized = true; 1777 mutex_init(&psp->hdcp_context.mutex); 1778 } 1779 1780 return ret; 1781 } 1782 1783 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1784 { 1785 /* 1786 * TODO: bypass the loading in sriov for now 1787 */ 1788 if (amdgpu_sriov_vf(psp->adev)) 1789 return 0; 1790 1791 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1792 } 1793 1794 static int psp_hdcp_terminate(struct psp_context *psp) 1795 { 1796 int ret; 1797 1798 /* 1799 * TODO: bypass the terminate in sriov for now 1800 */ 1801 if (amdgpu_sriov_vf(psp->adev)) 1802 return 0; 1803 1804 if (!psp->hdcp_context.context.initialized) 1805 return 0; 1806 1807 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1808 1809 psp->hdcp_context.context.initialized = false; 1810 1811 return ret; 1812 } 1813 // HDCP end 1814 1815 // DTM start 1816 static int psp_dtm_initialize(struct psp_context *psp) 1817 { 1818 int ret; 1819 1820 /* 1821 * TODO: bypass the initialize in sriov for now 1822 */ 1823 if (amdgpu_sriov_vf(psp->adev)) 1824 return 0; 1825 1826 if (!psp->dtm_context.context.bin_desc.size_bytes || 1827 !psp->dtm_context.context.bin_desc.start_addr) { 1828 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1829 return 0; 1830 } 1831 1832 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1833 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1834 1835 if (!psp->dtm_context.context.mem_context.shared_buf) { 1836 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1837 if (ret) 1838 return ret; 1839 } 1840 1841 ret = psp_ta_load(psp, &psp->dtm_context.context); 1842 if (!ret) { 1843 psp->dtm_context.context.initialized = true; 1844 mutex_init(&psp->dtm_context.mutex); 1845 } 1846 1847 return ret; 1848 } 1849 1850 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1851 { 1852 /* 1853 * TODO: bypass the loading in sriov for now 1854 */ 1855 if (amdgpu_sriov_vf(psp->adev)) 1856 return 0; 1857 1858 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1859 } 1860 1861 static int psp_dtm_terminate(struct psp_context *psp) 1862 { 1863 int ret; 1864 1865 /* 1866 * TODO: bypass the terminate in sriov for now 1867 */ 1868 if (amdgpu_sriov_vf(psp->adev)) 1869 return 0; 1870 1871 if (!psp->dtm_context.context.initialized) 1872 return 0; 1873 1874 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1875 1876 psp->dtm_context.context.initialized = false; 1877 1878 return ret; 1879 } 1880 // DTM end 1881 1882 // RAP start 1883 static int psp_rap_initialize(struct psp_context *psp) 1884 { 1885 int ret; 1886 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1887 1888 /* 1889 * TODO: bypass the initialize in sriov for now 1890 */ 1891 if (amdgpu_sriov_vf(psp->adev)) 1892 return 0; 1893 1894 if (!psp->rap_context.context.bin_desc.size_bytes || 1895 !psp->rap_context.context.bin_desc.start_addr) { 1896 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1897 return 0; 1898 } 1899 1900 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1901 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1902 1903 if (!psp->rap_context.context.mem_context.shared_buf) { 1904 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1905 if (ret) 1906 return ret; 1907 } 1908 1909 ret = psp_ta_load(psp, &psp->rap_context.context); 1910 if (!ret) { 1911 psp->rap_context.context.initialized = true; 1912 mutex_init(&psp->rap_context.mutex); 1913 } else 1914 return ret; 1915 1916 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1917 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1918 psp_rap_terminate(psp); 1919 /* free rap shared memory */ 1920 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1921 1922 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1923 ret, status); 1924 1925 return ret; 1926 } 1927 1928 return 0; 1929 } 1930 1931 static int psp_rap_terminate(struct psp_context *psp) 1932 { 1933 int ret; 1934 1935 if (!psp->rap_context.context.initialized) 1936 return 0; 1937 1938 ret = psp_ta_unload(psp, &psp->rap_context.context); 1939 1940 psp->rap_context.context.initialized = false; 1941 1942 return ret; 1943 } 1944 1945 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1946 { 1947 struct ta_rap_shared_memory *rap_cmd; 1948 int ret = 0; 1949 1950 if (!psp->rap_context.context.initialized) 1951 return 0; 1952 1953 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1954 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1955 return -EINVAL; 1956 1957 mutex_lock(&psp->rap_context.mutex); 1958 1959 rap_cmd = (struct ta_rap_shared_memory *) 1960 psp->rap_context.context.mem_context.shared_buf; 1961 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1962 1963 rap_cmd->cmd_id = ta_cmd_id; 1964 rap_cmd->validation_method_id = METHOD_A; 1965 1966 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1967 if (ret) 1968 goto out_unlock; 1969 1970 if (status) 1971 *status = rap_cmd->rap_status; 1972 1973 out_unlock: 1974 mutex_unlock(&psp->rap_context.mutex); 1975 1976 return ret; 1977 } 1978 // RAP end 1979 1980 /* securedisplay start */ 1981 static int psp_securedisplay_initialize(struct psp_context *psp) 1982 { 1983 int ret; 1984 struct ta_securedisplay_cmd *securedisplay_cmd; 1985 1986 /* 1987 * TODO: bypass the initialize in sriov for now 1988 */ 1989 if (amdgpu_sriov_vf(psp->adev)) 1990 return 0; 1991 1992 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1993 !psp->securedisplay_context.context.bin_desc.start_addr) { 1994 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1995 return 0; 1996 } 1997 1998 psp->securedisplay_context.context.mem_context.shared_mem_size = 1999 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 2000 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2001 2002 if (!psp->securedisplay_context.context.initialized) { 2003 ret = psp_ta_init_shared_buf(psp, 2004 &psp->securedisplay_context.context.mem_context); 2005 if (ret) 2006 return ret; 2007 } 2008 2009 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 2010 if (!ret) { 2011 psp->securedisplay_context.context.initialized = true; 2012 mutex_init(&psp->securedisplay_context.mutex); 2013 } else 2014 return ret; 2015 2016 mutex_lock(&psp->securedisplay_context.mutex); 2017 2018 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2019 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2020 2021 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2022 2023 mutex_unlock(&psp->securedisplay_context.mutex); 2024 2025 if (ret) { 2026 psp_securedisplay_terminate(psp); 2027 /* free securedisplay shared memory */ 2028 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 2029 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2030 return -EINVAL; 2031 } 2032 2033 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2034 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2035 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2036 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2037 /* don't try again */ 2038 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2039 } 2040 2041 return 0; 2042 } 2043 2044 static int psp_securedisplay_terminate(struct psp_context *psp) 2045 { 2046 int ret; 2047 2048 /* 2049 * TODO:bypass the terminate in sriov for now 2050 */ 2051 if (amdgpu_sriov_vf(psp->adev)) 2052 return 0; 2053 2054 if (!psp->securedisplay_context.context.initialized) 2055 return 0; 2056 2057 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 2058 2059 psp->securedisplay_context.context.initialized = false; 2060 2061 return ret; 2062 } 2063 2064 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2065 { 2066 int ret; 2067 2068 if (!psp->securedisplay_context.context.initialized) 2069 return -EINVAL; 2070 2071 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2072 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 2073 return -EINVAL; 2074 2075 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2076 2077 return ret; 2078 } 2079 /* SECUREDISPLAY end */ 2080 2081 static int psp_hw_start(struct psp_context *psp) 2082 { 2083 struct amdgpu_device *adev = psp->adev; 2084 int ret; 2085 2086 if (!amdgpu_sriov_vf(adev)) { 2087 if ((is_psp_fw_valid(psp->kdb)) && 2088 (psp->funcs->bootloader_load_kdb != NULL)) { 2089 ret = psp_bootloader_load_kdb(psp); 2090 if (ret) { 2091 DRM_ERROR("PSP load kdb failed!\n"); 2092 return ret; 2093 } 2094 } 2095 2096 if ((is_psp_fw_valid(psp->spl)) && 2097 (psp->funcs->bootloader_load_spl != NULL)) { 2098 ret = psp_bootloader_load_spl(psp); 2099 if (ret) { 2100 DRM_ERROR("PSP load spl failed!\n"); 2101 return ret; 2102 } 2103 } 2104 2105 if ((is_psp_fw_valid(psp->sys)) && 2106 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2107 ret = psp_bootloader_load_sysdrv(psp); 2108 if (ret) { 2109 DRM_ERROR("PSP load sys drv failed!\n"); 2110 return ret; 2111 } 2112 } 2113 2114 if ((is_psp_fw_valid(psp->soc_drv)) && 2115 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2116 ret = psp_bootloader_load_soc_drv(psp); 2117 if (ret) { 2118 DRM_ERROR("PSP load soc drv failed!\n"); 2119 return ret; 2120 } 2121 } 2122 2123 if ((is_psp_fw_valid(psp->intf_drv)) && 2124 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2125 ret = psp_bootloader_load_intf_drv(psp); 2126 if (ret) { 2127 DRM_ERROR("PSP load intf drv failed!\n"); 2128 return ret; 2129 } 2130 } 2131 2132 if ((is_psp_fw_valid(psp->dbg_drv)) && 2133 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2134 ret = psp_bootloader_load_dbg_drv(psp); 2135 if (ret) { 2136 DRM_ERROR("PSP load dbg drv failed!\n"); 2137 return ret; 2138 } 2139 } 2140 2141 if ((is_psp_fw_valid(psp->ras_drv)) && 2142 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2143 ret = psp_bootloader_load_ras_drv(psp); 2144 if (ret) { 2145 DRM_ERROR("PSP load ras_drv failed!\n"); 2146 return ret; 2147 } 2148 } 2149 2150 if ((is_psp_fw_valid(psp->sos)) && 2151 (psp->funcs->bootloader_load_sos != NULL)) { 2152 ret = psp_bootloader_load_sos(psp); 2153 if (ret) { 2154 DRM_ERROR("PSP load sos failed!\n"); 2155 return ret; 2156 } 2157 } 2158 } 2159 2160 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2161 if (ret) { 2162 DRM_ERROR("PSP create ring failed!\n"); 2163 return ret; 2164 } 2165 2166 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2167 goto skip_pin_bo; 2168 2169 if (!psp_boottime_tmr(psp)) { 2170 ret = psp_tmr_init(psp); 2171 if (ret) { 2172 DRM_ERROR("PSP tmr init failed!\n"); 2173 return ret; 2174 } 2175 } 2176 2177 skip_pin_bo: 2178 /* 2179 * For ASICs with DF Cstate management centralized 2180 * to PMFW, TMR setup should be performed after PMFW 2181 * loaded and before other non-psp firmware loaded. 2182 */ 2183 if (psp->pmfw_centralized_cstate_management) { 2184 ret = psp_load_smu_fw(psp); 2185 if (ret) 2186 return ret; 2187 } 2188 2189 ret = psp_tmr_load(psp); 2190 if (ret) { 2191 DRM_ERROR("PSP load tmr failed!\n"); 2192 return ret; 2193 } 2194 2195 return 0; 2196 } 2197 2198 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2199 enum psp_gfx_fw_type *type) 2200 { 2201 switch (ucode->ucode_id) { 2202 case AMDGPU_UCODE_ID_CAP: 2203 *type = GFX_FW_TYPE_CAP; 2204 break; 2205 case AMDGPU_UCODE_ID_SDMA0: 2206 *type = GFX_FW_TYPE_SDMA0; 2207 break; 2208 case AMDGPU_UCODE_ID_SDMA1: 2209 *type = GFX_FW_TYPE_SDMA1; 2210 break; 2211 case AMDGPU_UCODE_ID_SDMA2: 2212 *type = GFX_FW_TYPE_SDMA2; 2213 break; 2214 case AMDGPU_UCODE_ID_SDMA3: 2215 *type = GFX_FW_TYPE_SDMA3; 2216 break; 2217 case AMDGPU_UCODE_ID_SDMA4: 2218 *type = GFX_FW_TYPE_SDMA4; 2219 break; 2220 case AMDGPU_UCODE_ID_SDMA5: 2221 *type = GFX_FW_TYPE_SDMA5; 2222 break; 2223 case AMDGPU_UCODE_ID_SDMA6: 2224 *type = GFX_FW_TYPE_SDMA6; 2225 break; 2226 case AMDGPU_UCODE_ID_SDMA7: 2227 *type = GFX_FW_TYPE_SDMA7; 2228 break; 2229 case AMDGPU_UCODE_ID_CP_MES: 2230 *type = GFX_FW_TYPE_CP_MES; 2231 break; 2232 case AMDGPU_UCODE_ID_CP_MES_DATA: 2233 *type = GFX_FW_TYPE_MES_STACK; 2234 break; 2235 case AMDGPU_UCODE_ID_CP_MES1: 2236 *type = GFX_FW_TYPE_CP_MES_KIQ; 2237 break; 2238 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2239 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2240 break; 2241 case AMDGPU_UCODE_ID_CP_CE: 2242 *type = GFX_FW_TYPE_CP_CE; 2243 break; 2244 case AMDGPU_UCODE_ID_CP_PFP: 2245 *type = GFX_FW_TYPE_CP_PFP; 2246 break; 2247 case AMDGPU_UCODE_ID_CP_ME: 2248 *type = GFX_FW_TYPE_CP_ME; 2249 break; 2250 case AMDGPU_UCODE_ID_CP_MEC1: 2251 *type = GFX_FW_TYPE_CP_MEC; 2252 break; 2253 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2254 *type = GFX_FW_TYPE_CP_MEC_ME1; 2255 break; 2256 case AMDGPU_UCODE_ID_CP_MEC2: 2257 *type = GFX_FW_TYPE_CP_MEC; 2258 break; 2259 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2260 *type = GFX_FW_TYPE_CP_MEC_ME2; 2261 break; 2262 case AMDGPU_UCODE_ID_RLC_P: 2263 *type = GFX_FW_TYPE_RLC_P; 2264 break; 2265 case AMDGPU_UCODE_ID_RLC_V: 2266 *type = GFX_FW_TYPE_RLC_V; 2267 break; 2268 case AMDGPU_UCODE_ID_RLC_G: 2269 *type = GFX_FW_TYPE_RLC_G; 2270 break; 2271 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2272 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2273 break; 2274 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2275 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2276 break; 2277 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2278 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2279 break; 2280 case AMDGPU_UCODE_ID_RLC_IRAM: 2281 *type = GFX_FW_TYPE_RLC_IRAM; 2282 break; 2283 case AMDGPU_UCODE_ID_RLC_DRAM: 2284 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2285 break; 2286 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2287 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2288 break; 2289 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2290 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2291 break; 2292 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2293 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2294 break; 2295 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2296 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2297 break; 2298 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2299 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2300 break; 2301 case AMDGPU_UCODE_ID_SMC: 2302 *type = GFX_FW_TYPE_SMU; 2303 break; 2304 case AMDGPU_UCODE_ID_PPTABLE: 2305 *type = GFX_FW_TYPE_PPTABLE; 2306 break; 2307 case AMDGPU_UCODE_ID_UVD: 2308 *type = GFX_FW_TYPE_UVD; 2309 break; 2310 case AMDGPU_UCODE_ID_UVD1: 2311 *type = GFX_FW_TYPE_UVD1; 2312 break; 2313 case AMDGPU_UCODE_ID_VCE: 2314 *type = GFX_FW_TYPE_VCE; 2315 break; 2316 case AMDGPU_UCODE_ID_VCN: 2317 *type = GFX_FW_TYPE_VCN; 2318 break; 2319 case AMDGPU_UCODE_ID_VCN1: 2320 *type = GFX_FW_TYPE_VCN1; 2321 break; 2322 case AMDGPU_UCODE_ID_DMCU_ERAM: 2323 *type = GFX_FW_TYPE_DMCU_ERAM; 2324 break; 2325 case AMDGPU_UCODE_ID_DMCU_INTV: 2326 *type = GFX_FW_TYPE_DMCU_ISR; 2327 break; 2328 case AMDGPU_UCODE_ID_VCN0_RAM: 2329 *type = GFX_FW_TYPE_VCN0_RAM; 2330 break; 2331 case AMDGPU_UCODE_ID_VCN1_RAM: 2332 *type = GFX_FW_TYPE_VCN1_RAM; 2333 break; 2334 case AMDGPU_UCODE_ID_DMCUB: 2335 *type = GFX_FW_TYPE_DMUB; 2336 break; 2337 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2338 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2339 break; 2340 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2341 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2342 break; 2343 case AMDGPU_UCODE_ID_IMU_I: 2344 *type = GFX_FW_TYPE_IMU_I; 2345 break; 2346 case AMDGPU_UCODE_ID_IMU_D: 2347 *type = GFX_FW_TYPE_IMU_D; 2348 break; 2349 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2350 *type = GFX_FW_TYPE_RS64_PFP; 2351 break; 2352 case AMDGPU_UCODE_ID_CP_RS64_ME: 2353 *type = GFX_FW_TYPE_RS64_ME; 2354 break; 2355 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2356 *type = GFX_FW_TYPE_RS64_MEC; 2357 break; 2358 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2359 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2360 break; 2361 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2362 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2363 break; 2364 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2365 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2366 break; 2367 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2368 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2369 break; 2370 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2371 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2372 break; 2373 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2374 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2375 break; 2376 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2377 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2378 break; 2379 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2380 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2381 break; 2382 case AMDGPU_UCODE_ID_MAXIMUM: 2383 default: 2384 return -EINVAL; 2385 } 2386 2387 return 0; 2388 } 2389 2390 static void psp_print_fw_hdr(struct psp_context *psp, 2391 struct amdgpu_firmware_info *ucode) 2392 { 2393 struct amdgpu_device *adev = psp->adev; 2394 struct common_firmware_header *hdr; 2395 2396 switch (ucode->ucode_id) { 2397 case AMDGPU_UCODE_ID_SDMA0: 2398 case AMDGPU_UCODE_ID_SDMA1: 2399 case AMDGPU_UCODE_ID_SDMA2: 2400 case AMDGPU_UCODE_ID_SDMA3: 2401 case AMDGPU_UCODE_ID_SDMA4: 2402 case AMDGPU_UCODE_ID_SDMA5: 2403 case AMDGPU_UCODE_ID_SDMA6: 2404 case AMDGPU_UCODE_ID_SDMA7: 2405 hdr = (struct common_firmware_header *) 2406 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2407 amdgpu_ucode_print_sdma_hdr(hdr); 2408 break; 2409 case AMDGPU_UCODE_ID_CP_CE: 2410 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2411 amdgpu_ucode_print_gfx_hdr(hdr); 2412 break; 2413 case AMDGPU_UCODE_ID_CP_PFP: 2414 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2415 amdgpu_ucode_print_gfx_hdr(hdr); 2416 break; 2417 case AMDGPU_UCODE_ID_CP_ME: 2418 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2419 amdgpu_ucode_print_gfx_hdr(hdr); 2420 break; 2421 case AMDGPU_UCODE_ID_CP_MEC1: 2422 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2423 amdgpu_ucode_print_gfx_hdr(hdr); 2424 break; 2425 case AMDGPU_UCODE_ID_RLC_G: 2426 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2427 amdgpu_ucode_print_rlc_hdr(hdr); 2428 break; 2429 case AMDGPU_UCODE_ID_SMC: 2430 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2431 amdgpu_ucode_print_smc_hdr(hdr); 2432 break; 2433 default: 2434 break; 2435 } 2436 } 2437 2438 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2439 struct psp_gfx_cmd_resp *cmd) 2440 { 2441 int ret; 2442 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2443 2444 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2445 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2446 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2447 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2448 2449 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2450 if (ret) 2451 DRM_ERROR("Unknown firmware type\n"); 2452 2453 return ret; 2454 } 2455 2456 int psp_execute_ip_fw_load(struct psp_context *psp, 2457 struct amdgpu_firmware_info *ucode) 2458 { 2459 int ret = 0; 2460 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2461 2462 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2463 if (!ret) { 2464 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2465 psp->fence_buf_mc_addr); 2466 } 2467 2468 release_psp_cmd_buf(psp); 2469 2470 return ret; 2471 } 2472 2473 static int psp_load_smu_fw(struct psp_context *psp) 2474 { 2475 int ret; 2476 struct amdgpu_device *adev = psp->adev; 2477 struct amdgpu_firmware_info *ucode = 2478 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2479 struct amdgpu_ras *ras = psp->ras_context.ras; 2480 2481 /* 2482 * Skip SMU FW reloading in case of using BACO for runpm only, 2483 * as SMU is always alive. 2484 */ 2485 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)) 2486 return 0; 2487 2488 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2489 return 0; 2490 2491 if ((amdgpu_in_reset(adev) && 2492 ras && adev->ras_enabled && 2493 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2494 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2495 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2496 if (ret) 2497 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2498 } 2499 2500 ret = psp_execute_ip_fw_load(psp, ucode); 2501 2502 if (ret) 2503 DRM_ERROR("PSP load smu failed!\n"); 2504 2505 return ret; 2506 } 2507 2508 static bool fw_load_skip_check(struct psp_context *psp, 2509 struct amdgpu_firmware_info *ucode) 2510 { 2511 if (!ucode->fw || !ucode->ucode_size) 2512 return true; 2513 2514 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2515 (psp_smu_reload_quirk(psp) || 2516 psp->autoload_supported || 2517 psp->pmfw_centralized_cstate_management)) 2518 return true; 2519 2520 if (amdgpu_sriov_vf(psp->adev) && 2521 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 2522 return true; 2523 2524 if (psp->autoload_supported && 2525 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2526 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2527 /* skip mec JT when autoload is enabled */ 2528 return true; 2529 2530 return false; 2531 } 2532 2533 int psp_load_fw_list(struct psp_context *psp, 2534 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2535 { 2536 int ret = 0, i; 2537 struct amdgpu_firmware_info *ucode; 2538 2539 for (i = 0; i < ucode_count; ++i) { 2540 ucode = ucode_list[i]; 2541 psp_print_fw_hdr(psp, ucode); 2542 ret = psp_execute_ip_fw_load(psp, ucode); 2543 if (ret) 2544 return ret; 2545 } 2546 return ret; 2547 } 2548 2549 static int psp_load_non_psp_fw(struct psp_context *psp) 2550 { 2551 int i, ret; 2552 struct amdgpu_firmware_info *ucode; 2553 struct amdgpu_device *adev = psp->adev; 2554 2555 if (psp->autoload_supported && 2556 !psp->pmfw_centralized_cstate_management) { 2557 ret = psp_load_smu_fw(psp); 2558 if (ret) 2559 return ret; 2560 } 2561 2562 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2563 ucode = &adev->firmware.ucode[i]; 2564 2565 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2566 !fw_load_skip_check(psp, ucode)) { 2567 ret = psp_load_smu_fw(psp); 2568 if (ret) 2569 return ret; 2570 continue; 2571 } 2572 2573 if (fw_load_skip_check(psp, ucode)) 2574 continue; 2575 2576 if (psp->autoload_supported && 2577 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2578 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2579 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2580 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2581 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2582 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2583 /* PSP only receive one SDMA fw for sienna_cichlid, 2584 * as all four sdma fw are same 2585 */ 2586 continue; 2587 2588 psp_print_fw_hdr(psp, ucode); 2589 2590 ret = psp_execute_ip_fw_load(psp, ucode); 2591 if (ret) 2592 return ret; 2593 2594 /* Start rlc autoload after psp recieved all the gfx firmware */ 2595 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2596 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 2597 ret = psp_rlc_autoload_start(psp); 2598 if (ret) { 2599 DRM_ERROR("Failed to start rlc autoload\n"); 2600 return ret; 2601 } 2602 } 2603 } 2604 2605 return 0; 2606 } 2607 2608 static int psp_load_fw(struct amdgpu_device *adev) 2609 { 2610 int ret; 2611 struct psp_context *psp = &adev->psp; 2612 2613 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2614 /* should not destroy ring, only stop */ 2615 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2616 } else { 2617 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2618 2619 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2620 if (ret) { 2621 DRM_ERROR("PSP ring init failed!\n"); 2622 goto failed; 2623 } 2624 } 2625 2626 ret = psp_hw_start(psp); 2627 if (ret) 2628 goto failed; 2629 2630 ret = psp_load_non_psp_fw(psp); 2631 if (ret) 2632 goto failed1; 2633 2634 ret = psp_asd_initialize(psp); 2635 if (ret) { 2636 DRM_ERROR("PSP load asd failed!\n"); 2637 goto failed1; 2638 } 2639 2640 ret = psp_rl_load(adev); 2641 if (ret) { 2642 DRM_ERROR("PSP load RL failed!\n"); 2643 goto failed1; 2644 } 2645 2646 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2647 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2648 ret = psp_xgmi_initialize(psp, false, true); 2649 /* Warning the XGMI seesion initialize failure 2650 * Instead of stop driver initialization 2651 */ 2652 if (ret) 2653 dev_err(psp->adev->dev, 2654 "XGMI: Failed to initialize XGMI session\n"); 2655 } 2656 } 2657 2658 if (psp->ta_fw) { 2659 ret = psp_ras_initialize(psp); 2660 if (ret) 2661 dev_err(psp->adev->dev, 2662 "RAS: Failed to initialize RAS\n"); 2663 2664 ret = psp_hdcp_initialize(psp); 2665 if (ret) 2666 dev_err(psp->adev->dev, 2667 "HDCP: Failed to initialize HDCP\n"); 2668 2669 ret = psp_dtm_initialize(psp); 2670 if (ret) 2671 dev_err(psp->adev->dev, 2672 "DTM: Failed to initialize DTM\n"); 2673 2674 ret = psp_rap_initialize(psp); 2675 if (ret) 2676 dev_err(psp->adev->dev, 2677 "RAP: Failed to initialize RAP\n"); 2678 2679 ret = psp_securedisplay_initialize(psp); 2680 if (ret) 2681 dev_err(psp->adev->dev, 2682 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2683 } 2684 2685 return 0; 2686 2687 failed1: 2688 psp_free_shared_bufs(psp); 2689 failed: 2690 /* 2691 * all cleanup jobs (xgmi terminate, ras terminate, 2692 * ring destroy, cmd/fence/fw buffers destory, 2693 * psp->cmd destory) are delayed to psp_hw_fini 2694 */ 2695 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2696 return ret; 2697 } 2698 2699 static int psp_hw_init(void *handle) 2700 { 2701 int ret; 2702 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2703 2704 mutex_lock(&adev->firmware.mutex); 2705 /* 2706 * This sequence is just used on hw_init only once, no need on 2707 * resume. 2708 */ 2709 ret = amdgpu_ucode_init_bo(adev); 2710 if (ret) 2711 goto failed; 2712 2713 ret = psp_load_fw(adev); 2714 if (ret) { 2715 DRM_ERROR("PSP firmware loading failed\n"); 2716 goto failed; 2717 } 2718 2719 mutex_unlock(&adev->firmware.mutex); 2720 return 0; 2721 2722 failed: 2723 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2724 mutex_unlock(&adev->firmware.mutex); 2725 return -EINVAL; 2726 } 2727 2728 static int psp_hw_fini(void *handle) 2729 { 2730 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2731 struct psp_context *psp = &adev->psp; 2732 2733 if (psp->ta_fw) { 2734 psp_ras_terminate(psp); 2735 psp_securedisplay_terminate(psp); 2736 psp_rap_terminate(psp); 2737 psp_dtm_terminate(psp); 2738 psp_hdcp_terminate(psp); 2739 2740 if (adev->gmc.xgmi.num_physical_nodes > 1) 2741 psp_xgmi_terminate(psp); 2742 } 2743 2744 psp_asd_terminate(psp); 2745 psp_tmr_terminate(psp); 2746 2747 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2748 2749 return 0; 2750 } 2751 2752 static int psp_suspend(void *handle) 2753 { 2754 int ret = 0; 2755 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2756 struct psp_context *psp = &adev->psp; 2757 2758 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2759 psp->xgmi_context.context.initialized) { 2760 ret = psp_xgmi_terminate(psp); 2761 if (ret) { 2762 DRM_ERROR("Failed to terminate xgmi ta\n"); 2763 goto out; 2764 } 2765 } 2766 2767 if (psp->ta_fw) { 2768 ret = psp_ras_terminate(psp); 2769 if (ret) { 2770 DRM_ERROR("Failed to terminate ras ta\n"); 2771 goto out; 2772 } 2773 ret = psp_hdcp_terminate(psp); 2774 if (ret) { 2775 DRM_ERROR("Failed to terminate hdcp ta\n"); 2776 goto out; 2777 } 2778 ret = psp_dtm_terminate(psp); 2779 if (ret) { 2780 DRM_ERROR("Failed to terminate dtm ta\n"); 2781 goto out; 2782 } 2783 ret = psp_rap_terminate(psp); 2784 if (ret) { 2785 DRM_ERROR("Failed to terminate rap ta\n"); 2786 goto out; 2787 } 2788 ret = psp_securedisplay_terminate(psp); 2789 if (ret) { 2790 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2791 goto out; 2792 } 2793 } 2794 2795 ret = psp_asd_terminate(psp); 2796 if (ret) { 2797 DRM_ERROR("Failed to terminate asd\n"); 2798 goto out; 2799 } 2800 2801 ret = psp_tmr_terminate(psp); 2802 if (ret) { 2803 DRM_ERROR("Failed to terminate tmr\n"); 2804 goto out; 2805 } 2806 2807 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2808 if (ret) 2809 DRM_ERROR("PSP ring stop failed\n"); 2810 2811 out: 2812 return ret; 2813 } 2814 2815 static int psp_resume(void *handle) 2816 { 2817 int ret; 2818 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2819 struct psp_context *psp = &adev->psp; 2820 2821 DRM_INFO("PSP is resuming...\n"); 2822 2823 if (psp->mem_train_ctx.enable_mem_training) { 2824 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2825 if (ret) { 2826 DRM_ERROR("Failed to process memory training!\n"); 2827 return ret; 2828 } 2829 } 2830 2831 mutex_lock(&adev->firmware.mutex); 2832 2833 ret = psp_hw_start(psp); 2834 if (ret) 2835 goto failed; 2836 2837 ret = psp_load_non_psp_fw(psp); 2838 if (ret) 2839 goto failed; 2840 2841 ret = psp_asd_initialize(psp); 2842 if (ret) { 2843 DRM_ERROR("PSP load asd failed!\n"); 2844 goto failed; 2845 } 2846 2847 ret = psp_rl_load(adev); 2848 if (ret) { 2849 dev_err(adev->dev, "PSP load RL failed!\n"); 2850 goto failed; 2851 } 2852 2853 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2854 ret = psp_xgmi_initialize(psp, false, true); 2855 /* Warning the XGMI seesion initialize failure 2856 * Instead of stop driver initialization 2857 */ 2858 if (ret) 2859 dev_err(psp->adev->dev, 2860 "XGMI: Failed to initialize XGMI session\n"); 2861 } 2862 2863 if (psp->ta_fw) { 2864 ret = psp_ras_initialize(psp); 2865 if (ret) 2866 dev_err(psp->adev->dev, 2867 "RAS: Failed to initialize RAS\n"); 2868 2869 ret = psp_hdcp_initialize(psp); 2870 if (ret) 2871 dev_err(psp->adev->dev, 2872 "HDCP: Failed to initialize HDCP\n"); 2873 2874 ret = psp_dtm_initialize(psp); 2875 if (ret) 2876 dev_err(psp->adev->dev, 2877 "DTM: Failed to initialize DTM\n"); 2878 2879 ret = psp_rap_initialize(psp); 2880 if (ret) 2881 dev_err(psp->adev->dev, 2882 "RAP: Failed to initialize RAP\n"); 2883 2884 ret = psp_securedisplay_initialize(psp); 2885 if (ret) 2886 dev_err(psp->adev->dev, 2887 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2888 } 2889 2890 mutex_unlock(&adev->firmware.mutex); 2891 2892 return 0; 2893 2894 failed: 2895 DRM_ERROR("PSP resume failed\n"); 2896 mutex_unlock(&adev->firmware.mutex); 2897 return ret; 2898 } 2899 2900 int psp_gpu_reset(struct amdgpu_device *adev) 2901 { 2902 int ret; 2903 2904 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2905 return 0; 2906 2907 mutex_lock(&adev->psp.mutex); 2908 ret = psp_mode1_reset(&adev->psp); 2909 mutex_unlock(&adev->psp.mutex); 2910 2911 return ret; 2912 } 2913 2914 int psp_rlc_autoload_start(struct psp_context *psp) 2915 { 2916 int ret; 2917 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2918 2919 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2920 2921 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2922 psp->fence_buf_mc_addr); 2923 2924 release_psp_cmd_buf(psp); 2925 2926 return ret; 2927 } 2928 2929 int psp_ring_cmd_submit(struct psp_context *psp, 2930 uint64_t cmd_buf_mc_addr, 2931 uint64_t fence_mc_addr, 2932 int index) 2933 { 2934 unsigned int psp_write_ptr_reg = 0; 2935 struct psp_gfx_rb_frame *write_frame; 2936 struct psp_ring *ring = &psp->km_ring; 2937 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2938 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2939 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2940 struct amdgpu_device *adev = psp->adev; 2941 uint32_t ring_size_dw = ring->ring_size / 4; 2942 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2943 2944 /* KM (GPCOM) prepare write pointer */ 2945 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2946 2947 /* Update KM RB frame pointer to new frame */ 2948 /* write_frame ptr increments by size of rb_frame in bytes */ 2949 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2950 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2951 write_frame = ring_buffer_start; 2952 else 2953 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2954 /* Check invalid write_frame ptr address */ 2955 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2956 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2957 ring_buffer_start, ring_buffer_end, write_frame); 2958 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2959 return -EINVAL; 2960 } 2961 2962 /* Initialize KM RB frame */ 2963 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2964 2965 /* Update KM RB frame */ 2966 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2967 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2968 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2969 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2970 write_frame->fence_value = index; 2971 amdgpu_device_flush_hdp(adev, NULL); 2972 2973 /* Update the write Pointer in DWORDs */ 2974 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2975 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2976 return 0; 2977 } 2978 2979 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 2980 { 2981 struct amdgpu_device *adev = psp->adev; 2982 char fw_name[PSP_FW_NAME_LEN]; 2983 const struct psp_firmware_header_v1_0 *asd_hdr; 2984 int err = 0; 2985 2986 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2987 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name); 2988 if (err) 2989 goto out; 2990 2991 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2992 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2993 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2994 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2995 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2996 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2997 return 0; 2998 out: 2999 amdgpu_ucode_release(&adev->psp.asd_fw); 3000 return err; 3001 } 3002 3003 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 3004 { 3005 struct amdgpu_device *adev = psp->adev; 3006 char fw_name[PSP_FW_NAME_LEN]; 3007 const struct psp_firmware_header_v1_0 *toc_hdr; 3008 int err = 0; 3009 3010 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 3011 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name); 3012 if (err) 3013 goto out; 3014 3015 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3016 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3017 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3018 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3019 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3020 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3021 return 0; 3022 out: 3023 amdgpu_ucode_release(&adev->psp.toc_fw); 3024 return err; 3025 } 3026 3027 static int parse_sos_bin_descriptor(struct psp_context *psp, 3028 const struct psp_fw_bin_desc *desc, 3029 const struct psp_firmware_header_v2_0 *sos_hdr) 3030 { 3031 uint8_t *ucode_start_addr = NULL; 3032 3033 if (!psp || !desc || !sos_hdr) 3034 return -EINVAL; 3035 3036 ucode_start_addr = (uint8_t *)sos_hdr + 3037 le32_to_cpu(desc->offset_bytes) + 3038 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3039 3040 switch (desc->fw_type) { 3041 case PSP_FW_TYPE_PSP_SOS: 3042 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3043 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3044 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3045 psp->sos.start_addr = ucode_start_addr; 3046 break; 3047 case PSP_FW_TYPE_PSP_SYS_DRV: 3048 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3049 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3050 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3051 psp->sys.start_addr = ucode_start_addr; 3052 break; 3053 case PSP_FW_TYPE_PSP_KDB: 3054 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3055 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3056 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3057 psp->kdb.start_addr = ucode_start_addr; 3058 break; 3059 case PSP_FW_TYPE_PSP_TOC: 3060 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3061 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3062 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3063 psp->toc.start_addr = ucode_start_addr; 3064 break; 3065 case PSP_FW_TYPE_PSP_SPL: 3066 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3067 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3068 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3069 psp->spl.start_addr = ucode_start_addr; 3070 break; 3071 case PSP_FW_TYPE_PSP_RL: 3072 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3073 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3074 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3075 psp->rl.start_addr = ucode_start_addr; 3076 break; 3077 case PSP_FW_TYPE_PSP_SOC_DRV: 3078 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3079 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3080 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3081 psp->soc_drv.start_addr = ucode_start_addr; 3082 break; 3083 case PSP_FW_TYPE_PSP_INTF_DRV: 3084 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3085 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3086 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3087 psp->intf_drv.start_addr = ucode_start_addr; 3088 break; 3089 case PSP_FW_TYPE_PSP_DBG_DRV: 3090 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3091 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3092 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3093 psp->dbg_drv.start_addr = ucode_start_addr; 3094 break; 3095 case PSP_FW_TYPE_PSP_RAS_DRV: 3096 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3097 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3098 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3099 psp->ras_drv.start_addr = ucode_start_addr; 3100 break; 3101 default: 3102 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3103 break; 3104 } 3105 3106 return 0; 3107 } 3108 3109 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3110 { 3111 const struct psp_firmware_header_v1_0 *sos_hdr; 3112 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3113 uint8_t *ucode_array_start_addr; 3114 3115 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3116 ucode_array_start_addr = (uint8_t *)sos_hdr + 3117 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3118 3119 if (adev->gmc.xgmi.connected_to_cpu || 3120 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3121 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3122 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3123 3124 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3125 adev->psp.sys.start_addr = ucode_array_start_addr; 3126 3127 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3128 adev->psp.sos.start_addr = ucode_array_start_addr + 3129 le32_to_cpu(sos_hdr->sos.offset_bytes); 3130 } else { 3131 /* Load alternate PSP SOS FW */ 3132 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3133 3134 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3135 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3136 3137 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3138 adev->psp.sys.start_addr = ucode_array_start_addr + 3139 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3140 3141 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3142 adev->psp.sos.start_addr = ucode_array_start_addr + 3143 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3144 } 3145 3146 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3147 dev_warn(adev->dev, "PSP SOS FW not available"); 3148 return -EINVAL; 3149 } 3150 3151 return 0; 3152 } 3153 3154 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 3155 { 3156 struct amdgpu_device *adev = psp->adev; 3157 char fw_name[PSP_FW_NAME_LEN]; 3158 const struct psp_firmware_header_v1_0 *sos_hdr; 3159 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3160 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3161 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3162 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3163 int err = 0; 3164 uint8_t *ucode_array_start_addr; 3165 int fw_index = 0; 3166 3167 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3168 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name); 3169 if (err) 3170 goto out; 3171 3172 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3173 ucode_array_start_addr = (uint8_t *)sos_hdr + 3174 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3175 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3176 3177 switch (sos_hdr->header.header_version_major) { 3178 case 1: 3179 err = psp_init_sos_base_fw(adev); 3180 if (err) 3181 goto out; 3182 3183 if (sos_hdr->header.header_version_minor == 1) { 3184 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3185 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3186 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3187 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3188 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3189 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3190 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3191 } 3192 if (sos_hdr->header.header_version_minor == 2) { 3193 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3194 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3195 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3196 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3197 } 3198 if (sos_hdr->header.header_version_minor == 3) { 3199 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3200 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3201 adev->psp.toc.start_addr = ucode_array_start_addr + 3202 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3203 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3204 adev->psp.kdb.start_addr = ucode_array_start_addr + 3205 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3206 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3207 adev->psp.spl.start_addr = ucode_array_start_addr + 3208 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3209 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3210 adev->psp.rl.start_addr = ucode_array_start_addr + 3211 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3212 } 3213 break; 3214 case 2: 3215 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3216 3217 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3218 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3219 err = -EINVAL; 3220 goto out; 3221 } 3222 3223 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3224 err = parse_sos_bin_descriptor(psp, 3225 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3226 sos_hdr_v2_0); 3227 if (err) 3228 goto out; 3229 } 3230 break; 3231 default: 3232 dev_err(adev->dev, 3233 "unsupported psp sos firmware\n"); 3234 err = -EINVAL; 3235 goto out; 3236 } 3237 3238 return 0; 3239 out: 3240 amdgpu_ucode_release(&adev->psp.sos_fw); 3241 3242 return err; 3243 } 3244 3245 static int parse_ta_bin_descriptor(struct psp_context *psp, 3246 const struct psp_fw_bin_desc *desc, 3247 const struct ta_firmware_header_v2_0 *ta_hdr) 3248 { 3249 uint8_t *ucode_start_addr = NULL; 3250 3251 if (!psp || !desc || !ta_hdr) 3252 return -EINVAL; 3253 3254 ucode_start_addr = (uint8_t *)ta_hdr + 3255 le32_to_cpu(desc->offset_bytes) + 3256 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3257 3258 switch (desc->fw_type) { 3259 case TA_FW_TYPE_PSP_ASD: 3260 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3261 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3262 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3263 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3264 break; 3265 case TA_FW_TYPE_PSP_XGMI: 3266 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3267 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3268 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3269 break; 3270 case TA_FW_TYPE_PSP_RAS: 3271 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3272 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3273 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3274 break; 3275 case TA_FW_TYPE_PSP_HDCP: 3276 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3277 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3278 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3279 break; 3280 case TA_FW_TYPE_PSP_DTM: 3281 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3282 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3283 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3284 break; 3285 case TA_FW_TYPE_PSP_RAP: 3286 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3287 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3288 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3289 break; 3290 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3291 psp->securedisplay_context.context.bin_desc.fw_version = 3292 le32_to_cpu(desc->fw_version); 3293 psp->securedisplay_context.context.bin_desc.size_bytes = 3294 le32_to_cpu(desc->size_bytes); 3295 psp->securedisplay_context.context.bin_desc.start_addr = 3296 ucode_start_addr; 3297 break; 3298 default: 3299 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3300 break; 3301 } 3302 3303 return 0; 3304 } 3305 3306 static int parse_ta_v1_microcode(struct psp_context *psp) 3307 { 3308 const struct ta_firmware_header_v1_0 *ta_hdr; 3309 struct amdgpu_device *adev = psp->adev; 3310 3311 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 3312 3313 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 3314 return -EINVAL; 3315 3316 adev->psp.xgmi_context.context.bin_desc.fw_version = 3317 le32_to_cpu(ta_hdr->xgmi.fw_version); 3318 adev->psp.xgmi_context.context.bin_desc.size_bytes = 3319 le32_to_cpu(ta_hdr->xgmi.size_bytes); 3320 adev->psp.xgmi_context.context.bin_desc.start_addr = 3321 (uint8_t *)ta_hdr + 3322 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3323 3324 adev->psp.ras_context.context.bin_desc.fw_version = 3325 le32_to_cpu(ta_hdr->ras.fw_version); 3326 adev->psp.ras_context.context.bin_desc.size_bytes = 3327 le32_to_cpu(ta_hdr->ras.size_bytes); 3328 adev->psp.ras_context.context.bin_desc.start_addr = 3329 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 3330 le32_to_cpu(ta_hdr->ras.offset_bytes); 3331 3332 adev->psp.hdcp_context.context.bin_desc.fw_version = 3333 le32_to_cpu(ta_hdr->hdcp.fw_version); 3334 adev->psp.hdcp_context.context.bin_desc.size_bytes = 3335 le32_to_cpu(ta_hdr->hdcp.size_bytes); 3336 adev->psp.hdcp_context.context.bin_desc.start_addr = 3337 (uint8_t *)ta_hdr + 3338 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3339 3340 adev->psp.dtm_context.context.bin_desc.fw_version = 3341 le32_to_cpu(ta_hdr->dtm.fw_version); 3342 adev->psp.dtm_context.context.bin_desc.size_bytes = 3343 le32_to_cpu(ta_hdr->dtm.size_bytes); 3344 adev->psp.dtm_context.context.bin_desc.start_addr = 3345 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3346 le32_to_cpu(ta_hdr->dtm.offset_bytes); 3347 3348 adev->psp.securedisplay_context.context.bin_desc.fw_version = 3349 le32_to_cpu(ta_hdr->securedisplay.fw_version); 3350 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 3351 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 3352 adev->psp.securedisplay_context.context.bin_desc.start_addr = 3353 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3354 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 3355 3356 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 3357 3358 return 0; 3359 } 3360 3361 static int parse_ta_v2_microcode(struct psp_context *psp) 3362 { 3363 const struct ta_firmware_header_v2_0 *ta_hdr; 3364 struct amdgpu_device *adev = psp->adev; 3365 int err = 0; 3366 int ta_index = 0; 3367 3368 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3369 3370 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 3371 return -EINVAL; 3372 3373 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3374 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3375 return -EINVAL; 3376 } 3377 3378 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3379 err = parse_ta_bin_descriptor(psp, 3380 &ta_hdr->ta_fw_bin[ta_index], 3381 ta_hdr); 3382 if (err) 3383 return err; 3384 } 3385 3386 return 0; 3387 } 3388 3389 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 3390 { 3391 const struct common_firmware_header *hdr; 3392 struct amdgpu_device *adev = psp->adev; 3393 char fw_name[PSP_FW_NAME_LEN]; 3394 int err; 3395 3396 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3397 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name); 3398 if (err) 3399 return err; 3400 3401 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 3402 switch (le16_to_cpu(hdr->header_version_major)) { 3403 case 1: 3404 err = parse_ta_v1_microcode(psp); 3405 break; 3406 case 2: 3407 err = parse_ta_v2_microcode(psp); 3408 break; 3409 default: 3410 dev_err(adev->dev, "unsupported TA header version\n"); 3411 err = -EINVAL; 3412 } 3413 3414 if (err) 3415 amdgpu_ucode_release(&adev->psp.ta_fw); 3416 3417 return err; 3418 } 3419 3420 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 3421 { 3422 struct amdgpu_device *adev = psp->adev; 3423 char fw_name[PSP_FW_NAME_LEN]; 3424 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3425 struct amdgpu_firmware_info *info = NULL; 3426 int err = 0; 3427 3428 if (!amdgpu_sriov_vf(adev)) { 3429 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3430 return -EINVAL; 3431 } 3432 3433 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3434 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name); 3435 if (err) { 3436 if (err == -ENODEV) { 3437 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3438 err = 0; 3439 goto out; 3440 } 3441 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3442 } 3443 3444 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3445 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3446 info->fw = adev->psp.cap_fw; 3447 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3448 adev->psp.cap_fw->data; 3449 adev->firmware.fw_size += ALIGN( 3450 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3451 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3452 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3453 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3454 3455 return 0; 3456 3457 out: 3458 amdgpu_ucode_release(&adev->psp.cap_fw); 3459 return err; 3460 } 3461 3462 static int psp_set_clockgating_state(void *handle, 3463 enum amd_clockgating_state state) 3464 { 3465 return 0; 3466 } 3467 3468 static int psp_set_powergating_state(void *handle, 3469 enum amd_powergating_state state) 3470 { 3471 return 0; 3472 } 3473 3474 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3475 struct device_attribute *attr, 3476 char *buf) 3477 { 3478 struct drm_device *ddev = dev_get_drvdata(dev); 3479 struct amdgpu_device *adev = drm_to_adev(ddev); 3480 uint32_t fw_ver; 3481 int ret; 3482 3483 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3484 DRM_INFO("PSP block is not ready yet."); 3485 return -EBUSY; 3486 } 3487 3488 mutex_lock(&adev->psp.mutex); 3489 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3490 mutex_unlock(&adev->psp.mutex); 3491 3492 if (ret) { 3493 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3494 return ret; 3495 } 3496 3497 return sysfs_emit(buf, "%x\n", fw_ver); 3498 } 3499 3500 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3501 struct device_attribute *attr, 3502 const char *buf, 3503 size_t count) 3504 { 3505 struct drm_device *ddev = dev_get_drvdata(dev); 3506 struct amdgpu_device *adev = drm_to_adev(ddev); 3507 int ret, idx; 3508 char fw_name[100]; 3509 const struct firmware *usbc_pd_fw; 3510 struct amdgpu_bo *fw_buf_bo = NULL; 3511 uint64_t fw_pri_mc_addr; 3512 void *fw_pri_cpu_addr; 3513 3514 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3515 DRM_INFO("PSP block is not ready yet."); 3516 return -EBUSY; 3517 } 3518 3519 if (!drm_dev_enter(ddev, &idx)) 3520 return -ENODEV; 3521 3522 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3523 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3524 if (ret) 3525 goto fail; 3526 3527 /* LFB address which is aligned to 1MB boundary per PSP request */ 3528 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3529 AMDGPU_GEM_DOMAIN_VRAM | 3530 AMDGPU_GEM_DOMAIN_GTT, 3531 &fw_buf_bo, &fw_pri_mc_addr, 3532 &fw_pri_cpu_addr); 3533 if (ret) 3534 goto rel_buf; 3535 3536 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3537 3538 mutex_lock(&adev->psp.mutex); 3539 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3540 mutex_unlock(&adev->psp.mutex); 3541 3542 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3543 3544 rel_buf: 3545 release_firmware(usbc_pd_fw); 3546 fail: 3547 if (ret) { 3548 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3549 count = ret; 3550 } 3551 3552 drm_dev_exit(idx); 3553 return count; 3554 } 3555 3556 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3557 { 3558 int idx; 3559 3560 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3561 return; 3562 3563 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3564 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3565 3566 drm_dev_exit(idx); 3567 } 3568 3569 /** 3570 * DOC: usbc_pd_fw 3571 * Reading from this file will retrieve the USB-C PD firmware version. Writing to 3572 * this file will trigger the update process. 3573 */ 3574 static DEVICE_ATTR(usbc_pd_fw, 0644, 3575 psp_usbc_pd_fw_sysfs_read, 3576 psp_usbc_pd_fw_sysfs_write); 3577 3578 int is_psp_fw_valid(struct psp_bin_desc bin) 3579 { 3580 return bin.size_bytes; 3581 } 3582 3583 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3584 struct bin_attribute *bin_attr, 3585 char *buffer, loff_t pos, size_t count) 3586 { 3587 struct device *dev = kobj_to_dev(kobj); 3588 struct drm_device *ddev = dev_get_drvdata(dev); 3589 struct amdgpu_device *adev = drm_to_adev(ddev); 3590 3591 adev->psp.vbflash_done = false; 3592 3593 /* Safeguard against memory drain */ 3594 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3595 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B); 3596 kvfree(adev->psp.vbflash_tmp_buf); 3597 adev->psp.vbflash_tmp_buf = NULL; 3598 adev->psp.vbflash_image_size = 0; 3599 return -ENOMEM; 3600 } 3601 3602 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3603 if (!adev->psp.vbflash_tmp_buf) { 3604 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3605 if (!adev->psp.vbflash_tmp_buf) 3606 return -ENOMEM; 3607 } 3608 3609 mutex_lock(&adev->psp.mutex); 3610 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3611 adev->psp.vbflash_image_size += count; 3612 mutex_unlock(&adev->psp.mutex); 3613 3614 dev_dbg(adev->dev, "IFWI staged for update"); 3615 3616 return count; 3617 } 3618 3619 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3620 struct bin_attribute *bin_attr, char *buffer, 3621 loff_t pos, size_t count) 3622 { 3623 struct device *dev = kobj_to_dev(kobj); 3624 struct drm_device *ddev = dev_get_drvdata(dev); 3625 struct amdgpu_device *adev = drm_to_adev(ddev); 3626 struct amdgpu_bo *fw_buf_bo = NULL; 3627 uint64_t fw_pri_mc_addr; 3628 void *fw_pri_cpu_addr; 3629 int ret; 3630 3631 if (adev->psp.vbflash_image_size == 0) 3632 return -EINVAL; 3633 3634 dev_dbg(adev->dev, "PSP IFWI flash process initiated"); 3635 3636 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3637 AMDGPU_GPU_PAGE_SIZE, 3638 AMDGPU_GEM_DOMAIN_VRAM, 3639 &fw_buf_bo, 3640 &fw_pri_mc_addr, 3641 &fw_pri_cpu_addr); 3642 if (ret) 3643 goto rel_buf; 3644 3645 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3646 3647 mutex_lock(&adev->psp.mutex); 3648 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3649 mutex_unlock(&adev->psp.mutex); 3650 3651 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3652 3653 rel_buf: 3654 kvfree(adev->psp.vbflash_tmp_buf); 3655 adev->psp.vbflash_tmp_buf = NULL; 3656 adev->psp.vbflash_image_size = 0; 3657 3658 if (ret) { 3659 dev_err(adev->dev, "Failed to load IFWI, err = %d", ret); 3660 return ret; 3661 } 3662 3663 dev_dbg(adev->dev, "PSP IFWI flash process done"); 3664 return 0; 3665 } 3666 3667 /** 3668 * DOC: psp_vbflash 3669 * Writing to this file will stage an IFWI for update. Reading from this file 3670 * will trigger the update process. 3671 */ 3672 static struct bin_attribute psp_vbflash_bin_attr = { 3673 .attr = {.name = "psp_vbflash", .mode = 0660}, 3674 .size = 0, 3675 .write = amdgpu_psp_vbflash_write, 3676 .read = amdgpu_psp_vbflash_read, 3677 }; 3678 3679 /** 3680 * DOC: psp_vbflash_status 3681 * The status of the flash process. 3682 * 0: IFWI flash not complete. 3683 * 1: IFWI flash complete. 3684 */ 3685 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 3686 struct device_attribute *attr, 3687 char *buf) 3688 { 3689 struct drm_device *ddev = dev_get_drvdata(dev); 3690 struct amdgpu_device *adev = drm_to_adev(ddev); 3691 uint32_t vbflash_status; 3692 3693 vbflash_status = psp_vbflash_status(&adev->psp); 3694 if (!adev->psp.vbflash_done) 3695 vbflash_status = 0; 3696 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 3697 vbflash_status = 1; 3698 3699 return sysfs_emit(buf, "0x%x\n", vbflash_status); 3700 } 3701 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 3702 3703 static struct bin_attribute *bin_flash_attrs[] = { 3704 &psp_vbflash_bin_attr, 3705 NULL 3706 }; 3707 3708 static struct attribute *flash_attrs[] = { 3709 &dev_attr_psp_vbflash_status.attr, 3710 &dev_attr_usbc_pd_fw.attr, 3711 NULL 3712 }; 3713 3714 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 3715 { 3716 struct device *dev = kobj_to_dev(kobj); 3717 struct drm_device *ddev = dev_get_drvdata(dev); 3718 struct amdgpu_device *adev = drm_to_adev(ddev); 3719 3720 if (attr == &dev_attr_usbc_pd_fw.attr) 3721 return adev->psp.sup_pd_fw_up ? 0660 : 0; 3722 3723 return adev->psp.sup_ifwi_up ? 0440 : 0; 3724 } 3725 3726 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, 3727 struct bin_attribute *attr, 3728 int idx) 3729 { 3730 struct device *dev = kobj_to_dev(kobj); 3731 struct drm_device *ddev = dev_get_drvdata(dev); 3732 struct amdgpu_device *adev = drm_to_adev(ddev); 3733 3734 return adev->psp.sup_ifwi_up ? 0660 : 0; 3735 } 3736 3737 const struct attribute_group amdgpu_flash_attr_group = { 3738 .attrs = flash_attrs, 3739 .bin_attrs = bin_flash_attrs, 3740 .is_bin_visible = amdgpu_bin_flash_attr_is_visible, 3741 .is_visible = amdgpu_flash_attr_is_visible, 3742 }; 3743 3744 const struct amd_ip_funcs psp_ip_funcs = { 3745 .name = "psp", 3746 .early_init = psp_early_init, 3747 .late_init = NULL, 3748 .sw_init = psp_sw_init, 3749 .sw_fini = psp_sw_fini, 3750 .hw_init = psp_hw_init, 3751 .hw_fini = psp_hw_fini, 3752 .suspend = psp_suspend, 3753 .resume = psp_resume, 3754 .is_idle = NULL, 3755 .check_soft_reset = NULL, 3756 .wait_for_idle = NULL, 3757 .soft_reset = NULL, 3758 .set_clockgating_state = psp_set_clockgating_state, 3759 .set_powergating_state = psp_set_powergating_state, 3760 }; 3761 3762 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 3763 .type = AMD_IP_BLOCK_TYPE_PSP, 3764 .major = 3, 3765 .minor = 1, 3766 .rev = 0, 3767 .funcs = &psp_ip_funcs, 3768 }; 3769 3770 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 3771 .type = AMD_IP_BLOCK_TYPE_PSP, 3772 .major = 10, 3773 .minor = 0, 3774 .rev = 0, 3775 .funcs = &psp_ip_funcs, 3776 }; 3777 3778 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 3779 .type = AMD_IP_BLOCK_TYPE_PSP, 3780 .major = 11, 3781 .minor = 0, 3782 .rev = 0, 3783 .funcs = &psp_ip_funcs, 3784 }; 3785 3786 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3787 .type = AMD_IP_BLOCK_TYPE_PSP, 3788 .major = 11, 3789 .minor = 0, 3790 .rev = 8, 3791 .funcs = &psp_ip_funcs, 3792 }; 3793 3794 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 3795 .type = AMD_IP_BLOCK_TYPE_PSP, 3796 .major = 12, 3797 .minor = 0, 3798 .rev = 0, 3799 .funcs = &psp_ip_funcs, 3800 }; 3801 3802 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3803 .type = AMD_IP_BLOCK_TYPE_PSP, 3804 .major = 13, 3805 .minor = 0, 3806 .rev = 0, 3807 .funcs = &psp_ip_funcs, 3808 }; 3809 3810 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 3811 .type = AMD_IP_BLOCK_TYPE_PSP, 3812 .major = 13, 3813 .minor = 0, 3814 .rev = 4, 3815 .funcs = &psp_ip_funcs, 3816 }; 3817