13d093da0STao Zhou /* 23d093da0STao Zhou * Copyright (C) 2019 Advanced Micro Devices, Inc. 33d093da0STao Zhou * 43d093da0STao Zhou * Permission is hereby granted, free of charge, to any person obtaining a 53d093da0STao Zhou * copy of this software and associated documentation files (the "Software"), 63d093da0STao Zhou * to deal in the Software without restriction, including without limitation 73d093da0STao Zhou * the rights to use, copy, modify, merge, publish, distribute, sublicense, 83d093da0STao Zhou * and/or sell copies of the Software, and to permit persons to whom the 93d093da0STao Zhou * Software is furnished to do so, subject to the following conditions: 103d093da0STao Zhou * 113d093da0STao Zhou * The above copyright notice and this permission notice shall be included 123d093da0STao Zhou * in all copies or substantial portions of the Software. 133d093da0STao Zhou * 143d093da0STao Zhou * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 153d093da0STao Zhou * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 163d093da0STao Zhou * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 173d093da0STao Zhou * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 183d093da0STao Zhou * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 193d093da0STao Zhou * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 203d093da0STao Zhou */ 213d093da0STao Zhou #ifndef __AMDGPU_MMHUB_H__ 223d093da0STao Zhou #define __AMDGPU_MMHUB_H__ 233d093da0STao Zhou 245e67bba3Syipechai enum amdgpu_mmhub_ras_memory_id { 255e67bba3Syipechai AMDGPU_MMHUB_WGMI_PAGEMEM = 0, 268bc7b360SHawking Zhang AMDGPU_MMHUB_RGMI_PAGEMEM = 1, 278bc7b360SHawking Zhang AMDGPU_MMHUB_WDRAM_PAGEMEM = 2, 288bc7b360SHawking Zhang AMDGPU_MMHUB_RDRAM_PAGEMEM = 3, 299fb1506eSOak Zeng AMDGPU_MMHUB_WIO_CMDMEM = 4, 3098a0f868STianci.Yin AMDGPU_MMHUB_RIO_CMDMEM = 5, 319fb1506eSOak Zeng AMDGPU_MMHUB_WGMI_CMDMEM = 6, 329fb1506eSOak Zeng AMDGPU_MMHUB_RGMI_CMDMEM = 7, 339fb1506eSOak Zeng AMDGPU_MMHUB_WDRAM_CMDMEM = 8, 349fb1506eSOak Zeng AMDGPU_MMHUB_RDRAM_CMDMEM = 9, 359fb1506eSOak Zeng AMDGPU_MMHUB_MAM_DMEM0 = 10, 369fb1506eSOak Zeng AMDGPU_MMHUB_MAM_DMEM1 = 11, 379fb1506eSOak Zeng AMDGPU_MMHUB_MAM_DMEM2 = 12, 3825faeddcSEvan Quan AMDGPU_MMHUB_MAM_DMEM3 = 13, 399fb1506eSOak Zeng AMDGPU_MMHUB_WRET_TAGMEM = 19, 409fb1506eSOak Zeng AMDGPU_MMHUB_RRET_TAGMEM = 20, 419fb1506eSOak Zeng AMDGPU_MMHUB_WIO_DATAMEM = 21, 429fb1506eSOak Zeng AMDGPU_MMHUB_WGMI_DATAMEM = 22, 433d093da0STao Zhou AMDGPU_MMHUB_WDRAM_DATAMEM = 23, 443d093da0STao Zhou AMDGPU_MMHUB_MEMORY_BLOCK_LAST, 45d3a5a121STao Zhou }; 46d3a5a121STao Zhou 47d3a5a121STao Zhou struct amdgpu_mmhub_ras { 485e67bba3Syipechai struct amdgpu_ras_block_object ras_block; 49d3a5a121STao Zhou }; 50d3a5a121STao Zhou 51*fec70a86SHawking Zhang struct amdgpu_mmhub_funcs { 52*fec70a86SHawking Zhang u64 (*get_fb_location)(struct amdgpu_device *adev); 533d093da0STao Zhou u64 (*get_mc_fb_offset)(struct amdgpu_device *adev); 543d093da0STao Zhou void (*init)(struct amdgpu_device *adev); 55 int (*gart_enable)(struct amdgpu_device *adev); 56 void (*set_fault_enable_default)(struct amdgpu_device *adev, 57 bool value); 58 void (*gart_disable)(struct amdgpu_device *adev); 59 int (*set_clockgating)(struct amdgpu_device *adev, 60 enum amd_clockgating_state state); 61 void (*get_clockgating)(struct amdgpu_device *adev, u64 *flags); 62 void (*setup_vm_pt_regs)(struct amdgpu_device *adev, uint32_t vmid, 63 uint64_t page_table_base); 64 void (*update_power_gating)(struct amdgpu_device *adev, 65 bool enable); 66 }; 67 68 struct amdgpu_mmhub { 69 struct ras_common_if *ras_if; 70 const struct amdgpu_mmhub_funcs *funcs; 71 struct amdgpu_mmhub_ras *ras; 72 }; 73 74 int amdgpu_mmhub_ras_sw_init(struct amdgpu_device *adev); 75 76 #endif 77 78