1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 #ifndef __AMDGPU_GMC_H__ 27 #define __AMDGPU_GMC_H__ 28 29 #include <linux/types.h> 30 31 #include "amdgpu_irq.h" 32 #include "amdgpu_ras.h" 33 34 /* VA hole for 48bit addresses on Vega10 */ 35 #define AMDGPU_GMC_HOLE_START 0x0000800000000000ULL 36 #define AMDGPU_GMC_HOLE_END 0xffff800000000000ULL 37 38 /* 39 * Hardware is programmed as if the hole doesn't exists with start and end 40 * address values. 41 * 42 * This mask is used to remove the upper 16bits of the VA and so come up with 43 * the linear addr value. 44 */ 45 #define AMDGPU_GMC_HOLE_MASK 0x0000ffffffffffffULL 46 47 /* 48 * Ring size as power of two for the log of recent faults. 49 */ 50 #define AMDGPU_GMC_FAULT_RING_ORDER 8 51 #define AMDGPU_GMC_FAULT_RING_SIZE (1 << AMDGPU_GMC_FAULT_RING_ORDER) 52 53 /* 54 * Hash size as power of two for the log of recent faults 55 */ 56 #define AMDGPU_GMC_FAULT_HASH_ORDER 8 57 #define AMDGPU_GMC_FAULT_HASH_SIZE (1 << AMDGPU_GMC_FAULT_HASH_ORDER) 58 59 /* 60 * Number of IH timestamp ticks until a fault is considered handled 61 */ 62 #define AMDGPU_GMC_FAULT_TIMEOUT 5000ULL 63 64 struct firmware; 65 66 enum amdgpu_memory_partition { 67 UNKNOWN_MEMORY_PARTITION_MODE = 0, 68 AMDGPU_NPS1_PARTITION_MODE = 1, 69 AMDGPU_NPS2_PARTITION_MODE = 2, 70 AMDGPU_NPS3_PARTITION_MODE = 3, 71 AMDGPU_NPS4_PARTITION_MODE = 4, 72 AMDGPU_NPS6_PARTITION_MODE = 6, 73 AMDGPU_NPS8_PARTITION_MODE = 8, 74 }; 75 76 /* 77 * GMC page fault information 78 */ 79 struct amdgpu_gmc_fault { 80 uint64_t timestamp:48; 81 uint64_t next:AMDGPU_GMC_FAULT_RING_ORDER; 82 atomic64_t key; 83 uint64_t timestamp_expiry:48; 84 }; 85 86 /* 87 * VMHUB structures, functions & helpers 88 */ 89 struct amdgpu_vmhub_funcs { 90 void (*print_l2_protection_fault_status)(struct amdgpu_device *adev, 91 uint32_t status); 92 uint32_t (*get_invalidate_req)(unsigned int vmid, uint32_t flush_type); 93 }; 94 95 struct amdgpu_vmhub { 96 uint32_t ctx0_ptb_addr_lo32; 97 uint32_t ctx0_ptb_addr_hi32; 98 uint32_t vm_inv_eng0_sem; 99 uint32_t vm_inv_eng0_req; 100 uint32_t vm_inv_eng0_ack; 101 uint32_t vm_context0_cntl; 102 uint32_t vm_l2_pro_fault_status; 103 uint32_t vm_l2_pro_fault_cntl; 104 105 /* 106 * store the register distances between two continuous context domain 107 * and invalidation engine. 108 */ 109 uint32_t ctx_distance; 110 uint32_t ctx_addr_distance; /* include LO32/HI32 */ 111 uint32_t eng_distance; 112 uint32_t eng_addr_distance; /* include LO32/HI32 */ 113 114 uint32_t vm_cntx_cntl; 115 uint32_t vm_cntx_cntl_vm_fault; 116 uint32_t vm_l2_bank_select_reserved_cid2; 117 118 uint32_t vm_contexts_disable; 119 120 const struct amdgpu_vmhub_funcs *vmhub_funcs; 121 }; 122 123 /* 124 * GPU MC structures, functions & helpers 125 */ 126 struct amdgpu_gmc_funcs { 127 /* flush the vm tlb via mmio */ 128 void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid, 129 uint32_t vmhub, uint32_t flush_type); 130 /* flush the vm tlb via pasid */ 131 int (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid, 132 uint32_t flush_type, bool all_hub, 133 uint32_t inst); 134 /* flush the vm tlb via ring */ 135 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid, 136 uint64_t pd_addr); 137 /* Change the VMID -> PASID mapping */ 138 void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid, 139 unsigned pasid); 140 /* enable/disable PRT support */ 141 void (*set_prt)(struct amdgpu_device *adev, bool enable); 142 /* map mtype to hardware flags */ 143 uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags); 144 /* get the pde for a given mc addr */ 145 void (*get_vm_pde)(struct amdgpu_device *adev, int level, 146 u64 *dst, u64 *flags); 147 /* get the pte flags to use for a BO VA mapping */ 148 void (*get_vm_pte)(struct amdgpu_device *adev, 149 struct amdgpu_bo_va_mapping *mapping, 150 uint64_t *flags); 151 /* get the amount of memory used by the vbios for pre-OS console */ 152 unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev); 153 154 enum amdgpu_memory_partition (*query_mem_partition_mode)( 155 struct amdgpu_device *adev); 156 }; 157 158 struct amdgpu_xgmi_ras { 159 struct amdgpu_ras_block_object ras_block; 160 }; 161 162 struct amdgpu_xgmi { 163 /* from psp */ 164 u64 node_id; 165 u64 hive_id; 166 /* fixed per family */ 167 u64 node_segment_size; 168 /* physical node (0-3) */ 169 unsigned physical_node_id; 170 /* number of nodes (0-4) */ 171 unsigned num_physical_nodes; 172 /* gpu list in the same hive */ 173 struct list_head head; 174 bool supported; 175 struct ras_common_if *ras_if; 176 bool connected_to_cpu; 177 bool pending_reset; 178 struct amdgpu_xgmi_ras *ras; 179 }; 180 181 struct amdgpu_mem_partition_info { 182 union { 183 struct { 184 uint32_t fpfn; 185 uint32_t lpfn; 186 } range; 187 struct { 188 int node; 189 } numa; 190 }; 191 uint64_t size; 192 }; 193 194 #define INVALID_PFN -1 195 196 struct amdgpu_gmc { 197 /* FB's physical address in MMIO space (for CPU to 198 * map FB). This is different compared to the agp/ 199 * gart/vram_start/end field as the later is from 200 * GPU's view and aper_base is from CPU's view. 201 */ 202 resource_size_t aper_size; 203 resource_size_t aper_base; 204 /* for some chips with <= 32MB we need to lie 205 * about vram size near mc fb location */ 206 u64 mc_vram_size; 207 u64 visible_vram_size; 208 /* AGP aperture start and end in MC address space 209 * Driver find a hole in the MC address space 210 * to place AGP by setting MC_VM_AGP_BOT/TOP registers 211 * Under VMID0, logical address == MC address. AGP 212 * aperture maps to physical bus or IOVA addressed. 213 * AGP aperture is used to simulate FB in ZFB case. 214 * AGP aperture is also used for page table in system 215 * memory (mainly for APU). 216 * 217 */ 218 u64 agp_size; 219 u64 agp_start; 220 u64 agp_end; 221 /* GART aperture start and end in MC address space 222 * Driver find a hole in the MC address space 223 * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR 224 * registers 225 * Under VMID0, logical address inside GART aperture will 226 * be translated through gpuvm gart page table to access 227 * paged system memory 228 */ 229 u64 gart_size; 230 u64 gart_start; 231 u64 gart_end; 232 /* Frame buffer aperture of this GPU device. Different from 233 * fb_start (see below), this only covers the local GPU device. 234 * If driver uses FB aperture to access FB, driver get fb_start from 235 * MC_VM_FB_LOCATION_BASE (set by vbios) and calculate vram_start 236 * of this local device by adding an offset inside the XGMI hive. 237 * If driver uses GART table for VMID0 FB access, driver finds a hole in 238 * VMID0's virtual address space to place the SYSVM aperture inside 239 * which the first part is vram and the second part is gart (covering 240 * system ram). 241 */ 242 u64 vram_start; 243 u64 vram_end; 244 /* FB region , it's same as local vram region in single GPU, in XGMI 245 * configuration, this region covers all GPUs in the same hive , 246 * each GPU in the hive has the same view of this FB region . 247 * GPU0's vram starts at offset (0 * segment size) , 248 * GPU1 starts at offset (1 * segment size), etc. 249 */ 250 u64 fb_start; 251 u64 fb_end; 252 unsigned vram_width; 253 u64 real_vram_size; 254 int vram_mtrr; 255 u64 mc_mask; 256 const struct firmware *fw; /* MC firmware */ 257 uint32_t fw_version; 258 struct amdgpu_irq_src vm_fault; 259 uint32_t vram_type; 260 uint8_t vram_vendor; 261 uint32_t srbm_soft_reset; 262 bool prt_warning; 263 uint32_t sdpif_register; 264 /* apertures */ 265 u64 shared_aperture_start; 266 u64 shared_aperture_end; 267 u64 private_aperture_start; 268 u64 private_aperture_end; 269 /* protects concurrent invalidation */ 270 spinlock_t invalidate_lock; 271 bool translate_further; 272 struct kfd_vm_fault_info *vm_fault_info; 273 atomic_t vm_fault_info_updated; 274 275 struct amdgpu_gmc_fault fault_ring[AMDGPU_GMC_FAULT_RING_SIZE]; 276 struct { 277 uint64_t idx:AMDGPU_GMC_FAULT_RING_ORDER; 278 } fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE]; 279 uint64_t last_fault:AMDGPU_GMC_FAULT_RING_ORDER; 280 281 bool tmz_enabled; 282 bool is_app_apu; 283 284 struct amdgpu_mem_partition_info *mem_partitions; 285 uint8_t num_mem_partitions; 286 const struct amdgpu_gmc_funcs *gmc_funcs; 287 288 struct amdgpu_xgmi xgmi; 289 struct amdgpu_irq_src ecc_irq; 290 int noretry; 291 292 uint32_t vmid0_page_table_block_size; 293 uint32_t vmid0_page_table_depth; 294 struct amdgpu_bo *pdb0_bo; 295 /* CPU kmapped address of pdb0*/ 296 void *ptr_pdb0; 297 298 /* MALL size */ 299 u64 mall_size; 300 /* number of UMC instances */ 301 int num_umc; 302 /* mode2 save restore */ 303 u64 VM_L2_CNTL; 304 u64 VM_L2_CNTL2; 305 u64 VM_DUMMY_PAGE_FAULT_CNTL; 306 u64 VM_DUMMY_PAGE_FAULT_ADDR_LO32; 307 u64 VM_DUMMY_PAGE_FAULT_ADDR_HI32; 308 u64 VM_L2_PROTECTION_FAULT_CNTL; 309 u64 VM_L2_PROTECTION_FAULT_CNTL2; 310 u64 VM_L2_PROTECTION_FAULT_MM_CNTL3; 311 u64 VM_L2_PROTECTION_FAULT_MM_CNTL4; 312 u64 VM_L2_PROTECTION_FAULT_ADDR_LO32; 313 u64 VM_L2_PROTECTION_FAULT_ADDR_HI32; 314 u64 VM_DEBUG; 315 u64 VM_L2_MM_GROUP_RT_CLASSES; 316 u64 VM_L2_BANK_SELECT_RESERVED_CID; 317 u64 VM_L2_BANK_SELECT_RESERVED_CID2; 318 u64 VM_L2_CACHE_PARITY_CNTL; 319 u64 VM_L2_IH_LOG_CNTL; 320 u64 VM_CONTEXT_CNTL[16]; 321 u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[16]; 322 u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[16]; 323 u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[16]; 324 u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[16]; 325 u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[16]; 326 u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[16]; 327 u64 MC_VM_MX_L1_TLB_CNTL; 328 }; 329 330 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type))) 331 #define amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, type, allhub, inst) \ 332 ((adev)->gmc.gmc_funcs->flush_gpu_tlb_pasid \ 333 ((adev), (pasid), (type), (allhub), (inst))) 334 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr)) 335 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid)) 336 #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags)) 337 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags)) 338 #define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapping), (flags)) 339 #define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev)) 340 341 /** 342 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR 343 * 344 * @adev: amdgpu_device pointer 345 * 346 * Returns: 347 * True if full VRAM is visible through the BAR 348 */ 349 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc) 350 { 351 WARN_ON(gmc->real_vram_size < gmc->visible_vram_size); 352 353 return (gmc->real_vram_size == gmc->visible_vram_size); 354 } 355 356 /** 357 * amdgpu_gmc_sign_extend - sign extend the given gmc address 358 * 359 * @addr: address to extend 360 */ 361 static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr) 362 { 363 if (addr >= AMDGPU_GMC_HOLE_START) 364 addr |= AMDGPU_GMC_HOLE_END; 365 366 return addr; 367 } 368 369 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev); 370 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 371 uint64_t *addr, uint64_t *flags); 372 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 373 uint32_t gpu_page_idx, uint64_t addr, 374 uint64_t flags); 375 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo); 376 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo); 377 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc); 378 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 379 u64 base); 380 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, 381 struct amdgpu_gmc *mc); 382 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, 383 struct amdgpu_gmc *mc); 384 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, 385 struct amdgpu_ih_ring *ih, uint64_t addr, 386 uint16_t pasid, uint64_t timestamp); 387 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, 388 uint16_t pasid); 389 int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev); 390 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev); 391 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev); 392 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev); 393 394 extern void amdgpu_gmc_tmz_set(struct amdgpu_device *adev); 395 extern void amdgpu_gmc_noretry_set(struct amdgpu_device *adev); 396 397 extern void 398 amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, 399 bool enable); 400 401 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev); 402 403 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev); 404 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr); 405 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo); 406 uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo); 407 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev); 408 int amdgpu_gmc_sysfs_init(struct amdgpu_device *adev); 409 void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev); 410 411 #endif 412