xref: /openbmc/linux/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c (revision c0c45238fcf44b05c86f2f7d1dda136df7a83ff9)
1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 
27 #include <linux/io-64-nonatomic-lo-hi.h>
28 
29 #include "amdgpu.h"
30 #include "amdgpu_gmc.h"
31 #include "amdgpu_ras.h"
32 #include "amdgpu_xgmi.h"
33 
34 #include <drm/drm_drv.h>
35 
36 /**
37  * amdgpu_gmc_pdb0_alloc - allocate vram for pdb0
38  *
39  * @adev: amdgpu_device pointer
40  *
41  * Allocate video memory for pdb0 and map it for CPU access
42  * Returns 0 for success, error for failure.
43  */
44 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev)
45 {
46 	int r;
47 	struct amdgpu_bo_param bp;
48 	u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes;
49 	uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21;
50 	uint32_t npdes = (vram_size + (1ULL << pde0_page_shift) -1) >> pde0_page_shift;
51 
52 	memset(&bp, 0, sizeof(bp));
53 	bp.size = PAGE_ALIGN((npdes + 1) * 8);
54 	bp.byte_align = PAGE_SIZE;
55 	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
56 	bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
57 		AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
58 	bp.type = ttm_bo_type_kernel;
59 	bp.resv = NULL;
60 	bp.bo_ptr_size = sizeof(struct amdgpu_bo);
61 
62 	r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo);
63 	if (r)
64 		return r;
65 
66 	r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false);
67 	if (unlikely(r != 0))
68 		goto bo_reserve_failure;
69 
70 	r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM);
71 	if (r)
72 		goto bo_pin_failure;
73 	r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0);
74 	if (r)
75 		goto bo_kmap_failure;
76 
77 	amdgpu_bo_unreserve(adev->gmc.pdb0_bo);
78 	return 0;
79 
80 bo_kmap_failure:
81 	amdgpu_bo_unpin(adev->gmc.pdb0_bo);
82 bo_pin_failure:
83 	amdgpu_bo_unreserve(adev->gmc.pdb0_bo);
84 bo_reserve_failure:
85 	amdgpu_bo_unref(&adev->gmc.pdb0_bo);
86 	return r;
87 }
88 
89 /**
90  * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO
91  *
92  * @bo: the BO to get the PDE for
93  * @level: the level in the PD hirarchy
94  * @addr: resulting addr
95  * @flags: resulting flags
96  *
97  * Get the address and flags to be used for a PDE (Page Directory Entry).
98  */
99 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
100 			       uint64_t *addr, uint64_t *flags)
101 {
102 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
103 
104 	switch (bo->tbo.resource->mem_type) {
105 	case TTM_PL_TT:
106 		*addr = bo->tbo.ttm->dma_address[0];
107 		break;
108 	case TTM_PL_VRAM:
109 		*addr = amdgpu_bo_gpu_offset(bo);
110 		break;
111 	default:
112 		*addr = 0;
113 		break;
114 	}
115 	*flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, bo->tbo.resource);
116 	amdgpu_gmc_get_vm_pde(adev, level, addr, flags);
117 }
118 
119 /*
120  * amdgpu_gmc_pd_addr - return the address of the root directory
121  */
122 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
123 {
124 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
125 	uint64_t pd_addr;
126 
127 	/* TODO: move that into ASIC specific code */
128 	if (adev->asic_type >= CHIP_VEGA10) {
129 		uint64_t flags = AMDGPU_PTE_VALID;
130 
131 		amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags);
132 		pd_addr |= flags;
133 	} else {
134 		pd_addr = amdgpu_bo_gpu_offset(bo);
135 	}
136 	return pd_addr;
137 }
138 
139 /**
140  * amdgpu_gmc_set_pte_pde - update the page tables using CPU
141  *
142  * @adev: amdgpu_device pointer
143  * @cpu_pt_addr: cpu address of the page table
144  * @gpu_page_idx: entry in the page table to update
145  * @addr: dst addr to write into pte/pde
146  * @flags: access flags
147  *
148  * Update the page tables using CPU.
149  */
150 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
151 				uint32_t gpu_page_idx, uint64_t addr,
152 				uint64_t flags)
153 {
154 	void __iomem *ptr = (void *)cpu_pt_addr;
155 	uint64_t value;
156 
157 	/*
158 	 * The following is for PTE only. GART does not have PDEs.
159 	*/
160 	value = addr & 0x0000FFFFFFFFF000ULL;
161 	value |= flags;
162 	writeq(value, ptr + (gpu_page_idx * 8));
163 
164 	return 0;
165 }
166 
167 /**
168  * amdgpu_gmc_agp_addr - return the address in the AGP address space
169  *
170  * @bo: TTM BO which needs the address, must be in GTT domain
171  *
172  * Tries to figure out how to access the BO through the AGP aperture. Returns
173  * AMDGPU_BO_INVALID_OFFSET if that is not possible.
174  */
175 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo)
176 {
177 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
178 
179 	if (bo->ttm->num_pages != 1 || bo->ttm->caching == ttm_cached)
180 		return AMDGPU_BO_INVALID_OFFSET;
181 
182 	if (bo->ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size)
183 		return AMDGPU_BO_INVALID_OFFSET;
184 
185 	return adev->gmc.agp_start + bo->ttm->dma_address[0];
186 }
187 
188 /**
189  * amdgpu_gmc_vram_location - try to find VRAM location
190  *
191  * @adev: amdgpu device structure holding all necessary information
192  * @mc: memory controller structure holding memory information
193  * @base: base address at which to put VRAM
194  *
195  * Function will try to place VRAM at base address provided
196  * as parameter.
197  */
198 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
199 			      u64 base)
200 {
201 	uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
202 
203 	mc->vram_start = base;
204 	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
205 	if (limit && limit < mc->real_vram_size)
206 		mc->real_vram_size = limit;
207 
208 	if (mc->xgmi.num_physical_nodes == 0) {
209 		mc->fb_start = mc->vram_start;
210 		mc->fb_end = mc->vram_end;
211 	}
212 	dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
213 			mc->mc_vram_size >> 20, mc->vram_start,
214 			mc->vram_end, mc->real_vram_size >> 20);
215 }
216 
217 /** amdgpu_gmc_sysvm_location - place vram and gart in sysvm aperture
218  *
219  * @adev: amdgpu device structure holding all necessary information
220  * @mc: memory controller structure holding memory information
221  *
222  * This function is only used if use GART for FB translation. In such
223  * case, we use sysvm aperture (vmid0 page tables) for both vram
224  * and gart (aka system memory) access.
225  *
226  * GPUVM (and our organization of vmid0 page tables) require sysvm
227  * aperture to be placed at a location aligned with 8 times of native
228  * page size. For example, if vm_context0_cntl.page_table_block_size
229  * is 12, then native page size is 8G (2M*2^12), sysvm should start
230  * with a 64G aligned address. For simplicity, we just put sysvm at
231  * address 0. So vram start at address 0 and gart is right after vram.
232  */
233 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
234 {
235 	u64 hive_vram_start = 0;
236 	u64 hive_vram_end = mc->xgmi.node_segment_size * mc->xgmi.num_physical_nodes - 1;
237 	mc->vram_start = mc->xgmi.node_segment_size * mc->xgmi.physical_node_id;
238 	mc->vram_end = mc->vram_start + mc->xgmi.node_segment_size - 1;
239 	mc->gart_start = hive_vram_end + 1;
240 	mc->gart_end = mc->gart_start + mc->gart_size - 1;
241 	mc->fb_start = hive_vram_start;
242 	mc->fb_end = hive_vram_end;
243 	dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
244 			mc->mc_vram_size >> 20, mc->vram_start,
245 			mc->vram_end, mc->real_vram_size >> 20);
246 	dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
247 			mc->gart_size >> 20, mc->gart_start, mc->gart_end);
248 }
249 
250 /**
251  * amdgpu_gmc_gart_location - try to find GART location
252  *
253  * @adev: amdgpu device structure holding all necessary information
254  * @mc: memory controller structure holding memory information
255  *
256  * Function will place try to place GART before or after VRAM.
257  * If GART size is bigger than space left then we ajust GART size.
258  * Thus function will never fails.
259  */
260 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
261 {
262 	const uint64_t four_gb = 0x100000000ULL;
263 	u64 size_af, size_bf;
264 	/*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/
265 	u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1);
266 
267 	/* VCE doesn't like it when BOs cross a 4GB segment, so align
268 	 * the GART base on a 4GB boundary as well.
269 	 */
270 	size_bf = mc->fb_start;
271 	size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb);
272 
273 	if (mc->gart_size > max(size_bf, size_af)) {
274 		dev_warn(adev->dev, "limiting GART\n");
275 		mc->gart_size = max(size_bf, size_af);
276 	}
277 
278 	if ((size_bf >= mc->gart_size && size_bf < size_af) ||
279 	    (size_af < mc->gart_size))
280 		mc->gart_start = 0;
281 	else
282 		mc->gart_start = max_mc_address - mc->gart_size + 1;
283 
284 	mc->gart_start &= ~(four_gb - 1);
285 	mc->gart_end = mc->gart_start + mc->gart_size - 1;
286 	dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
287 			mc->gart_size >> 20, mc->gart_start, mc->gart_end);
288 }
289 
290 /**
291  * amdgpu_gmc_agp_location - try to find AGP location
292  * @adev: amdgpu device structure holding all necessary information
293  * @mc: memory controller structure holding memory information
294  *
295  * Function will place try to find a place for the AGP BAR in the MC address
296  * space.
297  *
298  * AGP BAR will be assigned the largest available hole in the address space.
299  * Should be called after VRAM and GART locations are setup.
300  */
301 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
302 {
303 	const uint64_t sixteen_gb = 1ULL << 34;
304 	const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1);
305 	u64 size_af, size_bf;
306 
307 	if (amdgpu_sriov_vf(adev)) {
308 		mc->agp_start = 0xffffffffffff;
309 		mc->agp_end = 0x0;
310 		mc->agp_size = 0;
311 
312 		return;
313 	}
314 
315 	if (mc->fb_start > mc->gart_start) {
316 		size_bf = (mc->fb_start & sixteen_gb_mask) -
317 			ALIGN(mc->gart_end + 1, sixteen_gb);
318 		size_af = mc->mc_mask + 1 - ALIGN(mc->fb_end + 1, sixteen_gb);
319 	} else {
320 		size_bf = mc->fb_start & sixteen_gb_mask;
321 		size_af = (mc->gart_start & sixteen_gb_mask) -
322 			ALIGN(mc->fb_end + 1, sixteen_gb);
323 	}
324 
325 	if (size_bf > size_af) {
326 		mc->agp_start = (mc->fb_start - size_bf) & sixteen_gb_mask;
327 		mc->agp_size = size_bf;
328 	} else {
329 		mc->agp_start = ALIGN(mc->fb_end + 1, sixteen_gb);
330 		mc->agp_size = size_af;
331 	}
332 
333 	mc->agp_end = mc->agp_start + mc->agp_size - 1;
334 	dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n",
335 			mc->agp_size >> 20, mc->agp_start, mc->agp_end);
336 }
337 
338 /**
339  * amdgpu_gmc_fault_key - get hask key from vm fault address and pasid
340  *
341  * @addr: 48 bit physical address, page aligned (36 significant bits)
342  * @pasid: 16 bit process address space identifier
343  */
344 static inline uint64_t amdgpu_gmc_fault_key(uint64_t addr, uint16_t pasid)
345 {
346 	return addr << 4 | pasid;
347 }
348 
349 /**
350  * amdgpu_gmc_filter_faults - filter VM faults
351  *
352  * @adev: amdgpu device structure
353  * @ih: interrupt ring that the fault received from
354  * @addr: address of the VM fault
355  * @pasid: PASID of the process causing the fault
356  * @timestamp: timestamp of the fault
357  *
358  * Returns:
359  * True if the fault was filtered and should not be processed further.
360  * False if the fault is a new one and needs to be handled.
361  */
362 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev,
363 			      struct amdgpu_ih_ring *ih, uint64_t addr,
364 			      uint16_t pasid, uint64_t timestamp)
365 {
366 	struct amdgpu_gmc *gmc = &adev->gmc;
367 	uint64_t stamp, key = amdgpu_gmc_fault_key(addr, pasid);
368 	struct amdgpu_gmc_fault *fault;
369 	uint32_t hash;
370 
371 	/* Stale retry fault if timestamp goes backward */
372 	if (amdgpu_ih_ts_after(timestamp, ih->processed_timestamp))
373 		return true;
374 
375 	/* If we don't have space left in the ring buffer return immediately */
376 	stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) -
377 		AMDGPU_GMC_FAULT_TIMEOUT;
378 	if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp)
379 		return true;
380 
381 	/* Try to find the fault in the hash */
382 	hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
383 	fault = &gmc->fault_ring[gmc->fault_hash[hash].idx];
384 	while (fault->timestamp >= stamp) {
385 		uint64_t tmp;
386 
387 		if (atomic64_read(&fault->key) == key)
388 			return true;
389 
390 		tmp = fault->timestamp;
391 		fault = &gmc->fault_ring[fault->next];
392 
393 		/* Check if the entry was reused */
394 		if (fault->timestamp >= tmp)
395 			break;
396 	}
397 
398 	/* Add the fault to the ring */
399 	fault = &gmc->fault_ring[gmc->last_fault];
400 	atomic64_set(&fault->key, key);
401 	fault->timestamp = timestamp;
402 
403 	/* And update the hash */
404 	fault->next = gmc->fault_hash[hash].idx;
405 	gmc->fault_hash[hash].idx = gmc->last_fault++;
406 	return false;
407 }
408 
409 /**
410  * amdgpu_gmc_filter_faults_remove - remove address from VM faults filter
411  *
412  * @adev: amdgpu device structure
413  * @addr: address of the VM fault
414  * @pasid: PASID of the process causing the fault
415  *
416  * Remove the address from fault filter, then future vm fault on this address
417  * will pass to retry fault handler to recover.
418  */
419 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr,
420 				     uint16_t pasid)
421 {
422 	struct amdgpu_gmc *gmc = &adev->gmc;
423 	uint64_t key = amdgpu_gmc_fault_key(addr, pasid);
424 	struct amdgpu_gmc_fault *fault;
425 	uint32_t hash;
426 	uint64_t tmp;
427 
428 	hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
429 	fault = &gmc->fault_ring[gmc->fault_hash[hash].idx];
430 	do {
431 		if (atomic64_cmpxchg(&fault->key, key, 0) == key)
432 			break;
433 
434 		tmp = fault->timestamp;
435 		fault = &gmc->fault_ring[fault->next];
436 	} while (fault->timestamp < tmp);
437 }
438 
439 int amdgpu_gmc_ras_early_init(struct amdgpu_device *adev)
440 {
441 	if (!adev->gmc.xgmi.connected_to_cpu) {
442 		adev->gmc.xgmi.ras = &xgmi_ras;
443 		amdgpu_ras_register_ras_block(adev, &adev->gmc.xgmi.ras->ras_block);
444 		adev->gmc.xgmi.ras_if = &adev->gmc.xgmi.ras->ras_block.ras_comm;
445 	}
446 
447 	return 0;
448 }
449 
450 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev)
451 {
452 	return 0;
453 }
454 
455 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev)
456 {
457 
458 }
459 
460 	/*
461 	 * The latest engine allocation on gfx9/10 is:
462 	 * Engine 2, 3: firmware
463 	 * Engine 0, 1, 4~16: amdgpu ring,
464 	 *                    subject to change when ring number changes
465 	 * Engine 17: Gart flushes
466 	 */
467 #define GFXHUB_FREE_VM_INV_ENGS_BITMAP		0x1FFF3
468 #define MMHUB_FREE_VM_INV_ENGS_BITMAP		0x1FFF3
469 
470 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev)
471 {
472 	struct amdgpu_ring *ring;
473 	unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] =
474 		{GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP,
475 		GFXHUB_FREE_VM_INV_ENGS_BITMAP};
476 	unsigned i;
477 	unsigned vmhub, inv_eng;
478 
479 	for (i = 0; i < adev->num_rings; ++i) {
480 		ring = adev->rings[i];
481 		vmhub = ring->funcs->vmhub;
482 
483 		if (ring == &adev->mes.ring)
484 			continue;
485 
486 		inv_eng = ffs(vm_inv_engs[vmhub]);
487 		if (!inv_eng) {
488 			dev_err(adev->dev, "no VM inv eng for ring %s\n",
489 				ring->name);
490 			return -EINVAL;
491 		}
492 
493 		ring->vm_inv_eng = inv_eng - 1;
494 		vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng);
495 
496 		dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n",
497 			 ring->name, ring->vm_inv_eng, ring->funcs->vmhub);
498 	}
499 
500 	return 0;
501 }
502 
503 /**
504  * amdgpu_gmc_tmz_set -- check and set if a device supports TMZ
505  * @adev: amdgpu_device pointer
506  *
507  * Check and set if an the device @adev supports Trusted Memory
508  * Zones (TMZ).
509  */
510 void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)
511 {
512 	switch (adev->asic_type) {
513 	case CHIP_RAVEN:
514 	case CHIP_RENOIR:
515 		if (amdgpu_tmz == 0) {
516 			adev->gmc.tmz_enabled = false;
517 			dev_info(adev->dev,
518 				 "Trusted Memory Zone (TMZ) feature disabled (cmd line)\n");
519 		} else {
520 			adev->gmc.tmz_enabled = true;
521 			dev_info(adev->dev,
522 				 "Trusted Memory Zone (TMZ) feature enabled\n");
523 		}
524 		break;
525 	case CHIP_NAVI10:
526 	case CHIP_NAVI14:
527 	case CHIP_NAVI12:
528 	case CHIP_VANGOGH:
529 	case CHIP_YELLOW_CARP:
530 	case CHIP_IP_DISCOVERY:
531 		/* Don't enable it by default yet.
532 		 */
533 		if (amdgpu_tmz < 1) {
534 			adev->gmc.tmz_enabled = false;
535 			dev_info(adev->dev,
536 				 "Trusted Memory Zone (TMZ) feature disabled as experimental (default)\n");
537 		} else {
538 			adev->gmc.tmz_enabled = true;
539 			dev_info(adev->dev,
540 				 "Trusted Memory Zone (TMZ) feature enabled as experimental (cmd line)\n");
541 		}
542 		break;
543 	default:
544 		adev->gmc.tmz_enabled = false;
545 		dev_info(adev->dev,
546 			 "Trusted Memory Zone (TMZ) feature not supported\n");
547 		break;
548 	}
549 }
550 
551 /**
552  * amdgpu_gmc_noretry_set -- set per asic noretry defaults
553  * @adev: amdgpu_device pointer
554  *
555  * Set a per asic default for the no-retry parameter.
556  *
557  */
558 void amdgpu_gmc_noretry_set(struct amdgpu_device *adev)
559 {
560 	struct amdgpu_gmc *gmc = &adev->gmc;
561 
562 	switch (adev->ip_versions[GC_HWIP][0]) {
563 	case IP_VERSION(9, 0, 1):
564 	case IP_VERSION(9, 3, 0):
565 	case IP_VERSION(9, 4, 0):
566 	case IP_VERSION(9, 4, 1):
567 	case IP_VERSION(9, 4, 2):
568 	case IP_VERSION(10, 3, 3):
569 	case IP_VERSION(10, 3, 4):
570 	case IP_VERSION(10, 3, 5):
571 	case IP_VERSION(10, 3, 6):
572 	case IP_VERSION(10, 3, 7):
573 		/*
574 		 * noretry = 0 will cause kfd page fault tests fail
575 		 * for some ASICs, so set default to 1 for these ASICs.
576 		 */
577 		if (amdgpu_noretry == -1)
578 			gmc->noretry = 1;
579 		else
580 			gmc->noretry = amdgpu_noretry;
581 		break;
582 	default:
583 		/* Raven currently has issues with noretry
584 		 * regardless of what we decide for other
585 		 * asics, we should leave raven with
586 		 * noretry = 0 until we root cause the
587 		 * issues.
588 		 *
589 		 * default this to 0 for now, but we may want
590 		 * to change this in the future for certain
591 		 * GPUs as it can increase performance in
592 		 * certain cases.
593 		 */
594 		if (amdgpu_noretry == -1)
595 			gmc->noretry = 0;
596 		else
597 			gmc->noretry = amdgpu_noretry;
598 		break;
599 	}
600 }
601 
602 void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,
603 				   bool enable)
604 {
605 	struct amdgpu_vmhub *hub;
606 	u32 tmp, reg, i;
607 
608 	hub = &adev->vmhub[hub_type];
609 	for (i = 0; i < 16; i++) {
610 		reg = hub->vm_context0_cntl + hub->ctx_distance * i;
611 
612 		tmp = (hub_type == AMDGPU_GFXHUB_0) ?
613 			RREG32_SOC15_IP(GC, reg) :
614 			RREG32_SOC15_IP(MMHUB, reg);
615 
616 		if (enable)
617 			tmp |= hub->vm_cntx_cntl_vm_fault;
618 		else
619 			tmp &= ~hub->vm_cntx_cntl_vm_fault;
620 
621 		(hub_type == AMDGPU_GFXHUB_0) ?
622 			WREG32_SOC15_IP(GC, reg, tmp) :
623 			WREG32_SOC15_IP(MMHUB, reg, tmp);
624 	}
625 }
626 
627 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev)
628 {
629 	unsigned size;
630 
631 	/*
632 	 * Some ASICs need to reserve a region of video memory to avoid access
633 	 * from driver
634 	 */
635 	adev->mman.stolen_reserved_offset = 0;
636 	adev->mman.stolen_reserved_size = 0;
637 
638 	/*
639 	 * TODO:
640 	 * Currently there is a bug where some memory client outside
641 	 * of the driver writes to first 8M of VRAM on S3 resume,
642 	 * this overrides GART which by default gets placed in first 8M and
643 	 * causes VM_FAULTS once GTT is accessed.
644 	 * Keep the stolen memory reservation until the while this is not solved.
645 	 */
646 	switch (adev->asic_type) {
647 	case CHIP_VEGA10:
648 		adev->mman.keep_stolen_vga_memory = true;
649 		/*
650 		 * VEGA10 SRIOV VF needs some firmware reserved area.
651 		 */
652 		if (amdgpu_sriov_vf(adev)) {
653 			adev->mman.stolen_reserved_offset = 0x100000;
654 			adev->mman.stolen_reserved_size = 0x600000;
655 		}
656 		break;
657 	case CHIP_RAVEN:
658 	case CHIP_RENOIR:
659 		adev->mman.keep_stolen_vga_memory = true;
660 		break;
661 	case CHIP_YELLOW_CARP:
662 		if (amdgpu_discovery == 0) {
663 			adev->mman.stolen_reserved_offset = 0x1ffb0000;
664 			adev->mman.stolen_reserved_size = 64 * PAGE_SIZE;
665 		}
666 		break;
667 	default:
668 		adev->mman.keep_stolen_vga_memory = false;
669 		break;
670 	}
671 
672 	if (amdgpu_sriov_vf(adev) ||
673 	    !amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_DCE)) {
674 		size = 0;
675 	} else {
676 		size = amdgpu_gmc_get_vbios_fb_size(adev);
677 
678 		if (adev->mman.keep_stolen_vga_memory)
679 			size = max(size, (unsigned)AMDGPU_VBIOS_VGA_ALLOCATION);
680 	}
681 
682 	/* set to 0 if the pre-OS buffer uses up most of vram */
683 	if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
684 		size = 0;
685 
686 	if (size > AMDGPU_VBIOS_VGA_ALLOCATION) {
687 		adev->mman.stolen_vga_size = AMDGPU_VBIOS_VGA_ALLOCATION;
688 		adev->mman.stolen_extended_size = size - adev->mman.stolen_vga_size;
689 	} else {
690 		adev->mman.stolen_vga_size = size;
691 		adev->mman.stolen_extended_size = 0;
692 	}
693 }
694 
695 /**
696  * amdgpu_gmc_init_pdb0 - initialize PDB0
697  *
698  * @adev: amdgpu_device pointer
699  *
700  * This function is only used when GART page table is used
701  * for FB address translatioin. In such a case, we construct
702  * a 2-level system VM page table: PDB0->PTB, to cover both
703  * VRAM of the hive and system memory.
704  *
705  * PDB0 is static, initialized once on driver initialization.
706  * The first n entries of PDB0 are used as PTE by setting
707  * P bit to 1, pointing to VRAM. The n+1'th entry points
708  * to a big PTB covering system memory.
709  *
710  */
711 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev)
712 {
713 	int i;
714 	uint64_t flags = adev->gart.gart_pte_flags; //TODO it is UC. explore NC/RW?
715 	/* Each PDE0 (used as PTE) covers (2^vmid0_page_table_block_size)*2M
716 	 */
717 	u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes;
718 	u64 pde0_page_size = (1ULL<<adev->gmc.vmid0_page_table_block_size)<<21;
719 	u64 vram_addr = adev->vm_manager.vram_base_offset -
720 		adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
721 	u64 vram_end = vram_addr + vram_size;
722 	u64 gart_ptb_gpu_pa = amdgpu_gmc_vram_pa(adev, adev->gart.bo);
723 	int idx;
724 
725 	if (!drm_dev_enter(adev_to_drm(adev), &idx))
726 		return;
727 
728 	flags |= AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE;
729 	flags |= AMDGPU_PTE_WRITEABLE;
730 	flags |= AMDGPU_PTE_SNOOPED;
731 	flags |= AMDGPU_PTE_FRAG((adev->gmc.vmid0_page_table_block_size + 9*1));
732 	flags |= AMDGPU_PDE_PTE;
733 
734 	/* The first n PDE0 entries are used as PTE,
735 	 * pointing to vram
736 	 */
737 	for (i = 0; vram_addr < vram_end; i++, vram_addr += pde0_page_size)
738 		amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, vram_addr, flags);
739 
740 	/* The n+1'th PDE0 entry points to a huge
741 	 * PTB who has more than 512 entries each
742 	 * pointing to a 4K system page
743 	 */
744 	flags = AMDGPU_PTE_VALID;
745 	flags |= AMDGPU_PDE_BFS(0) | AMDGPU_PTE_SNOOPED;
746 	/* Requires gart_ptb_gpu_pa to be 4K aligned */
747 	amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags);
748 	drm_dev_exit(idx);
749 }
750 
751 /**
752  * amdgpu_gmc_vram_mc2pa - calculate vram buffer's physical address from MC
753  * address
754  *
755  * @adev: amdgpu_device pointer
756  * @mc_addr: MC address of buffer
757  */
758 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr)
759 {
760 	return mc_addr - adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
761 }
762 
763 /**
764  * amdgpu_gmc_vram_pa - calculate vram buffer object's physical address from
765  * GPU's view
766  *
767  * @adev: amdgpu_device pointer
768  * @bo: amdgpu buffer object
769  */
770 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo)
771 {
772 	return amdgpu_gmc_vram_mc2pa(adev, amdgpu_bo_gpu_offset(bo));
773 }
774 
775 /**
776  * amdgpu_gmc_vram_cpu_pa - calculate vram buffer object's physical address
777  * from CPU's view
778  *
779  * @adev: amdgpu_device pointer
780  * @bo: amdgpu buffer object
781  */
782 uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo)
783 {
784 	return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.aper_base;
785 }
786 
787 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev)
788 {
789 	struct amdgpu_bo *vram_bo = NULL;
790 	uint64_t vram_gpu = 0;
791 	void *vram_ptr = NULL;
792 
793 	int ret, size = 0x100000;
794 	uint8_t cptr[10];
795 
796 	ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
797 				AMDGPU_GEM_DOMAIN_VRAM,
798 				&vram_bo,
799 				&vram_gpu,
800 				&vram_ptr);
801 	if (ret)
802 		return ret;
803 
804 	memset(vram_ptr, 0x86, size);
805 	memset(cptr, 0x86, 10);
806 
807 	/**
808 	 * Check the start, the mid, and the end of the memory if the content of
809 	 * each byte is the pattern "0x86". If yes, we suppose the vram bo is
810 	 * workable.
811 	 *
812 	 * Note: If check the each byte of whole 1M bo, it will cost too many
813 	 * seconds, so here, we just pick up three parts for emulation.
814 	 */
815 	ret = memcmp(vram_ptr, cptr, 10);
816 	if (ret)
817 		return ret;
818 
819 	ret = memcmp(vram_ptr + (size / 2), cptr, 10);
820 	if (ret)
821 		return ret;
822 
823 	ret = memcmp(vram_ptr + size - 10, cptr, 10);
824 	if (ret)
825 		return ret;
826 
827 	amdgpu_bo_free_kernel(&vram_bo, &vram_gpu,
828 			&vram_ptr);
829 
830 	return 0;
831 }
832