1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef AMDGPU_DOORBELL_H 25 #define AMDGPU_DOORBELL_H 26 27 /* 28 * GPU doorbell structures, functions & helpers 29 */ 30 struct amdgpu_doorbell { 31 /* doorbell mmio */ 32 resource_size_t base; 33 resource_size_t size; 34 u32 __iomem *ptr; 35 36 /* Number of doorbells reserved for amdgpu kernel driver */ 37 u32 num_kernel_doorbells; 38 }; 39 40 /* Reserved doorbells for amdgpu (including multimedia). 41 * KFD can use all the rest in the 2M doorbell bar. 42 * For asic before vega10, doorbell is 32-bit, so the 43 * index/offset is in dword. For vega10 and after, doorbell 44 * can be 64-bit, so the index defined is in qword. 45 */ 46 struct amdgpu_doorbell_index { 47 uint32_t kiq; 48 uint32_t mec_ring0; 49 uint32_t mec_ring1; 50 uint32_t mec_ring2; 51 uint32_t mec_ring3; 52 uint32_t mec_ring4; 53 uint32_t mec_ring5; 54 uint32_t mec_ring6; 55 uint32_t mec_ring7; 56 uint32_t userqueue_start; 57 uint32_t userqueue_end; 58 uint32_t gfx_ring0; 59 uint32_t gfx_ring1; 60 uint32_t gfx_userqueue_start; 61 uint32_t gfx_userqueue_end; 62 uint32_t sdma_engine[16]; 63 uint32_t mes_ring0; 64 uint32_t mes_ring1; 65 uint32_t ih; 66 union { 67 struct { 68 uint32_t vcn_ring0_1; 69 uint32_t vcn_ring2_3; 70 uint32_t vcn_ring4_5; 71 uint32_t vcn_ring6_7; 72 } vcn; 73 struct { 74 uint32_t uvd_ring0_1; 75 uint32_t uvd_ring2_3; 76 uint32_t uvd_ring4_5; 77 uint32_t uvd_ring6_7; 78 uint32_t vce_ring0_1; 79 uint32_t vce_ring2_3; 80 uint32_t vce_ring4_5; 81 uint32_t vce_ring6_7; 82 } uvd_vce; 83 }; 84 uint32_t first_non_cp; 85 uint32_t last_non_cp; 86 uint32_t max_assignment; 87 /* Per engine SDMA doorbell size in dword */ 88 uint32_t sdma_doorbell_range; 89 /* Per xcc doorbell size for KIQ/KCQ */ 90 uint32_t xcc_doorbell_range; 91 }; 92 93 enum AMDGPU_DOORBELL_ASSIGNMENT { 94 AMDGPU_DOORBELL_KIQ = 0x000, 95 AMDGPU_DOORBELL_HIQ = 0x001, 96 AMDGPU_DOORBELL_DIQ = 0x002, 97 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 98 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 99 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 100 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 101 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 102 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 103 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 104 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 105 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 106 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 107 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 108 AMDGPU_DOORBELL_IH = 0x1E8, 109 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 110 AMDGPU_DOORBELL_INVALID = 0xFFFF 111 }; 112 113 enum AMDGPU_VEGA20_DOORBELL_ASSIGNMENT { 114 115 /* Compute + GFX: 0~255 */ 116 AMDGPU_VEGA20_DOORBELL_KIQ = 0x000, 117 AMDGPU_VEGA20_DOORBELL_HIQ = 0x001, 118 AMDGPU_VEGA20_DOORBELL_DIQ = 0x002, 119 AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 0x003, 120 AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 0x004, 121 AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 0x005, 122 AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 0x006, 123 AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 0x007, 124 AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008, 125 AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009, 126 AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A, 127 AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B, 128 AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A, 129 AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B, 130 /* SDMA:256~335*/ 131 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 0x100, 132 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 0x10A, 133 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 0x114, 134 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 0x11E, 135 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 0x128, 136 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 0x132, 137 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 0x13C, 138 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 0x146, 139 /* IH: 376~391 */ 140 AMDGPU_VEGA20_DOORBELL_IH = 0x178, 141 /* MMSCH: 392~407 142 * overlap the doorbell assignment with VCN as they are mutually exclusive 143 * VCN engine's doorbell is 32 bit and two VCN ring share one QWORD 144 */ 145 AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* VNC0 */ 146 AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189, 147 AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A, 148 AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B, 149 150 AMDGPU_VEGA20_DOORBELL64_VCN8_9 = 0x18C, /* VNC1 */ 151 AMDGPU_VEGA20_DOORBELL64_VCNa_b = 0x18D, 152 AMDGPU_VEGA20_DOORBELL64_VCNc_d = 0x18E, 153 AMDGPU_VEGA20_DOORBELL64_VCNe_f = 0x18F, 154 155 AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188, 156 AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189, 157 AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A, 158 AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 0x18B, 159 160 AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 0x18C, 161 AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D, 162 AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E, 163 AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F, 164 165 AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0, 166 AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7, 167 168 /* kiq/kcq from second XCD. Max 8 XCDs */ 169 AMDGPU_VEGA20_DOORBELL_XCC1_KIQ_START = 0x190, 170 /* 8 compute rings per GC. Max to 0x1CE */ 171 AMDGPU_VEGA20_DOORBELL_XCC1_MEC_RING0_START = 0x197, 172 173 /* AID1 SDMA: 0x1D0 ~ 0x1F7 */ 174 AMDGPU_VEGA20_DOORBELL_AID1_sDMA_START = 0x1D0, 175 176 AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x1F7, 177 AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF 178 }; 179 180 enum AMDGPU_NAVI10_DOORBELL_ASSIGNMENT { 181 182 /* Compute + GFX: 0~255 */ 183 AMDGPU_NAVI10_DOORBELL_KIQ = 0x000, 184 AMDGPU_NAVI10_DOORBELL_HIQ = 0x001, 185 AMDGPU_NAVI10_DOORBELL_DIQ = 0x002, 186 AMDGPU_NAVI10_DOORBELL_MEC_RING0 = 0x003, 187 AMDGPU_NAVI10_DOORBELL_MEC_RING1 = 0x004, 188 AMDGPU_NAVI10_DOORBELL_MEC_RING2 = 0x005, 189 AMDGPU_NAVI10_DOORBELL_MEC_RING3 = 0x006, 190 AMDGPU_NAVI10_DOORBELL_MEC_RING4 = 0x007, 191 AMDGPU_NAVI10_DOORBELL_MEC_RING5 = 0x008, 192 AMDGPU_NAVI10_DOORBELL_MEC_RING6 = 0x009, 193 AMDGPU_NAVI10_DOORBELL_MEC_RING7 = 0x00A, 194 AMDGPU_NAVI10_DOORBELL_MES_RING0 = 0x00B, 195 AMDGPU_NAVI10_DOORBELL_MES_RING1 = 0x00C, 196 AMDGPU_NAVI10_DOORBELL_USERQUEUE_START = 0x00D, 197 AMDGPU_NAVI10_DOORBELL_USERQUEUE_END = 0x08A, 198 AMDGPU_NAVI10_DOORBELL_GFX_RING0 = 0x08B, 199 AMDGPU_NAVI10_DOORBELL_GFX_RING1 = 0x08C, 200 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START = 0x08D, 201 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END = 0x0FF, 202 203 /* SDMA:256~335*/ 204 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 = 0x100, 205 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1 = 0x10A, 206 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2 = 0x114, 207 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3 = 0x11E, 208 /* IH: 376~391 */ 209 AMDGPU_NAVI10_DOORBELL_IH = 0x178, 210 /* MMSCH: 392~407 211 * overlap the doorbell assignment with VCN as they are mutually exclusive 212 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 213 */ 214 AMDGPU_NAVI10_DOORBELL64_VCN0_1 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 215 AMDGPU_NAVI10_DOORBELL64_VCN2_3 = 0x189, 216 AMDGPU_NAVI10_DOORBELL64_VCN4_5 = 0x18A, 217 AMDGPU_NAVI10_DOORBELL64_VCN6_7 = 0x18B, 218 219 AMDGPU_NAVI10_DOORBELL64_VCN8_9 = 0x18C, 220 AMDGPU_NAVI10_DOORBELL64_VCNa_b = 0x18D, 221 AMDGPU_NAVI10_DOORBELL64_VCNc_d = 0x18E, 222 AMDGPU_NAVI10_DOORBELL64_VCNe_f = 0x18F, 223 224 AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0, 225 AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP = AMDGPU_NAVI10_DOORBELL64_VCNe_f, 226 227 AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT = 0x18F, 228 AMDGPU_NAVI10_DOORBELL_INVALID = 0xFFFF 229 }; 230 231 /* 232 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 233 */ 234 enum AMDGPU_DOORBELL64_ASSIGNMENT { 235 /* 236 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 237 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 238 * Compute related doorbells are allocated from 0x00 to 0x8a 239 */ 240 241 242 /* kernel scheduling */ 243 AMDGPU_DOORBELL64_KIQ = 0x00, 244 245 /* HSA interface queue and debug queue */ 246 AMDGPU_DOORBELL64_HIQ = 0x01, 247 AMDGPU_DOORBELL64_DIQ = 0x02, 248 249 /* Compute engines */ 250 AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 251 AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 252 AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 253 AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 254 AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 255 AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 256 AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 257 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 258 259 /* User queue doorbell range (128 doorbells) */ 260 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 261 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 262 263 /* Graphics engine */ 264 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 265 266 /* 267 * Other graphics doorbells can be allocated here: from 0x8c to 0xdf 268 * Graphics voltage island aperture 1 269 * default non-graphics QWORD index is 0xe0 - 0xFF inclusive 270 */ 271 272 /* For vega10 sriov, the sdma doorbell must be fixed as follow 273 * to keep the same setting with host driver, or it will 274 * happen conflicts 275 */ 276 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, 277 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 278 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, 279 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 280 281 /* Interrupt handler */ 282 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 283 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 284 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 285 286 /* VCN engine use 32 bits doorbell */ 287 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 288 AMDGPU_DOORBELL64_VCN2_3 = 0xF9, 289 AMDGPU_DOORBELL64_VCN4_5 = 0xFA, 290 AMDGPU_DOORBELL64_VCN6_7 = 0xFB, 291 292 /* overlap the doorbell assignment with VCN as they are mutually exclusive 293 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 294 */ 295 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, 296 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, 297 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, 298 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, 299 300 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, 301 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, 302 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, 303 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, 304 305 AMDGPU_DOORBELL64_FIRST_NON_CP = AMDGPU_DOORBELL64_sDMA_ENGINE0, 306 AMDGPU_DOORBELL64_LAST_NON_CP = AMDGPU_DOORBELL64_VCE_RING6_7, 307 308 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 309 AMDGPU_DOORBELL64_INVALID = 0xFFFF 310 }; 311 312 enum AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1 { 313 314 /* XCC0: 0x00 ~20, XCC1: 20 ~ 2F ... */ 315 316 /* KIQ/HIQ/DIQ */ 317 AMDGPU_DOORBELL_LAYOUT1_KIQ_START = 0x000, 318 AMDGPU_DOORBELL_LAYOUT1_HIQ = 0x001, 319 AMDGPU_DOORBELL_LAYOUT1_DIQ = 0x002, 320 /* Compute: 0x08 ~ 0x20 */ 321 AMDGPU_DOORBELL_LAYOUT1_MEC_RING_START = 0x008, 322 AMDGPU_DOORBELL_LAYOUT1_MEC_RING_END = 0x00F, 323 AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_START = 0x010, 324 AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_END = 0x01F, 325 AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE = 0x020, 326 327 /* SDMA: 0x100 ~ 0x19F */ 328 AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START = 0x100, 329 AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_END = 0x19F, 330 /* IH: 0x1A0 ~ 0x1AF */ 331 AMDGPU_DOORBELL_LAYOUT1_IH = 0x1A0, 332 /* VCN: 0x1B0 ~ 0x1D4 */ 333 AMDGPU_DOORBELL_LAYOUT1_VCN_START = 0x1B0, 334 AMDGPU_DOORBELL_LAYOUT1_VCN_END = 0x1D4, 335 336 AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP = AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START, 337 AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP = AMDGPU_DOORBELL_LAYOUT1_VCN_END, 338 339 AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT = 0x1D4, 340 AMDGPU_DOORBELL_LAYOUT1_INVALID = 0xFFFF 341 }; 342 343 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 344 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 345 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 346 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 347 348 /* 349 * GPU doorbell aperture helpers function. 350 */ 351 int amdgpu_doorbell_init(struct amdgpu_device *adev); 352 void amdgpu_doorbell_fini(struct amdgpu_device *adev); 353 354 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 355 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 356 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 357 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 358 359 #endif 360