1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: monk liu <monk.liu@amd.com> 23 */ 24 25 #include <drm/drm_auth.h> 26 #include <drm/drm_drv.h> 27 #include "amdgpu.h" 28 #include "amdgpu_sched.h" 29 #include "amdgpu_ras.h" 30 #include <linux/nospec.h> 31 32 #define to_amdgpu_ctx_entity(e) \ 33 container_of((e), struct amdgpu_ctx_entity, entity) 34 35 const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM] = { 36 [AMDGPU_HW_IP_GFX] = 1, 37 [AMDGPU_HW_IP_COMPUTE] = 4, 38 [AMDGPU_HW_IP_DMA] = 2, 39 [AMDGPU_HW_IP_UVD] = 1, 40 [AMDGPU_HW_IP_VCE] = 1, 41 [AMDGPU_HW_IP_UVD_ENC] = 1, 42 [AMDGPU_HW_IP_VCN_DEC] = 1, 43 [AMDGPU_HW_IP_VCN_ENC] = 1, 44 [AMDGPU_HW_IP_VCN_JPEG] = 1, 45 }; 46 47 bool amdgpu_ctx_priority_is_valid(int32_t ctx_prio) 48 { 49 switch (ctx_prio) { 50 case AMDGPU_CTX_PRIORITY_UNSET: 51 case AMDGPU_CTX_PRIORITY_VERY_LOW: 52 case AMDGPU_CTX_PRIORITY_LOW: 53 case AMDGPU_CTX_PRIORITY_NORMAL: 54 case AMDGPU_CTX_PRIORITY_HIGH: 55 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 56 return true; 57 default: 58 return false; 59 } 60 } 61 62 static enum drm_sched_priority 63 amdgpu_ctx_to_drm_sched_prio(int32_t ctx_prio) 64 { 65 switch (ctx_prio) { 66 case AMDGPU_CTX_PRIORITY_UNSET: 67 return DRM_SCHED_PRIORITY_UNSET; 68 69 case AMDGPU_CTX_PRIORITY_VERY_LOW: 70 return DRM_SCHED_PRIORITY_MIN; 71 72 case AMDGPU_CTX_PRIORITY_LOW: 73 return DRM_SCHED_PRIORITY_MIN; 74 75 case AMDGPU_CTX_PRIORITY_NORMAL: 76 return DRM_SCHED_PRIORITY_NORMAL; 77 78 case AMDGPU_CTX_PRIORITY_HIGH: 79 return DRM_SCHED_PRIORITY_HIGH; 80 81 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 82 return DRM_SCHED_PRIORITY_HIGH; 83 84 /* This should not happen as we sanitized userspace provided priority 85 * already, WARN if this happens. 86 */ 87 default: 88 WARN(1, "Invalid context priority %d\n", ctx_prio); 89 return DRM_SCHED_PRIORITY_NORMAL; 90 } 91 92 } 93 94 static int amdgpu_ctx_priority_permit(struct drm_file *filp, 95 int32_t priority) 96 { 97 if (!amdgpu_ctx_priority_is_valid(priority)) 98 return -EINVAL; 99 100 /* NORMAL and below are accessible by everyone */ 101 if (priority <= AMDGPU_CTX_PRIORITY_NORMAL) 102 return 0; 103 104 if (capable(CAP_SYS_NICE)) 105 return 0; 106 107 if (drm_is_current_master(filp)) 108 return 0; 109 110 return -EACCES; 111 } 112 113 static enum amdgpu_gfx_pipe_priority amdgpu_ctx_prio_to_gfx_pipe_prio(int32_t prio) 114 { 115 switch (prio) { 116 case AMDGPU_CTX_PRIORITY_HIGH: 117 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 118 return AMDGPU_GFX_PIPE_PRIO_HIGH; 119 default: 120 return AMDGPU_GFX_PIPE_PRIO_NORMAL; 121 } 122 } 123 124 static enum amdgpu_ring_priority_level amdgpu_ctx_sched_prio_to_ring_prio(int32_t prio) 125 { 126 switch (prio) { 127 case AMDGPU_CTX_PRIORITY_HIGH: 128 return AMDGPU_RING_PRIO_1; 129 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 130 return AMDGPU_RING_PRIO_2; 131 default: 132 return AMDGPU_RING_PRIO_0; 133 } 134 } 135 136 static unsigned int amdgpu_ctx_get_hw_prio(struct amdgpu_ctx *ctx, u32 hw_ip) 137 { 138 struct amdgpu_device *adev = ctx->mgr->adev; 139 unsigned int hw_prio; 140 int32_t ctx_prio; 141 142 ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? 143 ctx->init_priority : ctx->override_priority; 144 145 switch (hw_ip) { 146 case AMDGPU_HW_IP_GFX: 147 case AMDGPU_HW_IP_COMPUTE: 148 hw_prio = amdgpu_ctx_prio_to_gfx_pipe_prio(ctx_prio); 149 break; 150 case AMDGPU_HW_IP_VCE: 151 case AMDGPU_HW_IP_VCN_ENC: 152 hw_prio = amdgpu_ctx_sched_prio_to_ring_prio(ctx_prio); 153 break; 154 default: 155 hw_prio = AMDGPU_RING_PRIO_DEFAULT; 156 break; 157 } 158 159 hw_ip = array_index_nospec(hw_ip, AMDGPU_HW_IP_NUM); 160 if (adev->gpu_sched[hw_ip][hw_prio].num_scheds == 0) 161 hw_prio = AMDGPU_RING_PRIO_DEFAULT; 162 163 return hw_prio; 164 } 165 166 /* Calculate the time spend on the hw */ 167 static ktime_t amdgpu_ctx_fence_time(struct dma_fence *fence) 168 { 169 struct drm_sched_fence *s_fence; 170 171 if (!fence) 172 return ns_to_ktime(0); 173 174 /* When the fence is not even scheduled it can't have spend time */ 175 s_fence = to_drm_sched_fence(fence); 176 if (!test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &s_fence->scheduled.flags)) 177 return ns_to_ktime(0); 178 179 /* When it is still running account how much already spend */ 180 if (!test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &s_fence->finished.flags)) 181 return ktime_sub(ktime_get(), s_fence->scheduled.timestamp); 182 183 return ktime_sub(s_fence->finished.timestamp, 184 s_fence->scheduled.timestamp); 185 } 186 187 static ktime_t amdgpu_ctx_entity_time(struct amdgpu_ctx *ctx, 188 struct amdgpu_ctx_entity *centity) 189 { 190 ktime_t res = ns_to_ktime(0); 191 uint32_t i; 192 193 spin_lock(&ctx->ring_lock); 194 for (i = 0; i < amdgpu_sched_jobs; i++) { 195 res = ktime_add(res, amdgpu_ctx_fence_time(centity->fences[i])); 196 } 197 spin_unlock(&ctx->ring_lock); 198 return res; 199 } 200 201 static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, 202 const u32 ring) 203 { 204 struct drm_gpu_scheduler **scheds = NULL, *sched = NULL; 205 struct amdgpu_device *adev = ctx->mgr->adev; 206 struct amdgpu_ctx_entity *entity; 207 enum drm_sched_priority drm_prio; 208 unsigned int hw_prio, num_scheds; 209 int32_t ctx_prio; 210 int r; 211 212 entity = kzalloc(struct_size(entity, fences, amdgpu_sched_jobs), 213 GFP_KERNEL); 214 if (!entity) 215 return -ENOMEM; 216 217 ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? 218 ctx->init_priority : ctx->override_priority; 219 entity->hw_ip = hw_ip; 220 entity->sequence = 1; 221 hw_prio = amdgpu_ctx_get_hw_prio(ctx, hw_ip); 222 drm_prio = amdgpu_ctx_to_drm_sched_prio(ctx_prio); 223 224 hw_ip = array_index_nospec(hw_ip, AMDGPU_HW_IP_NUM); 225 226 if (!(adev)->xcp_mgr) { 227 scheds = adev->gpu_sched[hw_ip][hw_prio].sched; 228 num_scheds = adev->gpu_sched[hw_ip][hw_prio].num_scheds; 229 } else { 230 struct amdgpu_fpriv *fpriv; 231 232 fpriv = container_of(ctx->ctx_mgr, struct amdgpu_fpriv, ctx_mgr); 233 r = amdgpu_xcp_select_scheds(adev, hw_ip, hw_prio, fpriv, 234 &num_scheds, &scheds); 235 if (r) 236 goto cleanup_entity; 237 } 238 239 /* disable load balance if the hw engine retains context among dependent jobs */ 240 if (hw_ip == AMDGPU_HW_IP_VCN_ENC || 241 hw_ip == AMDGPU_HW_IP_VCN_DEC || 242 hw_ip == AMDGPU_HW_IP_UVD_ENC || 243 hw_ip == AMDGPU_HW_IP_UVD) { 244 sched = drm_sched_pick_best(scheds, num_scheds); 245 scheds = &sched; 246 num_scheds = 1; 247 } 248 249 r = drm_sched_entity_init(&entity->entity, drm_prio, scheds, num_scheds, 250 &ctx->guilty); 251 if (r) 252 goto error_free_entity; 253 254 /* It's not an error if we fail to install the new entity */ 255 if (cmpxchg(&ctx->entities[hw_ip][ring], NULL, entity)) 256 goto cleanup_entity; 257 258 return 0; 259 260 cleanup_entity: 261 drm_sched_entity_fini(&entity->entity); 262 263 error_free_entity: 264 kfree(entity); 265 266 return r; 267 } 268 269 static ktime_t amdgpu_ctx_fini_entity(struct amdgpu_ctx_entity *entity) 270 { 271 ktime_t res = ns_to_ktime(0); 272 int i; 273 274 if (!entity) 275 return res; 276 277 for (i = 0; i < amdgpu_sched_jobs; ++i) { 278 res = ktime_add(res, amdgpu_ctx_fence_time(entity->fences[i])); 279 dma_fence_put(entity->fences[i]); 280 } 281 282 kfree(entity); 283 return res; 284 } 285 286 static int amdgpu_ctx_get_stable_pstate(struct amdgpu_ctx *ctx, 287 u32 *stable_pstate) 288 { 289 struct amdgpu_device *adev = ctx->mgr->adev; 290 enum amd_dpm_forced_level current_level; 291 292 current_level = amdgpu_dpm_get_performance_level(adev); 293 294 switch (current_level) { 295 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 296 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_STANDARD; 297 break; 298 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 299 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK; 300 break; 301 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 302 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK; 303 break; 304 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 305 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_PEAK; 306 break; 307 default: 308 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_NONE; 309 break; 310 } 311 return 0; 312 } 313 314 static int amdgpu_ctx_init(struct amdgpu_ctx_mgr *mgr, int32_t priority, 315 struct drm_file *filp, struct amdgpu_ctx *ctx) 316 { 317 struct amdgpu_fpriv *fpriv = filp->driver_priv; 318 u32 current_stable_pstate; 319 int r; 320 321 r = amdgpu_ctx_priority_permit(filp, priority); 322 if (r) 323 return r; 324 325 memset(ctx, 0, sizeof(*ctx)); 326 327 kref_init(&ctx->refcount); 328 ctx->mgr = mgr; 329 spin_lock_init(&ctx->ring_lock); 330 331 ctx->reset_counter = atomic_read(&mgr->adev->gpu_reset_counter); 332 ctx->reset_counter_query = ctx->reset_counter; 333 ctx->vram_lost_counter = atomic_read(&mgr->adev->vram_lost_counter); 334 ctx->init_priority = priority; 335 ctx->override_priority = AMDGPU_CTX_PRIORITY_UNSET; 336 337 r = amdgpu_ctx_get_stable_pstate(ctx, ¤t_stable_pstate); 338 if (r) 339 return r; 340 341 if (mgr->adev->pm.stable_pstate_ctx) 342 ctx->stable_pstate = mgr->adev->pm.stable_pstate_ctx->stable_pstate; 343 else 344 ctx->stable_pstate = current_stable_pstate; 345 346 ctx->ctx_mgr = &(fpriv->ctx_mgr); 347 return 0; 348 } 349 350 static int amdgpu_ctx_set_stable_pstate(struct amdgpu_ctx *ctx, 351 u32 stable_pstate) 352 { 353 struct amdgpu_device *adev = ctx->mgr->adev; 354 enum amd_dpm_forced_level level; 355 u32 current_stable_pstate; 356 int r; 357 358 mutex_lock(&adev->pm.stable_pstate_ctx_lock); 359 if (adev->pm.stable_pstate_ctx && adev->pm.stable_pstate_ctx != ctx) { 360 r = -EBUSY; 361 goto done; 362 } 363 364 r = amdgpu_ctx_get_stable_pstate(ctx, ¤t_stable_pstate); 365 if (r || (stable_pstate == current_stable_pstate)) 366 goto done; 367 368 switch (stable_pstate) { 369 case AMDGPU_CTX_STABLE_PSTATE_NONE: 370 level = AMD_DPM_FORCED_LEVEL_AUTO; 371 break; 372 case AMDGPU_CTX_STABLE_PSTATE_STANDARD: 373 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD; 374 break; 375 case AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK: 376 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK; 377 break; 378 case AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK: 379 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK; 380 break; 381 case AMDGPU_CTX_STABLE_PSTATE_PEAK: 382 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 383 break; 384 default: 385 r = -EINVAL; 386 goto done; 387 } 388 389 r = amdgpu_dpm_force_performance_level(adev, level); 390 391 if (level == AMD_DPM_FORCED_LEVEL_AUTO) 392 adev->pm.stable_pstate_ctx = NULL; 393 else 394 adev->pm.stable_pstate_ctx = ctx; 395 done: 396 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 397 398 return r; 399 } 400 401 static void amdgpu_ctx_fini(struct kref *ref) 402 { 403 struct amdgpu_ctx *ctx = container_of(ref, struct amdgpu_ctx, refcount); 404 struct amdgpu_ctx_mgr *mgr = ctx->mgr; 405 struct amdgpu_device *adev = mgr->adev; 406 unsigned i, j, idx; 407 408 if (!adev) 409 return; 410 411 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 412 for (j = 0; j < AMDGPU_MAX_ENTITY_NUM; ++j) { 413 ktime_t spend; 414 415 spend = amdgpu_ctx_fini_entity(ctx->entities[i][j]); 416 atomic64_add(ktime_to_ns(spend), &mgr->time_spend[i]); 417 } 418 } 419 420 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 421 amdgpu_ctx_set_stable_pstate(ctx, ctx->stable_pstate); 422 drm_dev_exit(idx); 423 } 424 425 kfree(ctx); 426 } 427 428 int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance, 429 u32 ring, struct drm_sched_entity **entity) 430 { 431 int r; 432 433 if (hw_ip >= AMDGPU_HW_IP_NUM) { 434 DRM_ERROR("unknown HW IP type: %d\n", hw_ip); 435 return -EINVAL; 436 } 437 438 /* Right now all IPs have only one instance - multiple rings. */ 439 if (instance != 0) { 440 DRM_DEBUG("invalid ip instance: %d\n", instance); 441 return -EINVAL; 442 } 443 444 if (ring >= amdgpu_ctx_num_entities[hw_ip]) { 445 DRM_DEBUG("invalid ring: %d %d\n", hw_ip, ring); 446 return -EINVAL; 447 } 448 449 if (ctx->entities[hw_ip][ring] == NULL) { 450 r = amdgpu_ctx_init_entity(ctx, hw_ip, ring); 451 if (r) 452 return r; 453 } 454 455 *entity = &ctx->entities[hw_ip][ring]->entity; 456 return 0; 457 } 458 459 static int amdgpu_ctx_alloc(struct amdgpu_device *adev, 460 struct amdgpu_fpriv *fpriv, 461 struct drm_file *filp, 462 int32_t priority, 463 uint32_t *id) 464 { 465 struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; 466 struct amdgpu_ctx *ctx; 467 int r; 468 469 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 470 if (!ctx) 471 return -ENOMEM; 472 473 mutex_lock(&mgr->lock); 474 r = idr_alloc(&mgr->ctx_handles, ctx, 1, AMDGPU_VM_MAX_NUM_CTX, GFP_KERNEL); 475 if (r < 0) { 476 mutex_unlock(&mgr->lock); 477 kfree(ctx); 478 return r; 479 } 480 481 *id = (uint32_t)r; 482 r = amdgpu_ctx_init(mgr, priority, filp, ctx); 483 if (r) { 484 idr_remove(&mgr->ctx_handles, *id); 485 *id = 0; 486 kfree(ctx); 487 } 488 mutex_unlock(&mgr->lock); 489 return r; 490 } 491 492 static void amdgpu_ctx_do_release(struct kref *ref) 493 { 494 struct amdgpu_ctx *ctx; 495 u32 i, j; 496 497 ctx = container_of(ref, struct amdgpu_ctx, refcount); 498 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 499 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 500 if (!ctx->entities[i][j]) 501 continue; 502 503 drm_sched_entity_destroy(&ctx->entities[i][j]->entity); 504 } 505 } 506 507 amdgpu_ctx_fini(ref); 508 } 509 510 static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id) 511 { 512 struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; 513 struct amdgpu_ctx *ctx; 514 515 mutex_lock(&mgr->lock); 516 ctx = idr_remove(&mgr->ctx_handles, id); 517 if (ctx) 518 kref_put(&ctx->refcount, amdgpu_ctx_do_release); 519 mutex_unlock(&mgr->lock); 520 return ctx ? 0 : -EINVAL; 521 } 522 523 static int amdgpu_ctx_query(struct amdgpu_device *adev, 524 struct amdgpu_fpriv *fpriv, uint32_t id, 525 union drm_amdgpu_ctx_out *out) 526 { 527 struct amdgpu_ctx *ctx; 528 struct amdgpu_ctx_mgr *mgr; 529 unsigned reset_counter; 530 531 if (!fpriv) 532 return -EINVAL; 533 534 mgr = &fpriv->ctx_mgr; 535 mutex_lock(&mgr->lock); 536 ctx = idr_find(&mgr->ctx_handles, id); 537 if (!ctx) { 538 mutex_unlock(&mgr->lock); 539 return -EINVAL; 540 } 541 542 /* TODO: these two are always zero */ 543 out->state.flags = 0x0; 544 out->state.hangs = 0x0; 545 546 /* determine if a GPU reset has occured since the last call */ 547 reset_counter = atomic_read(&adev->gpu_reset_counter); 548 /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */ 549 if (ctx->reset_counter_query == reset_counter) 550 out->state.reset_status = AMDGPU_CTX_NO_RESET; 551 else 552 out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET; 553 ctx->reset_counter_query = reset_counter; 554 555 mutex_unlock(&mgr->lock); 556 return 0; 557 } 558 559 #define AMDGPU_RAS_COUNTE_DELAY_MS 3000 560 561 static int amdgpu_ctx_query2(struct amdgpu_device *adev, 562 struct amdgpu_fpriv *fpriv, uint32_t id, 563 union drm_amdgpu_ctx_out *out) 564 { 565 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 566 struct amdgpu_ctx *ctx; 567 struct amdgpu_ctx_mgr *mgr; 568 569 if (!fpriv) 570 return -EINVAL; 571 572 mgr = &fpriv->ctx_mgr; 573 mutex_lock(&mgr->lock); 574 ctx = idr_find(&mgr->ctx_handles, id); 575 if (!ctx) { 576 mutex_unlock(&mgr->lock); 577 return -EINVAL; 578 } 579 580 out->state.flags = 0x0; 581 out->state.hangs = 0x0; 582 583 if (ctx->reset_counter != atomic_read(&adev->gpu_reset_counter)) 584 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RESET; 585 586 if (ctx->vram_lost_counter != atomic_read(&adev->vram_lost_counter)) 587 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST; 588 589 if (atomic_read(&ctx->guilty)) 590 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY; 591 592 if (amdgpu_in_reset(adev)) 593 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS; 594 595 if (adev->ras_enabled && con) { 596 /* Return the cached values in O(1), 597 * and schedule delayed work to cache 598 * new vaues. 599 */ 600 int ce_count, ue_count; 601 602 ce_count = atomic_read(&con->ras_ce_count); 603 ue_count = atomic_read(&con->ras_ue_count); 604 605 if (ce_count != ctx->ras_counter_ce) { 606 ctx->ras_counter_ce = ce_count; 607 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE; 608 } 609 610 if (ue_count != ctx->ras_counter_ue) { 611 ctx->ras_counter_ue = ue_count; 612 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE; 613 } 614 615 schedule_delayed_work(&con->ras_counte_delay_work, 616 msecs_to_jiffies(AMDGPU_RAS_COUNTE_DELAY_MS)); 617 } 618 619 mutex_unlock(&mgr->lock); 620 return 0; 621 } 622 623 624 625 static int amdgpu_ctx_stable_pstate(struct amdgpu_device *adev, 626 struct amdgpu_fpriv *fpriv, uint32_t id, 627 bool set, u32 *stable_pstate) 628 { 629 struct amdgpu_ctx *ctx; 630 struct amdgpu_ctx_mgr *mgr; 631 int r; 632 633 if (!fpriv) 634 return -EINVAL; 635 636 mgr = &fpriv->ctx_mgr; 637 mutex_lock(&mgr->lock); 638 ctx = idr_find(&mgr->ctx_handles, id); 639 if (!ctx) { 640 mutex_unlock(&mgr->lock); 641 return -EINVAL; 642 } 643 644 if (set) 645 r = amdgpu_ctx_set_stable_pstate(ctx, *stable_pstate); 646 else 647 r = amdgpu_ctx_get_stable_pstate(ctx, stable_pstate); 648 649 mutex_unlock(&mgr->lock); 650 return r; 651 } 652 653 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 654 struct drm_file *filp) 655 { 656 int r; 657 uint32_t id, stable_pstate; 658 int32_t priority; 659 660 union drm_amdgpu_ctx *args = data; 661 struct amdgpu_device *adev = drm_to_adev(dev); 662 struct amdgpu_fpriv *fpriv = filp->driver_priv; 663 664 id = args->in.ctx_id; 665 priority = args->in.priority; 666 667 /* For backwards compatibility reasons, we need to accept 668 * ioctls with garbage in the priority field */ 669 if (!amdgpu_ctx_priority_is_valid(priority)) 670 priority = AMDGPU_CTX_PRIORITY_NORMAL; 671 672 switch (args->in.op) { 673 case AMDGPU_CTX_OP_ALLOC_CTX: 674 r = amdgpu_ctx_alloc(adev, fpriv, filp, priority, &id); 675 args->out.alloc.ctx_id = id; 676 break; 677 case AMDGPU_CTX_OP_FREE_CTX: 678 r = amdgpu_ctx_free(fpriv, id); 679 break; 680 case AMDGPU_CTX_OP_QUERY_STATE: 681 r = amdgpu_ctx_query(adev, fpriv, id, &args->out); 682 break; 683 case AMDGPU_CTX_OP_QUERY_STATE2: 684 r = amdgpu_ctx_query2(adev, fpriv, id, &args->out); 685 break; 686 case AMDGPU_CTX_OP_GET_STABLE_PSTATE: 687 if (args->in.flags) 688 return -EINVAL; 689 r = amdgpu_ctx_stable_pstate(adev, fpriv, id, false, &stable_pstate); 690 if (!r) 691 args->out.pstate.flags = stable_pstate; 692 break; 693 case AMDGPU_CTX_OP_SET_STABLE_PSTATE: 694 if (args->in.flags & ~AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK) 695 return -EINVAL; 696 stable_pstate = args->in.flags & AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK; 697 if (stable_pstate > AMDGPU_CTX_STABLE_PSTATE_PEAK) 698 return -EINVAL; 699 r = amdgpu_ctx_stable_pstate(adev, fpriv, id, true, &stable_pstate); 700 break; 701 default: 702 return -EINVAL; 703 } 704 705 return r; 706 } 707 708 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id) 709 { 710 struct amdgpu_ctx *ctx; 711 struct amdgpu_ctx_mgr *mgr; 712 713 if (!fpriv) 714 return NULL; 715 716 mgr = &fpriv->ctx_mgr; 717 718 mutex_lock(&mgr->lock); 719 ctx = idr_find(&mgr->ctx_handles, id); 720 if (ctx) 721 kref_get(&ctx->refcount); 722 mutex_unlock(&mgr->lock); 723 return ctx; 724 } 725 726 int amdgpu_ctx_put(struct amdgpu_ctx *ctx) 727 { 728 if (ctx == NULL) 729 return -EINVAL; 730 731 kref_put(&ctx->refcount, amdgpu_ctx_do_release); 732 return 0; 733 } 734 735 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, 736 struct drm_sched_entity *entity, 737 struct dma_fence *fence) 738 { 739 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 740 uint64_t seq = centity->sequence; 741 struct dma_fence *other = NULL; 742 unsigned idx = 0; 743 744 idx = seq & (amdgpu_sched_jobs - 1); 745 other = centity->fences[idx]; 746 WARN_ON(other && !dma_fence_is_signaled(other)); 747 748 dma_fence_get(fence); 749 750 spin_lock(&ctx->ring_lock); 751 centity->fences[idx] = fence; 752 centity->sequence++; 753 spin_unlock(&ctx->ring_lock); 754 755 atomic64_add(ktime_to_ns(amdgpu_ctx_fence_time(other)), 756 &ctx->mgr->time_spend[centity->hw_ip]); 757 758 dma_fence_put(other); 759 return seq; 760 } 761 762 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 763 struct drm_sched_entity *entity, 764 uint64_t seq) 765 { 766 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 767 struct dma_fence *fence; 768 769 spin_lock(&ctx->ring_lock); 770 771 if (seq == ~0ull) 772 seq = centity->sequence - 1; 773 774 if (seq >= centity->sequence) { 775 spin_unlock(&ctx->ring_lock); 776 return ERR_PTR(-EINVAL); 777 } 778 779 780 if (seq + amdgpu_sched_jobs < centity->sequence) { 781 spin_unlock(&ctx->ring_lock); 782 return NULL; 783 } 784 785 fence = dma_fence_get(centity->fences[seq & (amdgpu_sched_jobs - 1)]); 786 spin_unlock(&ctx->ring_lock); 787 788 return fence; 789 } 790 791 static void amdgpu_ctx_set_entity_priority(struct amdgpu_ctx *ctx, 792 struct amdgpu_ctx_entity *aentity, 793 int hw_ip, 794 int32_t priority) 795 { 796 struct amdgpu_device *adev = ctx->mgr->adev; 797 unsigned int hw_prio; 798 struct drm_gpu_scheduler **scheds = NULL; 799 unsigned num_scheds; 800 801 /* set sw priority */ 802 drm_sched_entity_set_priority(&aentity->entity, 803 amdgpu_ctx_to_drm_sched_prio(priority)); 804 805 /* set hw priority */ 806 if (hw_ip == AMDGPU_HW_IP_COMPUTE || hw_ip == AMDGPU_HW_IP_GFX) { 807 hw_prio = amdgpu_ctx_get_hw_prio(ctx, hw_ip); 808 hw_prio = array_index_nospec(hw_prio, AMDGPU_RING_PRIO_MAX); 809 scheds = adev->gpu_sched[hw_ip][hw_prio].sched; 810 num_scheds = adev->gpu_sched[hw_ip][hw_prio].num_scheds; 811 drm_sched_entity_modify_sched(&aentity->entity, scheds, 812 num_scheds); 813 } 814 } 815 816 void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, 817 int32_t priority) 818 { 819 int32_t ctx_prio; 820 unsigned i, j; 821 822 ctx->override_priority = priority; 823 824 ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? 825 ctx->init_priority : ctx->override_priority; 826 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 827 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 828 if (!ctx->entities[i][j]) 829 continue; 830 831 amdgpu_ctx_set_entity_priority(ctx, ctx->entities[i][j], 832 i, ctx_prio); 833 } 834 } 835 } 836 837 int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, 838 struct drm_sched_entity *entity) 839 { 840 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 841 struct dma_fence *other; 842 unsigned idx; 843 long r; 844 845 spin_lock(&ctx->ring_lock); 846 idx = centity->sequence & (amdgpu_sched_jobs - 1); 847 other = dma_fence_get(centity->fences[idx]); 848 spin_unlock(&ctx->ring_lock); 849 850 if (!other) 851 return 0; 852 853 r = dma_fence_wait(other, true); 854 if (r < 0 && r != -ERESTARTSYS) 855 DRM_ERROR("Error (%ld) waiting for fence!\n", r); 856 857 dma_fence_put(other); 858 return r; 859 } 860 861 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr, 862 struct amdgpu_device *adev) 863 { 864 unsigned int i; 865 866 mgr->adev = adev; 867 mutex_init(&mgr->lock); 868 idr_init_base(&mgr->ctx_handles, 1); 869 870 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) 871 atomic64_set(&mgr->time_spend[i], 0); 872 } 873 874 long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout) 875 { 876 struct amdgpu_ctx *ctx; 877 struct idr *idp; 878 uint32_t id, i, j; 879 880 idp = &mgr->ctx_handles; 881 882 mutex_lock(&mgr->lock); 883 idr_for_each_entry(idp, ctx, id) { 884 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 885 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 886 struct drm_sched_entity *entity; 887 888 if (!ctx->entities[i][j]) 889 continue; 890 891 entity = &ctx->entities[i][j]->entity; 892 timeout = drm_sched_entity_flush(entity, timeout); 893 } 894 } 895 } 896 mutex_unlock(&mgr->lock); 897 return timeout; 898 } 899 900 void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr) 901 { 902 struct amdgpu_ctx *ctx; 903 struct idr *idp; 904 uint32_t id, i, j; 905 906 idp = &mgr->ctx_handles; 907 908 idr_for_each_entry(idp, ctx, id) { 909 if (kref_read(&ctx->refcount) != 1) { 910 DRM_ERROR("ctx %p is still alive\n", ctx); 911 continue; 912 } 913 914 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 915 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 916 struct drm_sched_entity *entity; 917 918 if (!ctx->entities[i][j]) 919 continue; 920 921 entity = &ctx->entities[i][j]->entity; 922 drm_sched_entity_fini(entity); 923 } 924 } 925 } 926 } 927 928 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr) 929 { 930 struct amdgpu_ctx *ctx; 931 struct idr *idp; 932 uint32_t id; 933 934 amdgpu_ctx_mgr_entity_fini(mgr); 935 936 idp = &mgr->ctx_handles; 937 938 idr_for_each_entry(idp, ctx, id) { 939 if (kref_put(&ctx->refcount, amdgpu_ctx_fini) != 1) 940 DRM_ERROR("ctx %p is still alive\n", ctx); 941 } 942 943 idr_destroy(&mgr->ctx_handles); 944 mutex_destroy(&mgr->lock); 945 } 946 947 void amdgpu_ctx_mgr_usage(struct amdgpu_ctx_mgr *mgr, 948 ktime_t usage[AMDGPU_HW_IP_NUM]) 949 { 950 struct amdgpu_ctx *ctx; 951 unsigned int hw_ip, i; 952 uint32_t id; 953 954 /* 955 * This is a little bit racy because it can be that a ctx or a fence are 956 * destroyed just in the moment we try to account them. But that is ok 957 * since exactly that case is explicitely allowed by the interface. 958 */ 959 mutex_lock(&mgr->lock); 960 for (hw_ip = 0; hw_ip < AMDGPU_HW_IP_NUM; ++hw_ip) { 961 uint64_t ns = atomic64_read(&mgr->time_spend[hw_ip]); 962 963 usage[hw_ip] = ns_to_ktime(ns); 964 } 965 966 idr_for_each_entry(&mgr->ctx_handles, ctx, id) { 967 for (hw_ip = 0; hw_ip < AMDGPU_HW_IP_NUM; ++hw_ip) { 968 for (i = 0; i < amdgpu_ctx_num_entities[hw_ip]; ++i) { 969 struct amdgpu_ctx_entity *centity; 970 ktime_t spend; 971 972 centity = ctx->entities[hw_ip][i]; 973 if (!centity) 974 continue; 975 spend = amdgpu_ctx_entity_time(ctx, centity); 976 usage[hw_ip] = ktime_add(usage[hw_ip], spend); 977 } 978 } 979 } 980 mutex_unlock(&mgr->lock); 981 } 982