xref: /openbmc/linux/drivers/gpu/drm/amd/amdgpu/amdgpu.h (revision f3539c12d8196ce0a1993364d30b3a18908470d1)
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30 
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
38 
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
44 
45 #include <drm/drmP.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
48 
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_gds.h"
55 #include "amd_powerplay.h"
56 #include "amdgpu_acp.h"
57 
58 #include "gpu_scheduler.h"
59 
60 /*
61  * Modules parameters.
62  */
63 extern int amdgpu_modeset;
64 extern int amdgpu_vram_limit;
65 extern int amdgpu_gart_size;
66 extern int amdgpu_benchmarking;
67 extern int amdgpu_testing;
68 extern int amdgpu_audio;
69 extern int amdgpu_disp_priority;
70 extern int amdgpu_hw_i2c;
71 extern int amdgpu_pcie_gen2;
72 extern int amdgpu_msi;
73 extern int amdgpu_lockup_timeout;
74 extern int amdgpu_dpm;
75 extern int amdgpu_smc_load_fw;
76 extern int amdgpu_aspm;
77 extern int amdgpu_runtime_pm;
78 extern unsigned amdgpu_ip_block_mask;
79 extern int amdgpu_bapm;
80 extern int amdgpu_deep_color;
81 extern int amdgpu_vm_size;
82 extern int amdgpu_vm_block_size;
83 extern int amdgpu_vm_fault_stop;
84 extern int amdgpu_vm_debug;
85 extern int amdgpu_sched_jobs;
86 extern int amdgpu_sched_hw_submission;
87 extern int amdgpu_powerplay;
88 extern int amdgpu_powercontainment;
89 extern unsigned amdgpu_pcie_gen_cap;
90 extern unsigned amdgpu_pcie_lane_cap;
91 extern unsigned amdgpu_cg_mask;
92 extern unsigned amdgpu_pg_mask;
93 extern char *amdgpu_disable_cu;
94 
95 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000
96 #define AMDGPU_MAX_USEC_TIMEOUT			100000	/* 100 ms */
97 #define AMDGPU_FENCE_JIFFIES_TIMEOUT		(HZ / 2)
98 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
99 #define AMDGPU_IB_POOL_SIZE			16
100 #define AMDGPU_DEBUGFS_MAX_COMPONENTS		32
101 #define AMDGPUFB_CONN_LIMIT			4
102 #define AMDGPU_BIOS_NUM_SCRATCH			8
103 
104 /* max number of rings */
105 #define AMDGPU_MAX_RINGS			16
106 #define AMDGPU_MAX_GFX_RINGS			1
107 #define AMDGPU_MAX_COMPUTE_RINGS		8
108 #define AMDGPU_MAX_VCE_RINGS			2
109 
110 /* max number of IP instances */
111 #define AMDGPU_MAX_SDMA_INSTANCES		2
112 
113 /* hardcode that limit for now */
114 #define AMDGPU_VA_RESERVED_SIZE			(8 << 20)
115 
116 /* hard reset data */
117 #define AMDGPU_ASIC_RESET_DATA                  0x39d5e86b
118 
119 /* reset flags */
120 #define AMDGPU_RESET_GFX			(1 << 0)
121 #define AMDGPU_RESET_COMPUTE			(1 << 1)
122 #define AMDGPU_RESET_DMA			(1 << 2)
123 #define AMDGPU_RESET_CP				(1 << 3)
124 #define AMDGPU_RESET_GRBM			(1 << 4)
125 #define AMDGPU_RESET_DMA1			(1 << 5)
126 #define AMDGPU_RESET_RLC			(1 << 6)
127 #define AMDGPU_RESET_SEM			(1 << 7)
128 #define AMDGPU_RESET_IH				(1 << 8)
129 #define AMDGPU_RESET_VMC			(1 << 9)
130 #define AMDGPU_RESET_MC				(1 << 10)
131 #define AMDGPU_RESET_DISPLAY			(1 << 11)
132 #define AMDGPU_RESET_UVD			(1 << 12)
133 #define AMDGPU_RESET_VCE			(1 << 13)
134 #define AMDGPU_RESET_VCE1			(1 << 14)
135 
136 /* GFX current status */
137 #define AMDGPU_GFX_NORMAL_MODE			0x00000000L
138 #define AMDGPU_GFX_SAFE_MODE			0x00000001L
139 #define AMDGPU_GFX_PG_DISABLED_MODE		0x00000002L
140 #define AMDGPU_GFX_CG_DISABLED_MODE		0x00000004L
141 #define AMDGPU_GFX_LBPW_DISABLED_MODE		0x00000008L
142 
143 /* max cursor sizes (in pixels) */
144 #define CIK_CURSOR_WIDTH 128
145 #define CIK_CURSOR_HEIGHT 128
146 
147 struct amdgpu_device;
148 struct amdgpu_ib;
149 struct amdgpu_vm;
150 struct amdgpu_ring;
151 struct amdgpu_cs_parser;
152 struct amdgpu_job;
153 struct amdgpu_irq_src;
154 struct amdgpu_fpriv;
155 
156 enum amdgpu_cp_irq {
157 	AMDGPU_CP_IRQ_GFX_EOP = 0,
158 	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
159 	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
160 	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
161 	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
162 	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
163 	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
164 	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
165 	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
166 
167 	AMDGPU_CP_IRQ_LAST
168 };
169 
170 enum amdgpu_sdma_irq {
171 	AMDGPU_SDMA_IRQ_TRAP0 = 0,
172 	AMDGPU_SDMA_IRQ_TRAP1,
173 
174 	AMDGPU_SDMA_IRQ_LAST
175 };
176 
177 enum amdgpu_thermal_irq {
178 	AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
179 	AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
180 
181 	AMDGPU_THERMAL_IRQ_LAST
182 };
183 
184 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
185 				  enum amd_ip_block_type block_type,
186 				  enum amd_clockgating_state state);
187 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
188 				  enum amd_ip_block_type block_type,
189 				  enum amd_powergating_state state);
190 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
191 			 enum amd_ip_block_type block_type);
192 bool amdgpu_is_idle(struct amdgpu_device *adev,
193 		    enum amd_ip_block_type block_type);
194 
195 struct amdgpu_ip_block_version {
196 	enum amd_ip_block_type type;
197 	u32 major;
198 	u32 minor;
199 	u32 rev;
200 	const struct amd_ip_funcs *funcs;
201 };
202 
203 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
204 				enum amd_ip_block_type type,
205 				u32 major, u32 minor);
206 
207 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
208 					struct amdgpu_device *adev,
209 					enum amd_ip_block_type type);
210 
211 /* provided by hw blocks that can move/clear data.  e.g., gfx or sdma */
212 struct amdgpu_buffer_funcs {
213 	/* maximum bytes in a single operation */
214 	uint32_t	copy_max_bytes;
215 
216 	/* number of dw to reserve per operation */
217 	unsigned	copy_num_dw;
218 
219 	/* used for buffer migration */
220 	void (*emit_copy_buffer)(struct amdgpu_ib *ib,
221 				 /* src addr in bytes */
222 				 uint64_t src_offset,
223 				 /* dst addr in bytes */
224 				 uint64_t dst_offset,
225 				 /* number of byte to transfer */
226 				 uint32_t byte_count);
227 
228 	/* maximum bytes in a single operation */
229 	uint32_t	fill_max_bytes;
230 
231 	/* number of dw to reserve per operation */
232 	unsigned	fill_num_dw;
233 
234 	/* used for buffer clearing */
235 	void (*emit_fill_buffer)(struct amdgpu_ib *ib,
236 				 /* value to write to memory */
237 				 uint32_t src_data,
238 				 /* dst addr in bytes */
239 				 uint64_t dst_offset,
240 				 /* number of byte to fill */
241 				 uint32_t byte_count);
242 };
243 
244 /* provided by hw blocks that can write ptes, e.g., sdma */
245 struct amdgpu_vm_pte_funcs {
246 	/* copy pte entries from GART */
247 	void (*copy_pte)(struct amdgpu_ib *ib,
248 			 uint64_t pe, uint64_t src,
249 			 unsigned count);
250 	/* write pte one entry at a time with addr mapping */
251 	void (*write_pte)(struct amdgpu_ib *ib,
252 			  const dma_addr_t *pages_addr, uint64_t pe,
253 			  uint64_t addr, unsigned count,
254 			  uint32_t incr, uint32_t flags);
255 	/* for linear pte/pde updates without addr mapping */
256 	void (*set_pte_pde)(struct amdgpu_ib *ib,
257 			    uint64_t pe,
258 			    uint64_t addr, unsigned count,
259 			    uint32_t incr, uint32_t flags);
260 };
261 
262 /* provided by the gmc block */
263 struct amdgpu_gart_funcs {
264 	/* flush the vm tlb via mmio */
265 	void (*flush_gpu_tlb)(struct amdgpu_device *adev,
266 			      uint32_t vmid);
267 	/* write pte/pde updates using the cpu */
268 	int (*set_pte_pde)(struct amdgpu_device *adev,
269 			   void *cpu_pt_addr, /* cpu addr of page table */
270 			   uint32_t gpu_page_idx, /* pte/pde to update */
271 			   uint64_t addr, /* addr to write into pte/pde */
272 			   uint32_t flags); /* access flags */
273 };
274 
275 /* provided by the ih block */
276 struct amdgpu_ih_funcs {
277 	/* ring read/write ptr handling, called from interrupt context */
278 	u32 (*get_wptr)(struct amdgpu_device *adev);
279 	void (*decode_iv)(struct amdgpu_device *adev,
280 			  struct amdgpu_iv_entry *entry);
281 	void (*set_rptr)(struct amdgpu_device *adev);
282 };
283 
284 /* provided by hw blocks that expose a ring buffer for commands */
285 struct amdgpu_ring_funcs {
286 	/* ring read/write ptr handling */
287 	u32 (*get_rptr)(struct amdgpu_ring *ring);
288 	u32 (*get_wptr)(struct amdgpu_ring *ring);
289 	void (*set_wptr)(struct amdgpu_ring *ring);
290 	/* validating and patching of IBs */
291 	int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
292 	/* command emit functions */
293 	void (*emit_ib)(struct amdgpu_ring *ring,
294 			struct amdgpu_ib *ib,
295 			unsigned vm_id, bool ctx_switch);
296 	void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
297 			   uint64_t seq, unsigned flags);
298 	void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
299 	void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
300 			      uint64_t pd_addr);
301 	void (*emit_hdp_flush)(struct amdgpu_ring *ring);
302 	void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
303 	void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
304 				uint32_t gds_base, uint32_t gds_size,
305 				uint32_t gws_base, uint32_t gws_size,
306 				uint32_t oa_base, uint32_t oa_size);
307 	/* testing functions */
308 	int (*test_ring)(struct amdgpu_ring *ring);
309 	int (*test_ib)(struct amdgpu_ring *ring, long timeout);
310 	/* insert NOP packets */
311 	void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
312 	/* pad the indirect buffer to the necessary number of dw */
313 	void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
314 	unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
315 	void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
316 	/* note usage for clock and power gating */
317 	void (*begin_use)(struct amdgpu_ring *ring);
318 	void (*end_use)(struct amdgpu_ring *ring);
319 };
320 
321 /*
322  * BIOS.
323  */
324 bool amdgpu_get_bios(struct amdgpu_device *adev);
325 bool amdgpu_read_bios(struct amdgpu_device *adev);
326 
327 /*
328  * Dummy page
329  */
330 struct amdgpu_dummy_page {
331 	struct page	*page;
332 	dma_addr_t	addr;
333 };
334 int amdgpu_dummy_page_init(struct amdgpu_device *adev);
335 void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
336 
337 
338 /*
339  * Clocks
340  */
341 
342 #define AMDGPU_MAX_PPLL 3
343 
344 struct amdgpu_clock {
345 	struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
346 	struct amdgpu_pll spll;
347 	struct amdgpu_pll mpll;
348 	/* 10 Khz units */
349 	uint32_t default_mclk;
350 	uint32_t default_sclk;
351 	uint32_t default_dispclk;
352 	uint32_t current_dispclk;
353 	uint32_t dp_extclk;
354 	uint32_t max_pixel_clock;
355 };
356 
357 /*
358  * Fences.
359  */
360 struct amdgpu_fence_driver {
361 	uint64_t			gpu_addr;
362 	volatile uint32_t		*cpu_addr;
363 	/* sync_seq is protected by ring emission lock */
364 	uint32_t			sync_seq;
365 	atomic_t			last_seq;
366 	bool				initialized;
367 	struct amdgpu_irq_src		*irq_src;
368 	unsigned			irq_type;
369 	struct timer_list		fallback_timer;
370 	unsigned			num_fences_mask;
371 	spinlock_t			lock;
372 	struct fence			**fences;
373 };
374 
375 /* some special values for the owner field */
376 #define AMDGPU_FENCE_OWNER_UNDEFINED	((void*)0ul)
377 #define AMDGPU_FENCE_OWNER_VM		((void*)1ul)
378 
379 #define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
380 #define AMDGPU_FENCE_FLAG_INT           (1 << 1)
381 
382 int amdgpu_fence_driver_init(struct amdgpu_device *adev);
383 void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
384 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
385 
386 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
387 				  unsigned num_hw_submission);
388 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
389 				   struct amdgpu_irq_src *irq_src,
390 				   unsigned irq_type);
391 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
392 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
393 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence);
394 void amdgpu_fence_process(struct amdgpu_ring *ring);
395 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
396 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
397 
398 /*
399  * TTM.
400  */
401 
402 #define AMDGPU_TTM_LRU_SIZE	20
403 
404 struct amdgpu_mman_lru {
405 	struct list_head		*lru[TTM_NUM_MEM_TYPES];
406 	struct list_head		*swap_lru;
407 };
408 
409 struct amdgpu_mman {
410 	struct ttm_bo_global_ref        bo_global_ref;
411 	struct drm_global_reference	mem_global_ref;
412 	struct ttm_bo_device		bdev;
413 	bool				mem_global_referenced;
414 	bool				initialized;
415 
416 #if defined(CONFIG_DEBUG_FS)
417 	struct dentry			*vram;
418 	struct dentry			*gtt;
419 #endif
420 
421 	/* buffer handling */
422 	const struct amdgpu_buffer_funcs	*buffer_funcs;
423 	struct amdgpu_ring			*buffer_funcs_ring;
424 	/* Scheduler entity for buffer moves */
425 	struct amd_sched_entity			entity;
426 
427 	/* custom LRU management */
428 	struct amdgpu_mman_lru			log2_size[AMDGPU_TTM_LRU_SIZE];
429 	/* guard for log2_size array, don't add anything in between */
430 	struct amdgpu_mman_lru			guard;
431 };
432 
433 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
434 		       uint64_t src_offset,
435 		       uint64_t dst_offset,
436 		       uint32_t byte_count,
437 		       struct reservation_object *resv,
438 		       struct fence **fence);
439 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
440 
441 struct amdgpu_bo_list_entry {
442 	struct amdgpu_bo		*robj;
443 	struct ttm_validate_buffer	tv;
444 	struct amdgpu_bo_va		*bo_va;
445 	uint32_t			priority;
446 	struct page			**user_pages;
447 	int				user_invalidated;
448 };
449 
450 struct amdgpu_bo_va_mapping {
451 	struct list_head		list;
452 	struct interval_tree_node	it;
453 	uint64_t			offset;
454 	uint32_t			flags;
455 };
456 
457 /* bo virtual addresses in a specific vm */
458 struct amdgpu_bo_va {
459 	/* protected by bo being reserved */
460 	struct list_head		bo_list;
461 	struct fence		        *last_pt_update;
462 	unsigned			ref_count;
463 
464 	/* protected by vm mutex and spinlock */
465 	struct list_head		vm_status;
466 
467 	/* mappings for this bo_va */
468 	struct list_head		invalids;
469 	struct list_head		valids;
470 
471 	/* constant after initialization */
472 	struct amdgpu_vm		*vm;
473 	struct amdgpu_bo		*bo;
474 };
475 
476 #define AMDGPU_GEM_DOMAIN_MAX		0x3
477 
478 struct amdgpu_bo {
479 	/* Protected by gem.mutex */
480 	struct list_head		list;
481 	/* Protected by tbo.reserved */
482 	u32				prefered_domains;
483 	u32				allowed_domains;
484 	struct ttm_place		placements[AMDGPU_GEM_DOMAIN_MAX + 1];
485 	struct ttm_placement		placement;
486 	struct ttm_buffer_object	tbo;
487 	struct ttm_bo_kmap_obj		kmap;
488 	u64				flags;
489 	unsigned			pin_count;
490 	void				*kptr;
491 	u64				tiling_flags;
492 	u64				metadata_flags;
493 	void				*metadata;
494 	u32				metadata_size;
495 	/* list of all virtual address to which this bo
496 	 * is associated to
497 	 */
498 	struct list_head		va;
499 	/* Constant after initialization */
500 	struct amdgpu_device		*adev;
501 	struct drm_gem_object		gem_base;
502 	struct amdgpu_bo		*parent;
503 
504 	struct ttm_bo_kmap_obj		dma_buf_vmap;
505 	struct amdgpu_mn		*mn;
506 	struct list_head		mn_list;
507 };
508 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
509 
510 void amdgpu_gem_object_free(struct drm_gem_object *obj);
511 int amdgpu_gem_object_open(struct drm_gem_object *obj,
512 				struct drm_file *file_priv);
513 void amdgpu_gem_object_close(struct drm_gem_object *obj,
514 				struct drm_file *file_priv);
515 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
516 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
517 struct drm_gem_object *
518 amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
519 				 struct dma_buf_attachment *attach,
520 				 struct sg_table *sg);
521 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
522 					struct drm_gem_object *gobj,
523 					int flags);
524 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
525 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
526 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
527 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
528 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
529 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
530 
531 /* sub-allocation manager, it has to be protected by another lock.
532  * By conception this is an helper for other part of the driver
533  * like the indirect buffer or semaphore, which both have their
534  * locking.
535  *
536  * Principe is simple, we keep a list of sub allocation in offset
537  * order (first entry has offset == 0, last entry has the highest
538  * offset).
539  *
540  * When allocating new object we first check if there is room at
541  * the end total_size - (last_object_offset + last_object_size) >=
542  * alloc_size. If so we allocate new object there.
543  *
544  * When there is not enough room at the end, we start waiting for
545  * each sub object until we reach object_offset+object_size >=
546  * alloc_size, this object then become the sub object we return.
547  *
548  * Alignment can't be bigger than page size.
549  *
550  * Hole are not considered for allocation to keep things simple.
551  * Assumption is that there won't be hole (all object on same
552  * alignment).
553  */
554 
555 #define AMDGPU_SA_NUM_FENCE_LISTS	32
556 
557 struct amdgpu_sa_manager {
558 	wait_queue_head_t	wq;
559 	struct amdgpu_bo	*bo;
560 	struct list_head	*hole;
561 	struct list_head	flist[AMDGPU_SA_NUM_FENCE_LISTS];
562 	struct list_head	olist;
563 	unsigned		size;
564 	uint64_t		gpu_addr;
565 	void			*cpu_ptr;
566 	uint32_t		domain;
567 	uint32_t		align;
568 };
569 
570 /* sub-allocation buffer */
571 struct amdgpu_sa_bo {
572 	struct list_head		olist;
573 	struct list_head		flist;
574 	struct amdgpu_sa_manager	*manager;
575 	unsigned			soffset;
576 	unsigned			eoffset;
577 	struct fence		        *fence;
578 };
579 
580 /*
581  * GEM objects.
582  */
583 void amdgpu_gem_force_release(struct amdgpu_device *adev);
584 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
585 				int alignment, u32 initial_domain,
586 				u64 flags, bool kernel,
587 				struct drm_gem_object **obj);
588 
589 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
590 			    struct drm_device *dev,
591 			    struct drm_mode_create_dumb *args);
592 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
593 			  struct drm_device *dev,
594 			  uint32_t handle, uint64_t *offset_p);
595 /*
596  * Synchronization
597  */
598 struct amdgpu_sync {
599 	DECLARE_HASHTABLE(fences, 4);
600 	struct fence	        *last_vm_update;
601 };
602 
603 void amdgpu_sync_create(struct amdgpu_sync *sync);
604 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
605 		      struct fence *f);
606 int amdgpu_sync_resv(struct amdgpu_device *adev,
607 		     struct amdgpu_sync *sync,
608 		     struct reservation_object *resv,
609 		     void *owner);
610 struct fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
611 				     struct amdgpu_ring *ring);
612 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
613 void amdgpu_sync_free(struct amdgpu_sync *sync);
614 int amdgpu_sync_init(void);
615 void amdgpu_sync_fini(void);
616 int amdgpu_fence_slab_init(void);
617 void amdgpu_fence_slab_fini(void);
618 
619 /*
620  * GART structures, functions & helpers
621  */
622 struct amdgpu_mc;
623 
624 #define AMDGPU_GPU_PAGE_SIZE 4096
625 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
626 #define AMDGPU_GPU_PAGE_SHIFT 12
627 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
628 
629 struct amdgpu_gart {
630 	dma_addr_t			table_addr;
631 	struct amdgpu_bo		*robj;
632 	void				*ptr;
633 	unsigned			num_gpu_pages;
634 	unsigned			num_cpu_pages;
635 	unsigned			table_size;
636 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
637 	struct page			**pages;
638 #endif
639 	bool				ready;
640 	const struct amdgpu_gart_funcs *gart_funcs;
641 };
642 
643 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
644 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
645 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
646 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
647 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
648 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
649 int amdgpu_gart_init(struct amdgpu_device *adev);
650 void amdgpu_gart_fini(struct amdgpu_device *adev);
651 void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
652 			int pages);
653 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
654 		     int pages, struct page **pagelist,
655 		     dma_addr_t *dma_addr, uint32_t flags);
656 
657 /*
658  * GPU MC structures, functions & helpers
659  */
660 struct amdgpu_mc {
661 	resource_size_t		aper_size;
662 	resource_size_t		aper_base;
663 	resource_size_t		agp_base;
664 	/* for some chips with <= 32MB we need to lie
665 	 * about vram size near mc fb location */
666 	u64			mc_vram_size;
667 	u64			visible_vram_size;
668 	u64			gtt_size;
669 	u64			gtt_start;
670 	u64			gtt_end;
671 	u64			vram_start;
672 	u64			vram_end;
673 	unsigned		vram_width;
674 	u64			real_vram_size;
675 	int			vram_mtrr;
676 	u64                     gtt_base_align;
677 	u64                     mc_mask;
678 	const struct firmware   *fw;	/* MC firmware */
679 	uint32_t                fw_version;
680 	struct amdgpu_irq_src	vm_fault;
681 	uint32_t		vram_type;
682 };
683 
684 /*
685  * GPU doorbell structures, functions & helpers
686  */
687 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
688 {
689 	AMDGPU_DOORBELL_KIQ                     = 0x000,
690 	AMDGPU_DOORBELL_HIQ                     = 0x001,
691 	AMDGPU_DOORBELL_DIQ                     = 0x002,
692 	AMDGPU_DOORBELL_MEC_RING0               = 0x010,
693 	AMDGPU_DOORBELL_MEC_RING1               = 0x011,
694 	AMDGPU_DOORBELL_MEC_RING2               = 0x012,
695 	AMDGPU_DOORBELL_MEC_RING3               = 0x013,
696 	AMDGPU_DOORBELL_MEC_RING4               = 0x014,
697 	AMDGPU_DOORBELL_MEC_RING5               = 0x015,
698 	AMDGPU_DOORBELL_MEC_RING6               = 0x016,
699 	AMDGPU_DOORBELL_MEC_RING7               = 0x017,
700 	AMDGPU_DOORBELL_GFX_RING0               = 0x020,
701 	AMDGPU_DOORBELL_sDMA_ENGINE0            = 0x1E0,
702 	AMDGPU_DOORBELL_sDMA_ENGINE1            = 0x1E1,
703 	AMDGPU_DOORBELL_IH                      = 0x1E8,
704 	AMDGPU_DOORBELL_MAX_ASSIGNMENT          = 0x3FF,
705 	AMDGPU_DOORBELL_INVALID                 = 0xFFFF
706 } AMDGPU_DOORBELL_ASSIGNMENT;
707 
708 struct amdgpu_doorbell {
709 	/* doorbell mmio */
710 	resource_size_t		base;
711 	resource_size_t		size;
712 	u32 __iomem		*ptr;
713 	u32			num_doorbells;	/* Number of doorbells actually reserved for amdgpu. */
714 };
715 
716 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
717 				phys_addr_t *aperture_base,
718 				size_t *aperture_size,
719 				size_t *start_offset);
720 
721 /*
722  * IRQS.
723  */
724 
725 struct amdgpu_flip_work {
726 	struct work_struct		flip_work;
727 	struct work_struct		unpin_work;
728 	struct amdgpu_device		*adev;
729 	int				crtc_id;
730 	uint64_t			base;
731 	struct drm_pending_vblank_event *event;
732 	struct amdgpu_bo		*old_rbo;
733 	struct fence			*excl;
734 	unsigned			shared_count;
735 	struct fence			**shared;
736 	struct fence_cb			cb;
737 	bool				async;
738 };
739 
740 
741 /*
742  * CP & rings.
743  */
744 
745 struct amdgpu_ib {
746 	struct amdgpu_sa_bo		*sa_bo;
747 	uint32_t			length_dw;
748 	uint64_t			gpu_addr;
749 	uint32_t			*ptr;
750 	uint32_t			flags;
751 };
752 
753 enum amdgpu_ring_type {
754 	AMDGPU_RING_TYPE_GFX,
755 	AMDGPU_RING_TYPE_COMPUTE,
756 	AMDGPU_RING_TYPE_SDMA,
757 	AMDGPU_RING_TYPE_UVD,
758 	AMDGPU_RING_TYPE_VCE
759 };
760 
761 extern const struct amd_sched_backend_ops amdgpu_sched_ops;
762 
763 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
764 		     struct amdgpu_job **job, struct amdgpu_vm *vm);
765 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
766 			     struct amdgpu_job **job);
767 
768 void amdgpu_job_free_resources(struct amdgpu_job *job);
769 void amdgpu_job_free(struct amdgpu_job *job);
770 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
771 		      struct amd_sched_entity *entity, void *owner,
772 		      struct fence **f);
773 
774 struct amdgpu_ring {
775 	struct amdgpu_device		*adev;
776 	const struct amdgpu_ring_funcs	*funcs;
777 	struct amdgpu_fence_driver	fence_drv;
778 	struct amd_gpu_scheduler	sched;
779 
780 	struct amdgpu_bo	*ring_obj;
781 	volatile uint32_t	*ring;
782 	unsigned		rptr_offs;
783 	unsigned		wptr;
784 	unsigned		wptr_old;
785 	unsigned		ring_size;
786 	unsigned		max_dw;
787 	int			count_dw;
788 	uint64_t		gpu_addr;
789 	uint32_t		align_mask;
790 	uint32_t		ptr_mask;
791 	bool			ready;
792 	u32			nop;
793 	u32			idx;
794 	u32			me;
795 	u32			pipe;
796 	u32			queue;
797 	struct amdgpu_bo	*mqd_obj;
798 	u32			doorbell_index;
799 	bool			use_doorbell;
800 	unsigned		wptr_offs;
801 	unsigned		fence_offs;
802 	uint64_t		current_ctx;
803 	enum amdgpu_ring_type	type;
804 	char			name[16];
805 	unsigned		cond_exe_offs;
806 	u64			cond_exe_gpu_addr;
807 	volatile u32		*cond_exe_cpu_addr;
808 #if defined(CONFIG_DEBUG_FS)
809 	struct dentry *ent;
810 #endif
811 };
812 
813 /*
814  * VM
815  */
816 
817 /* maximum number of VMIDs */
818 #define AMDGPU_NUM_VM	16
819 
820 /* number of entries in page table */
821 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
822 
823 /* PTBs (Page Table Blocks) need to be aligned to 32K */
824 #define AMDGPU_VM_PTB_ALIGN_SIZE   32768
825 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
826 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
827 
828 #define AMDGPU_PTE_VALID	(1 << 0)
829 #define AMDGPU_PTE_SYSTEM	(1 << 1)
830 #define AMDGPU_PTE_SNOOPED	(1 << 2)
831 
832 /* VI only */
833 #define AMDGPU_PTE_EXECUTABLE	(1 << 4)
834 
835 #define AMDGPU_PTE_READABLE	(1 << 5)
836 #define AMDGPU_PTE_WRITEABLE	(1 << 6)
837 
838 /* PTE (Page Table Entry) fragment field for different page sizes */
839 #define AMDGPU_PTE_FRAG_4KB	(0 << 7)
840 #define AMDGPU_PTE_FRAG_64KB	(4 << 7)
841 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
842 
843 /* How to programm VM fault handling */
844 #define AMDGPU_VM_FAULT_STOP_NEVER	0
845 #define AMDGPU_VM_FAULT_STOP_FIRST	1
846 #define AMDGPU_VM_FAULT_STOP_ALWAYS	2
847 
848 struct amdgpu_vm_pt {
849 	struct amdgpu_bo_list_entry	entry;
850 	uint64_t			addr;
851 };
852 
853 struct amdgpu_vm {
854 	/* tree of virtual addresses mapped */
855 	struct rb_root		va;
856 
857 	/* protecting invalidated */
858 	spinlock_t		status_lock;
859 
860 	/* BOs moved, but not yet updated in the PT */
861 	struct list_head	invalidated;
862 
863 	/* BOs cleared in the PT because of a move */
864 	struct list_head	cleared;
865 
866 	/* BO mappings freed, but not yet updated in the PT */
867 	struct list_head	freed;
868 
869 	/* contains the page directory */
870 	struct amdgpu_bo	*page_directory;
871 	unsigned		max_pde_used;
872 	struct fence		*page_directory_fence;
873 	uint64_t		last_eviction_counter;
874 
875 	/* array of page tables, one for each page directory entry */
876 	struct amdgpu_vm_pt	*page_tables;
877 
878 	/* for id and flush management per ring */
879 	struct amdgpu_vm_id	*ids[AMDGPU_MAX_RINGS];
880 
881 	/* protecting freed */
882 	spinlock_t		freed_lock;
883 
884 	/* Scheduler entity for page table updates */
885 	struct amd_sched_entity	entity;
886 
887 	/* client id */
888 	u64                     client_id;
889 };
890 
891 struct amdgpu_vm_id {
892 	struct list_head	list;
893 	struct fence		*first;
894 	struct amdgpu_sync	active;
895 	struct fence		*last_flush;
896 	atomic64_t		owner;
897 
898 	uint64_t		pd_gpu_addr;
899 	/* last flushed PD/PT update */
900 	struct fence		*flushed_updates;
901 
902 	uint32_t                current_gpu_reset_count;
903 
904 	uint32_t		gds_base;
905 	uint32_t		gds_size;
906 	uint32_t		gws_base;
907 	uint32_t		gws_size;
908 	uint32_t		oa_base;
909 	uint32_t		oa_size;
910 };
911 
912 struct amdgpu_vm_manager {
913 	/* Handling of VMIDs */
914 	struct mutex				lock;
915 	unsigned				num_ids;
916 	struct list_head			ids_lru;
917 	struct amdgpu_vm_id			ids[AMDGPU_NUM_VM];
918 
919 	/* Handling of VM fences */
920 	u64					fence_context;
921 	unsigned				seqno[AMDGPU_MAX_RINGS];
922 
923 	uint32_t				max_pfn;
924 	/* vram base address for page table entry  */
925 	u64					vram_base_offset;
926 	/* is vm enabled? */
927 	bool					enabled;
928 	/* vm pte handling */
929 	const struct amdgpu_vm_pte_funcs        *vm_pte_funcs;
930 	struct amdgpu_ring                      *vm_pte_rings[AMDGPU_MAX_RINGS];
931 	unsigned				vm_pte_num_rings;
932 	atomic_t				vm_pte_next_ring;
933 	/* client id counter */
934 	atomic64_t				client_counter;
935 };
936 
937 void amdgpu_vm_manager_init(struct amdgpu_device *adev);
938 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
939 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
940 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
941 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
942 			 struct list_head *validated,
943 			 struct amdgpu_bo_list_entry *entry);
944 void amdgpu_vm_get_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
945 			  struct list_head *duplicates);
946 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
947 				  struct amdgpu_vm *vm);
948 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
949 		      struct amdgpu_sync *sync, struct fence *fence,
950 		      struct amdgpu_job *job);
951 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job);
952 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
953 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
954 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
955 				    struct amdgpu_vm *vm);
956 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
957 			  struct amdgpu_vm *vm);
958 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
959 			     struct amdgpu_sync *sync);
960 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
961 			struct amdgpu_bo_va *bo_va,
962 			struct ttm_mem_reg *mem);
963 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
964 			     struct amdgpu_bo *bo);
965 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
966 				       struct amdgpu_bo *bo);
967 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
968 				      struct amdgpu_vm *vm,
969 				      struct amdgpu_bo *bo);
970 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
971 		     struct amdgpu_bo_va *bo_va,
972 		     uint64_t addr, uint64_t offset,
973 		     uint64_t size, uint32_t flags);
974 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
975 		       struct amdgpu_bo_va *bo_va,
976 		       uint64_t addr);
977 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
978 		      struct amdgpu_bo_va *bo_va);
979 
980 /*
981  * context related structures
982  */
983 
984 struct amdgpu_ctx_ring {
985 	uint64_t		sequence;
986 	struct fence		**fences;
987 	struct amd_sched_entity	entity;
988 };
989 
990 struct amdgpu_ctx {
991 	struct kref		refcount;
992 	struct amdgpu_device    *adev;
993 	unsigned		reset_counter;
994 	spinlock_t		ring_lock;
995 	struct fence            **fences;
996 	struct amdgpu_ctx_ring	rings[AMDGPU_MAX_RINGS];
997 };
998 
999 struct amdgpu_ctx_mgr {
1000 	struct amdgpu_device	*adev;
1001 	struct mutex		lock;
1002 	/* protected by lock */
1003 	struct idr		ctx_handles;
1004 };
1005 
1006 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1007 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1008 
1009 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
1010 			      struct fence *fence);
1011 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1012 				   struct amdgpu_ring *ring, uint64_t seq);
1013 
1014 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1015 		     struct drm_file *filp);
1016 
1017 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1018 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
1019 
1020 /*
1021  * file private structure
1022  */
1023 
1024 struct amdgpu_fpriv {
1025 	struct amdgpu_vm	vm;
1026 	struct mutex		bo_list_lock;
1027 	struct idr		bo_list_handles;
1028 	struct amdgpu_ctx_mgr	ctx_mgr;
1029 };
1030 
1031 /*
1032  * residency list
1033  */
1034 
1035 struct amdgpu_bo_list {
1036 	struct mutex lock;
1037 	struct amdgpu_bo *gds_obj;
1038 	struct amdgpu_bo *gws_obj;
1039 	struct amdgpu_bo *oa_obj;
1040 	unsigned first_userptr;
1041 	unsigned num_entries;
1042 	struct amdgpu_bo_list_entry *array;
1043 };
1044 
1045 struct amdgpu_bo_list *
1046 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1047 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
1048 			     struct list_head *validated);
1049 void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1050 void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1051 
1052 /*
1053  * GFX stuff
1054  */
1055 #include "clearstate_defs.h"
1056 
1057 struct amdgpu_rlc_funcs {
1058 	void (*enter_safe_mode)(struct amdgpu_device *adev);
1059 	void (*exit_safe_mode)(struct amdgpu_device *adev);
1060 };
1061 
1062 struct amdgpu_rlc {
1063 	/* for power gating */
1064 	struct amdgpu_bo	*save_restore_obj;
1065 	uint64_t		save_restore_gpu_addr;
1066 	volatile uint32_t	*sr_ptr;
1067 	const u32               *reg_list;
1068 	u32                     reg_list_size;
1069 	/* for clear state */
1070 	struct amdgpu_bo	*clear_state_obj;
1071 	uint64_t		clear_state_gpu_addr;
1072 	volatile uint32_t	*cs_ptr;
1073 	const struct cs_section_def   *cs_data;
1074 	u32                     clear_state_size;
1075 	/* for cp tables */
1076 	struct amdgpu_bo	*cp_table_obj;
1077 	uint64_t		cp_table_gpu_addr;
1078 	volatile uint32_t	*cp_table_ptr;
1079 	u32                     cp_table_size;
1080 
1081 	/* safe mode for updating CG/PG state */
1082 	bool in_safe_mode;
1083 	const struct amdgpu_rlc_funcs *funcs;
1084 
1085 	/* for firmware data */
1086 	u32 save_and_restore_offset;
1087 	u32 clear_state_descriptor_offset;
1088 	u32 avail_scratch_ram_locations;
1089 	u32 reg_restore_list_size;
1090 	u32 reg_list_format_start;
1091 	u32 reg_list_format_separate_start;
1092 	u32 starting_offsets_start;
1093 	u32 reg_list_format_size_bytes;
1094 	u32 reg_list_size_bytes;
1095 
1096 	u32 *register_list_format;
1097 	u32 *register_restore;
1098 };
1099 
1100 struct amdgpu_mec {
1101 	struct amdgpu_bo	*hpd_eop_obj;
1102 	u64			hpd_eop_gpu_addr;
1103 	u32 num_pipe;
1104 	u32 num_mec;
1105 	u32 num_queue;
1106 };
1107 
1108 /*
1109  * GPU scratch registers structures, functions & helpers
1110  */
1111 struct amdgpu_scratch {
1112 	unsigned		num_reg;
1113 	uint32_t                reg_base;
1114 	bool			free[32];
1115 	uint32_t		reg[32];
1116 };
1117 
1118 /*
1119  * GFX configurations
1120  */
1121 struct amdgpu_gca_config {
1122 	unsigned max_shader_engines;
1123 	unsigned max_tile_pipes;
1124 	unsigned max_cu_per_sh;
1125 	unsigned max_sh_per_se;
1126 	unsigned max_backends_per_se;
1127 	unsigned max_texture_channel_caches;
1128 	unsigned max_gprs;
1129 	unsigned max_gs_threads;
1130 	unsigned max_hw_contexts;
1131 	unsigned sc_prim_fifo_size_frontend;
1132 	unsigned sc_prim_fifo_size_backend;
1133 	unsigned sc_hiz_tile_fifo_size;
1134 	unsigned sc_earlyz_tile_fifo_size;
1135 
1136 	unsigned num_tile_pipes;
1137 	unsigned backend_enable_mask;
1138 	unsigned mem_max_burst_length_bytes;
1139 	unsigned mem_row_size_in_kb;
1140 	unsigned shader_engine_tile_size;
1141 	unsigned num_gpus;
1142 	unsigned multi_gpu_tile_size;
1143 	unsigned mc_arb_ramcfg;
1144 	unsigned gb_addr_config;
1145 	unsigned num_rbs;
1146 
1147 	uint32_t tile_mode_array[32];
1148 	uint32_t macrotile_mode_array[16];
1149 };
1150 
1151 struct amdgpu_cu_info {
1152 	uint32_t number; /* total active CU number */
1153 	uint32_t ao_cu_mask;
1154 	uint32_t bitmap[4][4];
1155 };
1156 
1157 struct amdgpu_gfx_funcs {
1158 	/* get the gpu clock counter */
1159 	uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1160 	void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
1161 };
1162 
1163 struct amdgpu_gfx {
1164 	struct mutex			gpu_clock_mutex;
1165 	struct amdgpu_gca_config	config;
1166 	struct amdgpu_rlc		rlc;
1167 	struct amdgpu_mec		mec;
1168 	struct amdgpu_scratch		scratch;
1169 	const struct firmware		*me_fw;	/* ME firmware */
1170 	uint32_t			me_fw_version;
1171 	const struct firmware		*pfp_fw; /* PFP firmware */
1172 	uint32_t			pfp_fw_version;
1173 	const struct firmware		*ce_fw;	/* CE firmware */
1174 	uint32_t			ce_fw_version;
1175 	const struct firmware		*rlc_fw; /* RLC firmware */
1176 	uint32_t			rlc_fw_version;
1177 	const struct firmware		*mec_fw; /* MEC firmware */
1178 	uint32_t			mec_fw_version;
1179 	const struct firmware		*mec2_fw; /* MEC2 firmware */
1180 	uint32_t			mec2_fw_version;
1181 	uint32_t			me_feature_version;
1182 	uint32_t			ce_feature_version;
1183 	uint32_t			pfp_feature_version;
1184 	uint32_t			rlc_feature_version;
1185 	uint32_t			mec_feature_version;
1186 	uint32_t			mec2_feature_version;
1187 	struct amdgpu_ring		gfx_ring[AMDGPU_MAX_GFX_RINGS];
1188 	unsigned			num_gfx_rings;
1189 	struct amdgpu_ring		compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1190 	unsigned			num_compute_rings;
1191 	struct amdgpu_irq_src		eop_irq;
1192 	struct amdgpu_irq_src		priv_reg_irq;
1193 	struct amdgpu_irq_src		priv_inst_irq;
1194 	/* gfx status */
1195 	uint32_t			gfx_current_status;
1196 	/* ce ram size*/
1197 	unsigned			ce_ram_size;
1198 	struct amdgpu_cu_info		cu_info;
1199 	const struct amdgpu_gfx_funcs	*funcs;
1200 };
1201 
1202 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
1203 		  unsigned size, struct amdgpu_ib *ib);
1204 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
1205 		    struct fence *f);
1206 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
1207 		       struct amdgpu_ib *ib, struct fence *last_vm_update,
1208 		       struct amdgpu_job *job, struct fence **f);
1209 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1210 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1211 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1212 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1213 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
1214 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
1215 void amdgpu_ring_commit(struct amdgpu_ring *ring);
1216 void amdgpu_ring_undo(struct amdgpu_ring *ring);
1217 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1218 		     unsigned ring_size, u32 nop, u32 align_mask,
1219 		     struct amdgpu_irq_src *irq_src, unsigned irq_type,
1220 		     enum amdgpu_ring_type ring_type);
1221 void amdgpu_ring_fini(struct amdgpu_ring *ring);
1222 
1223 /*
1224  * CS.
1225  */
1226 struct amdgpu_cs_chunk {
1227 	uint32_t		chunk_id;
1228 	uint32_t		length_dw;
1229 	void			*kdata;
1230 };
1231 
1232 struct amdgpu_cs_parser {
1233 	struct amdgpu_device	*adev;
1234 	struct drm_file		*filp;
1235 	struct amdgpu_ctx	*ctx;
1236 
1237 	/* chunks */
1238 	unsigned		nchunks;
1239 	struct amdgpu_cs_chunk	*chunks;
1240 
1241 	/* scheduler job object */
1242 	struct amdgpu_job	*job;
1243 
1244 	/* buffer objects */
1245 	struct ww_acquire_ctx		ticket;
1246 	struct amdgpu_bo_list		*bo_list;
1247 	struct amdgpu_bo_list_entry	vm_pd;
1248 	struct list_head		validated;
1249 	struct fence			*fence;
1250 	uint64_t			bytes_moved_threshold;
1251 	uint64_t			bytes_moved;
1252 
1253 	/* user fence */
1254 	struct amdgpu_bo_list_entry	uf_entry;
1255 };
1256 
1257 struct amdgpu_job {
1258 	struct amd_sched_job    base;
1259 	struct amdgpu_device	*adev;
1260 	struct amdgpu_vm	*vm;
1261 	struct amdgpu_ring	*ring;
1262 	struct amdgpu_sync	sync;
1263 	struct amdgpu_ib	*ibs;
1264 	struct fence		*fence; /* the hw fence */
1265 	uint32_t		num_ibs;
1266 	void			*owner;
1267 	uint64_t		ctx;
1268 	bool                    vm_needs_flush;
1269 	unsigned		vm_id;
1270 	uint64_t		vm_pd_addr;
1271 	uint32_t		gds_base, gds_size;
1272 	uint32_t		gws_base, gws_size;
1273 	uint32_t		oa_base, oa_size;
1274 
1275 	/* user fence handling */
1276 	uint64_t		uf_addr;
1277 	uint64_t		uf_sequence;
1278 
1279 };
1280 #define to_amdgpu_job(sched_job)		\
1281 		container_of((sched_job), struct amdgpu_job, base)
1282 
1283 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1284 				      uint32_t ib_idx, int idx)
1285 {
1286 	return p->job->ibs[ib_idx].ptr[idx];
1287 }
1288 
1289 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1290 				       uint32_t ib_idx, int idx,
1291 				       uint32_t value)
1292 {
1293 	p->job->ibs[ib_idx].ptr[idx] = value;
1294 }
1295 
1296 /*
1297  * Writeback
1298  */
1299 #define AMDGPU_MAX_WB 1024	/* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1300 
1301 struct amdgpu_wb {
1302 	struct amdgpu_bo	*wb_obj;
1303 	volatile uint32_t	*wb;
1304 	uint64_t		gpu_addr;
1305 	u32			num_wb;	/* Number of wb slots actually reserved for amdgpu. */
1306 	unsigned long		used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1307 };
1308 
1309 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1310 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1311 
1312 
1313 
1314 enum amdgpu_int_thermal_type {
1315 	THERMAL_TYPE_NONE,
1316 	THERMAL_TYPE_EXTERNAL,
1317 	THERMAL_TYPE_EXTERNAL_GPIO,
1318 	THERMAL_TYPE_RV6XX,
1319 	THERMAL_TYPE_RV770,
1320 	THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1321 	THERMAL_TYPE_EVERGREEN,
1322 	THERMAL_TYPE_SUMO,
1323 	THERMAL_TYPE_NI,
1324 	THERMAL_TYPE_SI,
1325 	THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1326 	THERMAL_TYPE_CI,
1327 	THERMAL_TYPE_KV,
1328 };
1329 
1330 enum amdgpu_dpm_auto_throttle_src {
1331 	AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1332 	AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1333 };
1334 
1335 enum amdgpu_dpm_event_src {
1336 	AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1337 	AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1338 	AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1339 	AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1340 	AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1341 };
1342 
1343 #define AMDGPU_MAX_VCE_LEVELS 6
1344 
1345 enum amdgpu_vce_level {
1346 	AMDGPU_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
1347 	AMDGPU_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
1348 	AMDGPU_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
1349 	AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1350 	AMDGPU_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
1351 	AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1352 };
1353 
1354 struct amdgpu_ps {
1355 	u32 caps; /* vbios flags */
1356 	u32 class; /* vbios flags */
1357 	u32 class2; /* vbios flags */
1358 	/* UVD clocks */
1359 	u32 vclk;
1360 	u32 dclk;
1361 	/* VCE clocks */
1362 	u32 evclk;
1363 	u32 ecclk;
1364 	bool vce_active;
1365 	enum amdgpu_vce_level vce_level;
1366 	/* asic priv */
1367 	void *ps_priv;
1368 };
1369 
1370 struct amdgpu_dpm_thermal {
1371 	/* thermal interrupt work */
1372 	struct work_struct work;
1373 	/* low temperature threshold */
1374 	int                min_temp;
1375 	/* high temperature threshold */
1376 	int                max_temp;
1377 	/* was last interrupt low to high or high to low */
1378 	bool               high_to_low;
1379 	/* interrupt source */
1380 	struct amdgpu_irq_src	irq;
1381 };
1382 
1383 enum amdgpu_clk_action
1384 {
1385 	AMDGPU_SCLK_UP = 1,
1386 	AMDGPU_SCLK_DOWN
1387 };
1388 
1389 struct amdgpu_blacklist_clocks
1390 {
1391 	u32 sclk;
1392 	u32 mclk;
1393 	enum amdgpu_clk_action action;
1394 };
1395 
1396 struct amdgpu_clock_and_voltage_limits {
1397 	u32 sclk;
1398 	u32 mclk;
1399 	u16 vddc;
1400 	u16 vddci;
1401 };
1402 
1403 struct amdgpu_clock_array {
1404 	u32 count;
1405 	u32 *values;
1406 };
1407 
1408 struct amdgpu_clock_voltage_dependency_entry {
1409 	u32 clk;
1410 	u16 v;
1411 };
1412 
1413 struct amdgpu_clock_voltage_dependency_table {
1414 	u32 count;
1415 	struct amdgpu_clock_voltage_dependency_entry *entries;
1416 };
1417 
1418 union amdgpu_cac_leakage_entry {
1419 	struct {
1420 		u16 vddc;
1421 		u32 leakage;
1422 	};
1423 	struct {
1424 		u16 vddc1;
1425 		u16 vddc2;
1426 		u16 vddc3;
1427 	};
1428 };
1429 
1430 struct amdgpu_cac_leakage_table {
1431 	u32 count;
1432 	union amdgpu_cac_leakage_entry *entries;
1433 };
1434 
1435 struct amdgpu_phase_shedding_limits_entry {
1436 	u16 voltage;
1437 	u32 sclk;
1438 	u32 mclk;
1439 };
1440 
1441 struct amdgpu_phase_shedding_limits_table {
1442 	u32 count;
1443 	struct amdgpu_phase_shedding_limits_entry *entries;
1444 };
1445 
1446 struct amdgpu_uvd_clock_voltage_dependency_entry {
1447 	u32 vclk;
1448 	u32 dclk;
1449 	u16 v;
1450 };
1451 
1452 struct amdgpu_uvd_clock_voltage_dependency_table {
1453 	u8 count;
1454 	struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1455 };
1456 
1457 struct amdgpu_vce_clock_voltage_dependency_entry {
1458 	u32 ecclk;
1459 	u32 evclk;
1460 	u16 v;
1461 };
1462 
1463 struct amdgpu_vce_clock_voltage_dependency_table {
1464 	u8 count;
1465 	struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1466 };
1467 
1468 struct amdgpu_ppm_table {
1469 	u8 ppm_design;
1470 	u16 cpu_core_number;
1471 	u32 platform_tdp;
1472 	u32 small_ac_platform_tdp;
1473 	u32 platform_tdc;
1474 	u32 small_ac_platform_tdc;
1475 	u32 apu_tdp;
1476 	u32 dgpu_tdp;
1477 	u32 dgpu_ulv_power;
1478 	u32 tj_max;
1479 };
1480 
1481 struct amdgpu_cac_tdp_table {
1482 	u16 tdp;
1483 	u16 configurable_tdp;
1484 	u16 tdc;
1485 	u16 battery_power_limit;
1486 	u16 small_power_limit;
1487 	u16 low_cac_leakage;
1488 	u16 high_cac_leakage;
1489 	u16 maximum_power_delivery_limit;
1490 };
1491 
1492 struct amdgpu_dpm_dynamic_state {
1493 	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1494 	struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1495 	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1496 	struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1497 	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1498 	struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1499 	struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1500 	struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1501 	struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1502 	struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1503 	struct amdgpu_clock_array valid_sclk_values;
1504 	struct amdgpu_clock_array valid_mclk_values;
1505 	struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1506 	struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1507 	u32 mclk_sclk_ratio;
1508 	u32 sclk_mclk_delta;
1509 	u16 vddc_vddci_delta;
1510 	u16 min_vddc_for_pcie_gen2;
1511 	struct amdgpu_cac_leakage_table cac_leakage_table;
1512 	struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1513 	struct amdgpu_ppm_table *ppm_table;
1514 	struct amdgpu_cac_tdp_table *cac_tdp_table;
1515 };
1516 
1517 struct amdgpu_dpm_fan {
1518 	u16 t_min;
1519 	u16 t_med;
1520 	u16 t_high;
1521 	u16 pwm_min;
1522 	u16 pwm_med;
1523 	u16 pwm_high;
1524 	u8 t_hyst;
1525 	u32 cycle_delay;
1526 	u16 t_max;
1527 	u8 control_mode;
1528 	u16 default_max_fan_pwm;
1529 	u16 default_fan_output_sensitivity;
1530 	u16 fan_output_sensitivity;
1531 	bool ucode_fan_control;
1532 };
1533 
1534 enum amdgpu_pcie_gen {
1535 	AMDGPU_PCIE_GEN1 = 0,
1536 	AMDGPU_PCIE_GEN2 = 1,
1537 	AMDGPU_PCIE_GEN3 = 2,
1538 	AMDGPU_PCIE_GEN_INVALID = 0xffff
1539 };
1540 
1541 enum amdgpu_dpm_forced_level {
1542 	AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1543 	AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1544 	AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1545 	AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
1546 };
1547 
1548 struct amdgpu_vce_state {
1549 	/* vce clocks */
1550 	u32 evclk;
1551 	u32 ecclk;
1552 	/* gpu clocks */
1553 	u32 sclk;
1554 	u32 mclk;
1555 	u8 clk_idx;
1556 	u8 pstate;
1557 };
1558 
1559 struct amdgpu_dpm_funcs {
1560 	int (*get_temperature)(struct amdgpu_device *adev);
1561 	int (*pre_set_power_state)(struct amdgpu_device *adev);
1562 	int (*set_power_state)(struct amdgpu_device *adev);
1563 	void (*post_set_power_state)(struct amdgpu_device *adev);
1564 	void (*display_configuration_changed)(struct amdgpu_device *adev);
1565 	u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1566 	u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1567 	void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1568 	void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1569 	int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1570 	bool (*vblank_too_short)(struct amdgpu_device *adev);
1571 	void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
1572 	void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
1573 	void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1574 	void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1575 	u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1576 	int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1577 	int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1578 	int (*force_clock_level)(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t mask);
1579 	int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf);
1580 	int (*get_sclk_od)(struct amdgpu_device *adev);
1581 	int (*set_sclk_od)(struct amdgpu_device *adev, uint32_t value);
1582 	int (*get_mclk_od)(struct amdgpu_device *adev);
1583 	int (*set_mclk_od)(struct amdgpu_device *adev, uint32_t value);
1584 };
1585 
1586 struct amdgpu_dpm {
1587 	struct amdgpu_ps        *ps;
1588 	/* number of valid power states */
1589 	int                     num_ps;
1590 	/* current power state that is active */
1591 	struct amdgpu_ps        *current_ps;
1592 	/* requested power state */
1593 	struct amdgpu_ps        *requested_ps;
1594 	/* boot up power state */
1595 	struct amdgpu_ps        *boot_ps;
1596 	/* default uvd power state */
1597 	struct amdgpu_ps        *uvd_ps;
1598 	/* vce requirements */
1599 	struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1600 	enum amdgpu_vce_level vce_level;
1601 	enum amd_pm_state_type state;
1602 	enum amd_pm_state_type user_state;
1603 	u32                     platform_caps;
1604 	u32                     voltage_response_time;
1605 	u32                     backbias_response_time;
1606 	void                    *priv;
1607 	u32			new_active_crtcs;
1608 	int			new_active_crtc_count;
1609 	u32			current_active_crtcs;
1610 	int			current_active_crtc_count;
1611 	struct amdgpu_dpm_dynamic_state dyn_state;
1612 	struct amdgpu_dpm_fan fan;
1613 	u32 tdp_limit;
1614 	u32 near_tdp_limit;
1615 	u32 near_tdp_limit_adjusted;
1616 	u32 sq_ramping_threshold;
1617 	u32 cac_leakage;
1618 	u16 tdp_od_limit;
1619 	u32 tdp_adjustment;
1620 	u16 load_line_slope;
1621 	bool power_control;
1622 	bool ac_power;
1623 	/* special states active */
1624 	bool                    thermal_active;
1625 	bool                    uvd_active;
1626 	bool                    vce_active;
1627 	/* thermal handling */
1628 	struct amdgpu_dpm_thermal thermal;
1629 	/* forced levels */
1630 	enum amdgpu_dpm_forced_level forced_level;
1631 };
1632 
1633 struct amdgpu_pm {
1634 	struct mutex		mutex;
1635 	u32                     current_sclk;
1636 	u32                     current_mclk;
1637 	u32                     default_sclk;
1638 	u32                     default_mclk;
1639 	struct amdgpu_i2c_chan *i2c_bus;
1640 	/* internal thermal controller on rv6xx+ */
1641 	enum amdgpu_int_thermal_type int_thermal_type;
1642 	struct device	        *int_hwmon_dev;
1643 	/* fan control parameters */
1644 	bool                    no_fan;
1645 	u8                      fan_pulses_per_revolution;
1646 	u8                      fan_min_rpm;
1647 	u8                      fan_max_rpm;
1648 	/* dpm */
1649 	bool                    dpm_enabled;
1650 	bool                    sysfs_initialized;
1651 	struct amdgpu_dpm       dpm;
1652 	const struct firmware	*fw;	/* SMC firmware */
1653 	uint32_t                fw_version;
1654 	const struct amdgpu_dpm_funcs *funcs;
1655 	uint32_t                pcie_gen_mask;
1656 	uint32_t                pcie_mlw_mask;
1657 	struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
1658 };
1659 
1660 void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1661 
1662 /*
1663  * UVD
1664  */
1665 #define AMDGPU_DEFAULT_UVD_HANDLES	10
1666 #define AMDGPU_MAX_UVD_HANDLES		40
1667 #define AMDGPU_UVD_STACK_SIZE		(200*1024)
1668 #define AMDGPU_UVD_HEAP_SIZE		(256*1024)
1669 #define AMDGPU_UVD_SESSION_SIZE		(50*1024)
1670 #define AMDGPU_UVD_FIRMWARE_OFFSET	256
1671 
1672 struct amdgpu_uvd {
1673 	struct amdgpu_bo	*vcpu_bo;
1674 	void			*cpu_addr;
1675 	uint64_t		gpu_addr;
1676 	unsigned		fw_version;
1677 	void			*saved_bo;
1678 	unsigned		max_handles;
1679 	atomic_t		handles[AMDGPU_MAX_UVD_HANDLES];
1680 	struct drm_file		*filp[AMDGPU_MAX_UVD_HANDLES];
1681 	struct delayed_work	idle_work;
1682 	const struct firmware	*fw;	/* UVD firmware */
1683 	struct amdgpu_ring	ring;
1684 	struct amdgpu_irq_src	irq;
1685 	bool			address_64_bit;
1686 	bool			use_ctx_buf;
1687 	struct amd_sched_entity entity;
1688 };
1689 
1690 /*
1691  * VCE
1692  */
1693 #define AMDGPU_MAX_VCE_HANDLES	16
1694 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1695 
1696 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1697 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1698 
1699 struct amdgpu_vce {
1700 	struct amdgpu_bo	*vcpu_bo;
1701 	uint64_t		gpu_addr;
1702 	unsigned		fw_version;
1703 	unsigned		fb_version;
1704 	atomic_t		handles[AMDGPU_MAX_VCE_HANDLES];
1705 	struct drm_file		*filp[AMDGPU_MAX_VCE_HANDLES];
1706 	uint32_t		img_size[AMDGPU_MAX_VCE_HANDLES];
1707 	struct delayed_work	idle_work;
1708 	struct mutex		idle_mutex;
1709 	const struct firmware	*fw;	/* VCE firmware */
1710 	struct amdgpu_ring	ring[AMDGPU_MAX_VCE_RINGS];
1711 	struct amdgpu_irq_src	irq;
1712 	unsigned		harvest_config;
1713 	struct amd_sched_entity	entity;
1714 };
1715 
1716 /*
1717  * SDMA
1718  */
1719 struct amdgpu_sdma_instance {
1720 	/* SDMA firmware */
1721 	const struct firmware	*fw;
1722 	uint32_t		fw_version;
1723 	uint32_t		feature_version;
1724 
1725 	struct amdgpu_ring	ring;
1726 	bool			burst_nop;
1727 };
1728 
1729 struct amdgpu_sdma {
1730 	struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1731 	struct amdgpu_irq_src	trap_irq;
1732 	struct amdgpu_irq_src	illegal_inst_irq;
1733 	int			num_instances;
1734 };
1735 
1736 /*
1737  * Firmware
1738  */
1739 struct amdgpu_firmware {
1740 	struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1741 	bool smu_load;
1742 	struct amdgpu_bo *fw_buf;
1743 	unsigned int fw_size;
1744 };
1745 
1746 /*
1747  * Benchmarking
1748  */
1749 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1750 
1751 
1752 /*
1753  * Testing
1754  */
1755 void amdgpu_test_moves(struct amdgpu_device *adev);
1756 void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1757 			   struct amdgpu_ring *cpA,
1758 			   struct amdgpu_ring *cpB);
1759 void amdgpu_test_syncing(struct amdgpu_device *adev);
1760 
1761 /*
1762  * MMU Notifier
1763  */
1764 #if defined(CONFIG_MMU_NOTIFIER)
1765 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1766 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1767 #else
1768 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1769 {
1770 	return -ENODEV;
1771 }
1772 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1773 #endif
1774 
1775 /*
1776  * Debugfs
1777  */
1778 struct amdgpu_debugfs {
1779 	const struct drm_info_list	*files;
1780 	unsigned		num_files;
1781 };
1782 
1783 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1784 			     const struct drm_info_list *files,
1785 			     unsigned nfiles);
1786 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1787 
1788 #if defined(CONFIG_DEBUG_FS)
1789 int amdgpu_debugfs_init(struct drm_minor *minor);
1790 void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1791 #endif
1792 
1793 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1794 
1795 /*
1796  * amdgpu smumgr functions
1797  */
1798 struct amdgpu_smumgr_funcs {
1799 	int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1800 	int (*request_smu_load_fw)(struct amdgpu_device *adev);
1801 	int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1802 };
1803 
1804 /*
1805  * amdgpu smumgr
1806  */
1807 struct amdgpu_smumgr {
1808 	struct amdgpu_bo *toc_buf;
1809 	struct amdgpu_bo *smu_buf;
1810 	/* asic priv smu data */
1811 	void *priv;
1812 	spinlock_t smu_lock;
1813 	/* smumgr functions */
1814 	const struct amdgpu_smumgr_funcs *smumgr_funcs;
1815 	/* ucode loading complete flag */
1816 	uint32_t fw_flags;
1817 };
1818 
1819 /*
1820  * ASIC specific register table accessible by UMD
1821  */
1822 struct amdgpu_allowed_register_entry {
1823 	uint32_t reg_offset;
1824 	bool untouched;
1825 	bool grbm_indexed;
1826 };
1827 
1828 /*
1829  * ASIC specific functions.
1830  */
1831 struct amdgpu_asic_funcs {
1832 	bool (*read_disabled_bios)(struct amdgpu_device *adev);
1833 	bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1834 				   u8 *bios, u32 length_bytes);
1835 	int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1836 			     u32 sh_num, u32 reg_offset, u32 *value);
1837 	void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1838 	int (*reset)(struct amdgpu_device *adev);
1839 	/* get the reference clock */
1840 	u32 (*get_xclk)(struct amdgpu_device *adev);
1841 	/* MM block clocks */
1842 	int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1843 	int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1844 	/* query virtual capabilities */
1845 	u32 (*get_virtual_caps)(struct amdgpu_device *adev);
1846 };
1847 
1848 /*
1849  * IOCTL.
1850  */
1851 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1852 			    struct drm_file *filp);
1853 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1854 				struct drm_file *filp);
1855 
1856 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1857 			  struct drm_file *filp);
1858 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1859 			struct drm_file *filp);
1860 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1861 			  struct drm_file *filp);
1862 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1863 			      struct drm_file *filp);
1864 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1865 			  struct drm_file *filp);
1866 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1867 			struct drm_file *filp);
1868 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1869 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1870 
1871 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1872 				struct drm_file *filp);
1873 
1874 /* VRAM scratch page for HDP bug, default vram page */
1875 struct amdgpu_vram_scratch {
1876 	struct amdgpu_bo		*robj;
1877 	volatile uint32_t		*ptr;
1878 	u64				gpu_addr;
1879 };
1880 
1881 /*
1882  * ACPI
1883  */
1884 struct amdgpu_atif_notification_cfg {
1885 	bool enabled;
1886 	int command_code;
1887 };
1888 
1889 struct amdgpu_atif_notifications {
1890 	bool display_switch;
1891 	bool expansion_mode_change;
1892 	bool thermal_state;
1893 	bool forced_power_state;
1894 	bool system_power_state;
1895 	bool display_conf_change;
1896 	bool px_gfx_switch;
1897 	bool brightness_change;
1898 	bool dgpu_display_event;
1899 };
1900 
1901 struct amdgpu_atif_functions {
1902 	bool system_params;
1903 	bool sbios_requests;
1904 	bool select_active_disp;
1905 	bool lid_state;
1906 	bool get_tv_standard;
1907 	bool set_tv_standard;
1908 	bool get_panel_expansion_mode;
1909 	bool set_panel_expansion_mode;
1910 	bool temperature_change;
1911 	bool graphics_device_types;
1912 };
1913 
1914 struct amdgpu_atif {
1915 	struct amdgpu_atif_notifications notifications;
1916 	struct amdgpu_atif_functions functions;
1917 	struct amdgpu_atif_notification_cfg notification_cfg;
1918 	struct amdgpu_encoder *encoder_for_bl;
1919 };
1920 
1921 struct amdgpu_atcs_functions {
1922 	bool get_ext_state;
1923 	bool pcie_perf_req;
1924 	bool pcie_dev_rdy;
1925 	bool pcie_bus_width;
1926 };
1927 
1928 struct amdgpu_atcs {
1929 	struct amdgpu_atcs_functions functions;
1930 };
1931 
1932 /*
1933  * CGS
1934  */
1935 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1936 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
1937 
1938 
1939 /* GPU virtualization */
1940 #define AMDGPU_VIRT_CAPS_SRIOV_EN       (1 << 0)
1941 #define AMDGPU_VIRT_CAPS_IS_VF          (1 << 1)
1942 struct amdgpu_virtualization {
1943 	bool supports_sr_iov;
1944 	bool is_virtual;
1945 	u32 caps;
1946 };
1947 
1948 /*
1949  * Core structure, functions and helpers.
1950  */
1951 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1952 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1953 
1954 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1955 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1956 
1957 struct amdgpu_ip_block_status {
1958 	bool valid;
1959 	bool sw;
1960 	bool hw;
1961 };
1962 
1963 struct amdgpu_device {
1964 	struct device			*dev;
1965 	struct drm_device		*ddev;
1966 	struct pci_dev			*pdev;
1967 
1968 #ifdef CONFIG_DRM_AMD_ACP
1969 	struct amdgpu_acp		acp;
1970 #endif
1971 
1972 	/* ASIC */
1973 	enum amd_asic_type		asic_type;
1974 	uint32_t			family;
1975 	uint32_t			rev_id;
1976 	uint32_t			external_rev_id;
1977 	unsigned long			flags;
1978 	int				usec_timeout;
1979 	const struct amdgpu_asic_funcs	*asic_funcs;
1980 	bool				shutdown;
1981 	bool				need_dma32;
1982 	bool				accel_working;
1983 	struct work_struct		reset_work;
1984 	struct notifier_block		acpi_nb;
1985 	struct amdgpu_i2c_chan		*i2c_bus[AMDGPU_MAX_I2C_BUS];
1986 	struct amdgpu_debugfs		debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1987 	unsigned			debugfs_count;
1988 #if defined(CONFIG_DEBUG_FS)
1989 	struct dentry			*debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1990 #endif
1991 	struct amdgpu_atif		atif;
1992 	struct amdgpu_atcs		atcs;
1993 	struct mutex			srbm_mutex;
1994 	/* GRBM index mutex. Protects concurrent access to GRBM index */
1995 	struct mutex                    grbm_idx_mutex;
1996 	struct dev_pm_domain		vga_pm_domain;
1997 	bool				have_disp_power_ref;
1998 
1999 	/* BIOS */
2000 	uint8_t				*bios;
2001 	bool				is_atom_bios;
2002 	struct amdgpu_bo		*stollen_vga_memory;
2003 	uint32_t			bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
2004 
2005 	/* Register/doorbell mmio */
2006 	resource_size_t			rmmio_base;
2007 	resource_size_t			rmmio_size;
2008 	void __iomem			*rmmio;
2009 	/* protects concurrent MM_INDEX/DATA based register access */
2010 	spinlock_t mmio_idx_lock;
2011 	/* protects concurrent SMC based register access */
2012 	spinlock_t smc_idx_lock;
2013 	amdgpu_rreg_t			smc_rreg;
2014 	amdgpu_wreg_t			smc_wreg;
2015 	/* protects concurrent PCIE register access */
2016 	spinlock_t pcie_idx_lock;
2017 	amdgpu_rreg_t			pcie_rreg;
2018 	amdgpu_wreg_t			pcie_wreg;
2019 	/* protects concurrent UVD register access */
2020 	spinlock_t uvd_ctx_idx_lock;
2021 	amdgpu_rreg_t			uvd_ctx_rreg;
2022 	amdgpu_wreg_t			uvd_ctx_wreg;
2023 	/* protects concurrent DIDT register access */
2024 	spinlock_t didt_idx_lock;
2025 	amdgpu_rreg_t			didt_rreg;
2026 	amdgpu_wreg_t			didt_wreg;
2027 	/* protects concurrent gc_cac register access */
2028 	spinlock_t gc_cac_idx_lock;
2029 	amdgpu_rreg_t			gc_cac_rreg;
2030 	amdgpu_wreg_t			gc_cac_wreg;
2031 	/* protects concurrent ENDPOINT (audio) register access */
2032 	spinlock_t audio_endpt_idx_lock;
2033 	amdgpu_block_rreg_t		audio_endpt_rreg;
2034 	amdgpu_block_wreg_t		audio_endpt_wreg;
2035 	void __iomem                    *rio_mem;
2036 	resource_size_t			rio_mem_size;
2037 	struct amdgpu_doorbell		doorbell;
2038 
2039 	/* clock/pll info */
2040 	struct amdgpu_clock            clock;
2041 
2042 	/* MC */
2043 	struct amdgpu_mc		mc;
2044 	struct amdgpu_gart		gart;
2045 	struct amdgpu_dummy_page	dummy_page;
2046 	struct amdgpu_vm_manager	vm_manager;
2047 
2048 	/* memory management */
2049 	struct amdgpu_mman		mman;
2050 	struct amdgpu_vram_scratch	vram_scratch;
2051 	struct amdgpu_wb		wb;
2052 	atomic64_t			vram_usage;
2053 	atomic64_t			vram_vis_usage;
2054 	atomic64_t			gtt_usage;
2055 	atomic64_t			num_bytes_moved;
2056 	atomic64_t			num_evictions;
2057 	atomic_t			gpu_reset_counter;
2058 
2059 	/* display */
2060 	struct amdgpu_mode_info		mode_info;
2061 	struct work_struct		hotplug_work;
2062 	struct amdgpu_irq_src		crtc_irq;
2063 	struct amdgpu_irq_src		pageflip_irq;
2064 	struct amdgpu_irq_src		hpd_irq;
2065 
2066 	/* rings */
2067 	u64				fence_context;
2068 	unsigned			num_rings;
2069 	struct amdgpu_ring		*rings[AMDGPU_MAX_RINGS];
2070 	bool				ib_pool_ready;
2071 	struct amdgpu_sa_manager	ring_tmp_bo;
2072 
2073 	/* interrupts */
2074 	struct amdgpu_irq		irq;
2075 
2076 	/* powerplay */
2077 	struct amd_powerplay		powerplay;
2078 	bool				pp_enabled;
2079 	bool				pp_force_state_enabled;
2080 
2081 	/* dpm */
2082 	struct amdgpu_pm		pm;
2083 	u32				cg_flags;
2084 	u32				pg_flags;
2085 
2086 	/* amdgpu smumgr */
2087 	struct amdgpu_smumgr smu;
2088 
2089 	/* gfx */
2090 	struct amdgpu_gfx		gfx;
2091 
2092 	/* sdma */
2093 	struct amdgpu_sdma		sdma;
2094 
2095 	/* uvd */
2096 	struct amdgpu_uvd		uvd;
2097 
2098 	/* vce */
2099 	struct amdgpu_vce		vce;
2100 
2101 	/* firmwares */
2102 	struct amdgpu_firmware		firmware;
2103 
2104 	/* GDS */
2105 	struct amdgpu_gds		gds;
2106 
2107 	const struct amdgpu_ip_block_version *ip_blocks;
2108 	int				num_ip_blocks;
2109 	struct amdgpu_ip_block_status	*ip_block_status;
2110 	struct mutex	mn_lock;
2111 	DECLARE_HASHTABLE(mn_hash, 7);
2112 
2113 	/* tracking pinned memory */
2114 	u64 vram_pin_size;
2115 	u64 invisible_pin_size;
2116 	u64 gart_pin_size;
2117 
2118 	/* amdkfd interface */
2119 	struct kfd_dev          *kfd;
2120 
2121 	struct amdgpu_virtualization virtualization;
2122 };
2123 
2124 bool amdgpu_device_is_px(struct drm_device *dev);
2125 int amdgpu_device_init(struct amdgpu_device *adev,
2126 		       struct drm_device *ddev,
2127 		       struct pci_dev *pdev,
2128 		       uint32_t flags);
2129 void amdgpu_device_fini(struct amdgpu_device *adev);
2130 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2131 
2132 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2133 			bool always_indirect);
2134 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2135 		    bool always_indirect);
2136 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2137 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2138 
2139 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2140 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2141 
2142 /*
2143  * Registers read & write functions.
2144  */
2145 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2146 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2147 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2148 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2149 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2150 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2151 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2152 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2153 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2154 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2155 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2156 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2157 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2158 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2159 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2160 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
2161 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
2162 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2163 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2164 #define WREG32_P(reg, val, mask)				\
2165 	do {							\
2166 		uint32_t tmp_ = RREG32(reg);			\
2167 		tmp_ &= (mask);					\
2168 		tmp_ |= ((val) & ~(mask));			\
2169 		WREG32(reg, tmp_);				\
2170 	} while (0)
2171 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2172 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2173 #define WREG32_PLL_P(reg, val, mask)				\
2174 	do {							\
2175 		uint32_t tmp_ = RREG32_PLL(reg);		\
2176 		tmp_ &= (mask);					\
2177 		tmp_ |= ((val) & ~(mask));			\
2178 		WREG32_PLL(reg, tmp_);				\
2179 	} while (0)
2180 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2181 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2182 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2183 
2184 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2185 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2186 
2187 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2188 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2189 
2190 #define REG_SET_FIELD(orig_val, reg, field, field_val)			\
2191 	(((orig_val) & ~REG_FIELD_MASK(reg, field)) |			\
2192 	 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2193 
2194 #define REG_GET_FIELD(value, reg, field)				\
2195 	(((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2196 
2197 /*
2198  * BIOS helpers.
2199  */
2200 #define RBIOS8(i) (adev->bios[i])
2201 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2202 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2203 
2204 /*
2205  * RING helpers.
2206  */
2207 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2208 {
2209 	if (ring->count_dw <= 0)
2210 		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2211 	ring->ring[ring->wptr++] = v;
2212 	ring->wptr &= ring->ptr_mask;
2213 	ring->count_dw--;
2214 }
2215 
2216 static inline struct amdgpu_sdma_instance *
2217 amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
2218 {
2219 	struct amdgpu_device *adev = ring->adev;
2220 	int i;
2221 
2222 	for (i = 0; i < adev->sdma.num_instances; i++)
2223 		if (&adev->sdma.instance[i].ring == ring)
2224 			break;
2225 
2226 	if (i < AMDGPU_MAX_SDMA_INSTANCES)
2227 		return &adev->sdma.instance[i];
2228 	else
2229 		return NULL;
2230 }
2231 
2232 /*
2233  * ASICs macro.
2234  */
2235 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2236 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2237 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2238 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2239 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2240 #define amdgpu_asic_get_virtual_caps(adev) ((adev)->asic_funcs->get_virtual_caps((adev)))
2241 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2242 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
2243 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2244 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2245 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2246 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2247 #define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags)))
2248 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2249 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2250 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2251 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
2252 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2253 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2254 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2255 #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
2256 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
2257 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2258 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2259 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2260 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2261 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
2262 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
2263 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
2264 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
2265 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2266 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2267 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2268 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2269 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2270 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2271 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2272 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2273 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2274 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2275 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2276 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2277 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2278 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
2279 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2280 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2281 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2282 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2283 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2284 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib),  (s), (d), (b))
2285 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
2286 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2287 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2288 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2289 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2290 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2291 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2292 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2293 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
2294 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
2295 
2296 #define amdgpu_dpm_get_temperature(adev) \
2297 	((adev)->pp_enabled ?						\
2298 	      (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
2299 	      (adev)->pm.funcs->get_temperature((adev)))
2300 
2301 #define amdgpu_dpm_set_fan_control_mode(adev, m) \
2302 	((adev)->pp_enabled ?						\
2303 	      (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
2304 	      (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
2305 
2306 #define amdgpu_dpm_get_fan_control_mode(adev) \
2307 	((adev)->pp_enabled ?						\
2308 	      (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
2309 	      (adev)->pm.funcs->get_fan_control_mode((adev)))
2310 
2311 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \
2312 	((adev)->pp_enabled ?						\
2313 	      (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2314 	      (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
2315 
2316 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \
2317 	((adev)->pp_enabled ?						\
2318 	      (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2319 	      (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
2320 
2321 #define amdgpu_dpm_get_sclk(adev, l) \
2322 	((adev)->pp_enabled ?						\
2323 	      (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
2324 		(adev)->pm.funcs->get_sclk((adev), (l)))
2325 
2326 #define amdgpu_dpm_get_mclk(adev, l)  \
2327 	((adev)->pp_enabled ?						\
2328 	      (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
2329 	      (adev)->pm.funcs->get_mclk((adev), (l)))
2330 
2331 
2332 #define amdgpu_dpm_force_performance_level(adev, l) \
2333 	((adev)->pp_enabled ?						\
2334 	      (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
2335 	      (adev)->pm.funcs->force_performance_level((adev), (l)))
2336 
2337 #define amdgpu_dpm_powergate_uvd(adev, g) \
2338 	((adev)->pp_enabled ?						\
2339 	      (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
2340 	      (adev)->pm.funcs->powergate_uvd((adev), (g)))
2341 
2342 #define amdgpu_dpm_powergate_vce(adev, g) \
2343 	((adev)->pp_enabled ?						\
2344 	      (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
2345 	      (adev)->pm.funcs->powergate_vce((adev), (g)))
2346 
2347 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
2348 	((adev)->pp_enabled ?						\
2349 	      (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
2350 	      (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
2351 
2352 #define amdgpu_dpm_get_current_power_state(adev) \
2353 	(adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
2354 
2355 #define amdgpu_dpm_get_performance_level(adev) \
2356 	(adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
2357 
2358 #define amdgpu_dpm_get_pp_num_states(adev, data) \
2359 	(adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
2360 
2361 #define amdgpu_dpm_get_pp_table(adev, table) \
2362 	(adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
2363 
2364 #define amdgpu_dpm_set_pp_table(adev, buf, size) \
2365 	(adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
2366 
2367 #define amdgpu_dpm_print_clock_levels(adev, type, buf) \
2368 	(adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
2369 
2370 #define amdgpu_dpm_force_clock_level(adev, type, level) \
2371 		(adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
2372 
2373 #define amdgpu_dpm_get_sclk_od(adev) \
2374 	(adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)
2375 
2376 #define amdgpu_dpm_set_sclk_od(adev, value) \
2377 	(adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)
2378 
2379 #define amdgpu_dpm_get_mclk_od(adev) \
2380 	((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
2381 
2382 #define amdgpu_dpm_set_mclk_od(adev, value) \
2383 	((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
2384 
2385 #define amdgpu_dpm_dispatch_task(adev, event_id, input, output)		\
2386 	(adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
2387 
2388 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2389 
2390 /* Common functions */
2391 int amdgpu_gpu_reset(struct amdgpu_device *adev);
2392 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2393 bool amdgpu_card_posted(struct amdgpu_device *adev);
2394 void amdgpu_update_display_priority(struct amdgpu_device *adev);
2395 
2396 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2397 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2398 		       u32 ip_instance, u32 ring,
2399 		       struct amdgpu_ring **out_ring);
2400 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2401 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2402 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
2403 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2404 				     uint32_t flags);
2405 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2406 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
2407 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2408 				  unsigned long end);
2409 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
2410 				       int *last_invalidated);
2411 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2412 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2413 				 struct ttm_mem_reg *mem);
2414 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2415 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2416 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2417 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2418 					     const u32 *registers,
2419 					     const u32 array_size);
2420 
2421 bool amdgpu_device_is_px(struct drm_device *dev);
2422 /* atpx handler */
2423 #if defined(CONFIG_VGA_SWITCHEROO)
2424 void amdgpu_register_atpx_handler(void);
2425 void amdgpu_unregister_atpx_handler(void);
2426 bool amdgpu_has_atpx_dgpu_power_cntl(void);
2427 bool amdgpu_is_atpx_hybrid(void);
2428 #else
2429 static inline void amdgpu_register_atpx_handler(void) {}
2430 static inline void amdgpu_unregister_atpx_handler(void) {}
2431 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2432 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
2433 #endif
2434 
2435 /*
2436  * KMS
2437  */
2438 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2439 extern const int amdgpu_max_kms_ioctl;
2440 
2441 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2442 int amdgpu_driver_unload_kms(struct drm_device *dev);
2443 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2444 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2445 void amdgpu_driver_postclose_kms(struct drm_device *dev,
2446 				 struct drm_file *file_priv);
2447 void amdgpu_driver_preclose_kms(struct drm_device *dev,
2448 				struct drm_file *file_priv);
2449 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2450 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2451 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2452 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2453 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2454 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
2455 				    int *max_error,
2456 				    struct timeval *vblank_time,
2457 				    unsigned flags);
2458 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2459 			     unsigned long arg);
2460 
2461 /*
2462  * functions used by amdgpu_encoder.c
2463  */
2464 struct amdgpu_afmt_acr {
2465 	u32 clock;
2466 
2467 	int n_32khz;
2468 	int cts_32khz;
2469 
2470 	int n_44_1khz;
2471 	int cts_44_1khz;
2472 
2473 	int n_48khz;
2474 	int cts_48khz;
2475 
2476 };
2477 
2478 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2479 
2480 /* amdgpu_acpi.c */
2481 #if defined(CONFIG_ACPI)
2482 int amdgpu_acpi_init(struct amdgpu_device *adev);
2483 void amdgpu_acpi_fini(struct amdgpu_device *adev);
2484 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2485 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2486 						u8 perf_req, bool advertise);
2487 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2488 #else
2489 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2490 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2491 #endif
2492 
2493 struct amdgpu_bo_va_mapping *
2494 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2495 		       uint64_t addr, struct amdgpu_bo **bo);
2496 
2497 #include "amdgpu_object.h"
2498 #endif
2499