1*c103de24SGrant Likely /* 2*c103de24SGrant Likely * Copyright (C) ST-Ericsson SA 2010 3*c103de24SGrant Likely * 4*c103de24SGrant Likely * License Terms: GNU General Public License, version 2 5*c103de24SGrant Likely * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson 6*c103de24SGrant Likely */ 7*c103de24SGrant Likely 8*c103de24SGrant Likely #include <linux/module.h> 9*c103de24SGrant Likely #include <linux/init.h> 10*c103de24SGrant Likely #include <linux/platform_device.h> 11*c103de24SGrant Likely #include <linux/slab.h> 12*c103de24SGrant Likely #include <linux/gpio.h> 13*c103de24SGrant Likely #include <linux/irq.h> 14*c103de24SGrant Likely #include <linux/interrupt.h> 15*c103de24SGrant Likely #include <linux/mfd/stmpe.h> 16*c103de24SGrant Likely 17*c103de24SGrant Likely /* 18*c103de24SGrant Likely * These registers are modified under the irq bus lock and cached to avoid 19*c103de24SGrant Likely * unnecessary writes in bus_sync_unlock. 20*c103de24SGrant Likely */ 21*c103de24SGrant Likely enum { REG_RE, REG_FE, REG_IE }; 22*c103de24SGrant Likely 23*c103de24SGrant Likely #define CACHE_NR_REGS 3 24*c103de24SGrant Likely #define CACHE_NR_BANKS (STMPE_NR_GPIOS / 8) 25*c103de24SGrant Likely 26*c103de24SGrant Likely struct stmpe_gpio { 27*c103de24SGrant Likely struct gpio_chip chip; 28*c103de24SGrant Likely struct stmpe *stmpe; 29*c103de24SGrant Likely struct device *dev; 30*c103de24SGrant Likely struct mutex irq_lock; 31*c103de24SGrant Likely 32*c103de24SGrant Likely int irq_base; 33*c103de24SGrant Likely unsigned norequest_mask; 34*c103de24SGrant Likely 35*c103de24SGrant Likely /* Caches of interrupt control registers for bus_lock */ 36*c103de24SGrant Likely u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS]; 37*c103de24SGrant Likely u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS]; 38*c103de24SGrant Likely }; 39*c103de24SGrant Likely 40*c103de24SGrant Likely static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip) 41*c103de24SGrant Likely { 42*c103de24SGrant Likely return container_of(chip, struct stmpe_gpio, chip); 43*c103de24SGrant Likely } 44*c103de24SGrant Likely 45*c103de24SGrant Likely static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset) 46*c103de24SGrant Likely { 47*c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 48*c103de24SGrant Likely struct stmpe *stmpe = stmpe_gpio->stmpe; 49*c103de24SGrant Likely u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8); 50*c103de24SGrant Likely u8 mask = 1 << (offset % 8); 51*c103de24SGrant Likely int ret; 52*c103de24SGrant Likely 53*c103de24SGrant Likely ret = stmpe_reg_read(stmpe, reg); 54*c103de24SGrant Likely if (ret < 0) 55*c103de24SGrant Likely return ret; 56*c103de24SGrant Likely 57*c103de24SGrant Likely return ret & mask; 58*c103de24SGrant Likely } 59*c103de24SGrant Likely 60*c103de24SGrant Likely static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 61*c103de24SGrant Likely { 62*c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 63*c103de24SGrant Likely struct stmpe *stmpe = stmpe_gpio->stmpe; 64*c103de24SGrant Likely int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB; 65*c103de24SGrant Likely u8 reg = stmpe->regs[which] - (offset / 8); 66*c103de24SGrant Likely u8 mask = 1 << (offset % 8); 67*c103de24SGrant Likely 68*c103de24SGrant Likely stmpe_reg_write(stmpe, reg, mask); 69*c103de24SGrant Likely } 70*c103de24SGrant Likely 71*c103de24SGrant Likely static int stmpe_gpio_direction_output(struct gpio_chip *chip, 72*c103de24SGrant Likely unsigned offset, int val) 73*c103de24SGrant Likely { 74*c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 75*c103de24SGrant Likely struct stmpe *stmpe = stmpe_gpio->stmpe; 76*c103de24SGrant Likely u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); 77*c103de24SGrant Likely u8 mask = 1 << (offset % 8); 78*c103de24SGrant Likely 79*c103de24SGrant Likely stmpe_gpio_set(chip, offset, val); 80*c103de24SGrant Likely 81*c103de24SGrant Likely return stmpe_set_bits(stmpe, reg, mask, mask); 82*c103de24SGrant Likely } 83*c103de24SGrant Likely 84*c103de24SGrant Likely static int stmpe_gpio_direction_input(struct gpio_chip *chip, 85*c103de24SGrant Likely unsigned offset) 86*c103de24SGrant Likely { 87*c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 88*c103de24SGrant Likely struct stmpe *stmpe = stmpe_gpio->stmpe; 89*c103de24SGrant Likely u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); 90*c103de24SGrant Likely u8 mask = 1 << (offset % 8); 91*c103de24SGrant Likely 92*c103de24SGrant Likely return stmpe_set_bits(stmpe, reg, mask, 0); 93*c103de24SGrant Likely } 94*c103de24SGrant Likely 95*c103de24SGrant Likely static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 96*c103de24SGrant Likely { 97*c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 98*c103de24SGrant Likely 99*c103de24SGrant Likely return stmpe_gpio->irq_base + offset; 100*c103de24SGrant Likely } 101*c103de24SGrant Likely 102*c103de24SGrant Likely static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset) 103*c103de24SGrant Likely { 104*c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 105*c103de24SGrant Likely struct stmpe *stmpe = stmpe_gpio->stmpe; 106*c103de24SGrant Likely 107*c103de24SGrant Likely if (stmpe_gpio->norequest_mask & (1 << offset)) 108*c103de24SGrant Likely return -EINVAL; 109*c103de24SGrant Likely 110*c103de24SGrant Likely return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO); 111*c103de24SGrant Likely } 112*c103de24SGrant Likely 113*c103de24SGrant Likely static struct gpio_chip template_chip = { 114*c103de24SGrant Likely .label = "stmpe", 115*c103de24SGrant Likely .owner = THIS_MODULE, 116*c103de24SGrant Likely .direction_input = stmpe_gpio_direction_input, 117*c103de24SGrant Likely .get = stmpe_gpio_get, 118*c103de24SGrant Likely .direction_output = stmpe_gpio_direction_output, 119*c103de24SGrant Likely .set = stmpe_gpio_set, 120*c103de24SGrant Likely .to_irq = stmpe_gpio_to_irq, 121*c103de24SGrant Likely .request = stmpe_gpio_request, 122*c103de24SGrant Likely .can_sleep = 1, 123*c103de24SGrant Likely }; 124*c103de24SGrant Likely 125*c103de24SGrant Likely static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type) 126*c103de24SGrant Likely { 127*c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d); 128*c103de24SGrant Likely int offset = d->irq - stmpe_gpio->irq_base; 129*c103de24SGrant Likely int regoffset = offset / 8; 130*c103de24SGrant Likely int mask = 1 << (offset % 8); 131*c103de24SGrant Likely 132*c103de24SGrant Likely if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH) 133*c103de24SGrant Likely return -EINVAL; 134*c103de24SGrant Likely 135*c103de24SGrant Likely if (type == IRQ_TYPE_EDGE_RISING) 136*c103de24SGrant Likely stmpe_gpio->regs[REG_RE][regoffset] |= mask; 137*c103de24SGrant Likely else 138*c103de24SGrant Likely stmpe_gpio->regs[REG_RE][regoffset] &= ~mask; 139*c103de24SGrant Likely 140*c103de24SGrant Likely if (type == IRQ_TYPE_EDGE_FALLING) 141*c103de24SGrant Likely stmpe_gpio->regs[REG_FE][regoffset] |= mask; 142*c103de24SGrant Likely else 143*c103de24SGrant Likely stmpe_gpio->regs[REG_FE][regoffset] &= ~mask; 144*c103de24SGrant Likely 145*c103de24SGrant Likely return 0; 146*c103de24SGrant Likely } 147*c103de24SGrant Likely 148*c103de24SGrant Likely static void stmpe_gpio_irq_lock(struct irq_data *d) 149*c103de24SGrant Likely { 150*c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d); 151*c103de24SGrant Likely 152*c103de24SGrant Likely mutex_lock(&stmpe_gpio->irq_lock); 153*c103de24SGrant Likely } 154*c103de24SGrant Likely 155*c103de24SGrant Likely static void stmpe_gpio_irq_sync_unlock(struct irq_data *d) 156*c103de24SGrant Likely { 157*c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d); 158*c103de24SGrant Likely struct stmpe *stmpe = stmpe_gpio->stmpe; 159*c103de24SGrant Likely int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); 160*c103de24SGrant Likely static const u8 regmap[] = { 161*c103de24SGrant Likely [REG_RE] = STMPE_IDX_GPRER_LSB, 162*c103de24SGrant Likely [REG_FE] = STMPE_IDX_GPFER_LSB, 163*c103de24SGrant Likely [REG_IE] = STMPE_IDX_IEGPIOR_LSB, 164*c103de24SGrant Likely }; 165*c103de24SGrant Likely int i, j; 166*c103de24SGrant Likely 167*c103de24SGrant Likely for (i = 0; i < CACHE_NR_REGS; i++) { 168*c103de24SGrant Likely for (j = 0; j < num_banks; j++) { 169*c103de24SGrant Likely u8 old = stmpe_gpio->oldregs[i][j]; 170*c103de24SGrant Likely u8 new = stmpe_gpio->regs[i][j]; 171*c103de24SGrant Likely 172*c103de24SGrant Likely if (new == old) 173*c103de24SGrant Likely continue; 174*c103de24SGrant Likely 175*c103de24SGrant Likely stmpe_gpio->oldregs[i][j] = new; 176*c103de24SGrant Likely stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new); 177*c103de24SGrant Likely } 178*c103de24SGrant Likely } 179*c103de24SGrant Likely 180*c103de24SGrant Likely mutex_unlock(&stmpe_gpio->irq_lock); 181*c103de24SGrant Likely } 182*c103de24SGrant Likely 183*c103de24SGrant Likely static void stmpe_gpio_irq_mask(struct irq_data *d) 184*c103de24SGrant Likely { 185*c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d); 186*c103de24SGrant Likely int offset = d->irq - stmpe_gpio->irq_base; 187*c103de24SGrant Likely int regoffset = offset / 8; 188*c103de24SGrant Likely int mask = 1 << (offset % 8); 189*c103de24SGrant Likely 190*c103de24SGrant Likely stmpe_gpio->regs[REG_IE][regoffset] &= ~mask; 191*c103de24SGrant Likely } 192*c103de24SGrant Likely 193*c103de24SGrant Likely static void stmpe_gpio_irq_unmask(struct irq_data *d) 194*c103de24SGrant Likely { 195*c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d); 196*c103de24SGrant Likely int offset = d->irq - stmpe_gpio->irq_base; 197*c103de24SGrant Likely int regoffset = offset / 8; 198*c103de24SGrant Likely int mask = 1 << (offset % 8); 199*c103de24SGrant Likely 200*c103de24SGrant Likely stmpe_gpio->regs[REG_IE][regoffset] |= mask; 201*c103de24SGrant Likely } 202*c103de24SGrant Likely 203*c103de24SGrant Likely static struct irq_chip stmpe_gpio_irq_chip = { 204*c103de24SGrant Likely .name = "stmpe-gpio", 205*c103de24SGrant Likely .irq_bus_lock = stmpe_gpio_irq_lock, 206*c103de24SGrant Likely .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock, 207*c103de24SGrant Likely .irq_mask = stmpe_gpio_irq_mask, 208*c103de24SGrant Likely .irq_unmask = stmpe_gpio_irq_unmask, 209*c103de24SGrant Likely .irq_set_type = stmpe_gpio_irq_set_type, 210*c103de24SGrant Likely }; 211*c103de24SGrant Likely 212*c103de24SGrant Likely static irqreturn_t stmpe_gpio_irq(int irq, void *dev) 213*c103de24SGrant Likely { 214*c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = dev; 215*c103de24SGrant Likely struct stmpe *stmpe = stmpe_gpio->stmpe; 216*c103de24SGrant Likely u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB]; 217*c103de24SGrant Likely int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); 218*c103de24SGrant Likely u8 status[num_banks]; 219*c103de24SGrant Likely int ret; 220*c103de24SGrant Likely int i; 221*c103de24SGrant Likely 222*c103de24SGrant Likely ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status); 223*c103de24SGrant Likely if (ret < 0) 224*c103de24SGrant Likely return IRQ_NONE; 225*c103de24SGrant Likely 226*c103de24SGrant Likely for (i = 0; i < num_banks; i++) { 227*c103de24SGrant Likely int bank = num_banks - i - 1; 228*c103de24SGrant Likely unsigned int enabled = stmpe_gpio->regs[REG_IE][bank]; 229*c103de24SGrant Likely unsigned int stat = status[i]; 230*c103de24SGrant Likely 231*c103de24SGrant Likely stat &= enabled; 232*c103de24SGrant Likely if (!stat) 233*c103de24SGrant Likely continue; 234*c103de24SGrant Likely 235*c103de24SGrant Likely while (stat) { 236*c103de24SGrant Likely int bit = __ffs(stat); 237*c103de24SGrant Likely int line = bank * 8 + bit; 238*c103de24SGrant Likely 239*c103de24SGrant Likely handle_nested_irq(stmpe_gpio->irq_base + line); 240*c103de24SGrant Likely stat &= ~(1 << bit); 241*c103de24SGrant Likely } 242*c103de24SGrant Likely 243*c103de24SGrant Likely stmpe_reg_write(stmpe, statmsbreg + i, status[i]); 244*c103de24SGrant Likely stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB] + i, 245*c103de24SGrant Likely status[i]); 246*c103de24SGrant Likely } 247*c103de24SGrant Likely 248*c103de24SGrant Likely return IRQ_HANDLED; 249*c103de24SGrant Likely } 250*c103de24SGrant Likely 251*c103de24SGrant Likely static int __devinit stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio) 252*c103de24SGrant Likely { 253*c103de24SGrant Likely int base = stmpe_gpio->irq_base; 254*c103de24SGrant Likely int irq; 255*c103de24SGrant Likely 256*c103de24SGrant Likely for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) { 257*c103de24SGrant Likely irq_set_chip_data(irq, stmpe_gpio); 258*c103de24SGrant Likely irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip, 259*c103de24SGrant Likely handle_simple_irq); 260*c103de24SGrant Likely irq_set_nested_thread(irq, 1); 261*c103de24SGrant Likely #ifdef CONFIG_ARM 262*c103de24SGrant Likely set_irq_flags(irq, IRQF_VALID); 263*c103de24SGrant Likely #else 264*c103de24SGrant Likely irq_set_noprobe(irq); 265*c103de24SGrant Likely #endif 266*c103de24SGrant Likely } 267*c103de24SGrant Likely 268*c103de24SGrant Likely return 0; 269*c103de24SGrant Likely } 270*c103de24SGrant Likely 271*c103de24SGrant Likely static void stmpe_gpio_irq_remove(struct stmpe_gpio *stmpe_gpio) 272*c103de24SGrant Likely { 273*c103de24SGrant Likely int base = stmpe_gpio->irq_base; 274*c103de24SGrant Likely int irq; 275*c103de24SGrant Likely 276*c103de24SGrant Likely for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) { 277*c103de24SGrant Likely #ifdef CONFIG_ARM 278*c103de24SGrant Likely set_irq_flags(irq, 0); 279*c103de24SGrant Likely #endif 280*c103de24SGrant Likely irq_set_chip_and_handler(irq, NULL, NULL); 281*c103de24SGrant Likely irq_set_chip_data(irq, NULL); 282*c103de24SGrant Likely } 283*c103de24SGrant Likely } 284*c103de24SGrant Likely 285*c103de24SGrant Likely static int __devinit stmpe_gpio_probe(struct platform_device *pdev) 286*c103de24SGrant Likely { 287*c103de24SGrant Likely struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent); 288*c103de24SGrant Likely struct stmpe_gpio_platform_data *pdata; 289*c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio; 290*c103de24SGrant Likely int ret; 291*c103de24SGrant Likely int irq; 292*c103de24SGrant Likely 293*c103de24SGrant Likely pdata = stmpe->pdata->gpio; 294*c103de24SGrant Likely 295*c103de24SGrant Likely irq = platform_get_irq(pdev, 0); 296*c103de24SGrant Likely if (irq < 0) 297*c103de24SGrant Likely return irq; 298*c103de24SGrant Likely 299*c103de24SGrant Likely stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL); 300*c103de24SGrant Likely if (!stmpe_gpio) 301*c103de24SGrant Likely return -ENOMEM; 302*c103de24SGrant Likely 303*c103de24SGrant Likely mutex_init(&stmpe_gpio->irq_lock); 304*c103de24SGrant Likely 305*c103de24SGrant Likely stmpe_gpio->dev = &pdev->dev; 306*c103de24SGrant Likely stmpe_gpio->stmpe = stmpe; 307*c103de24SGrant Likely stmpe_gpio->norequest_mask = pdata ? pdata->norequest_mask : 0; 308*c103de24SGrant Likely 309*c103de24SGrant Likely stmpe_gpio->chip = template_chip; 310*c103de24SGrant Likely stmpe_gpio->chip.ngpio = stmpe->num_gpios; 311*c103de24SGrant Likely stmpe_gpio->chip.dev = &pdev->dev; 312*c103de24SGrant Likely stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1; 313*c103de24SGrant Likely 314*c103de24SGrant Likely stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0); 315*c103de24SGrant Likely 316*c103de24SGrant Likely ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO); 317*c103de24SGrant Likely if (ret) 318*c103de24SGrant Likely goto out_free; 319*c103de24SGrant Likely 320*c103de24SGrant Likely ret = stmpe_gpio_irq_init(stmpe_gpio); 321*c103de24SGrant Likely if (ret) 322*c103de24SGrant Likely goto out_disable; 323*c103de24SGrant Likely 324*c103de24SGrant Likely ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq, IRQF_ONESHOT, 325*c103de24SGrant Likely "stmpe-gpio", stmpe_gpio); 326*c103de24SGrant Likely if (ret) { 327*c103de24SGrant Likely dev_err(&pdev->dev, "unable to get irq: %d\n", ret); 328*c103de24SGrant Likely goto out_removeirq; 329*c103de24SGrant Likely } 330*c103de24SGrant Likely 331*c103de24SGrant Likely ret = gpiochip_add(&stmpe_gpio->chip); 332*c103de24SGrant Likely if (ret) { 333*c103de24SGrant Likely dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); 334*c103de24SGrant Likely goto out_freeirq; 335*c103de24SGrant Likely } 336*c103de24SGrant Likely 337*c103de24SGrant Likely if (pdata && pdata->setup) 338*c103de24SGrant Likely pdata->setup(stmpe, stmpe_gpio->chip.base); 339*c103de24SGrant Likely 340*c103de24SGrant Likely platform_set_drvdata(pdev, stmpe_gpio); 341*c103de24SGrant Likely 342*c103de24SGrant Likely return 0; 343*c103de24SGrant Likely 344*c103de24SGrant Likely out_freeirq: 345*c103de24SGrant Likely free_irq(irq, stmpe_gpio); 346*c103de24SGrant Likely out_removeirq: 347*c103de24SGrant Likely stmpe_gpio_irq_remove(stmpe_gpio); 348*c103de24SGrant Likely out_disable: 349*c103de24SGrant Likely stmpe_disable(stmpe, STMPE_BLOCK_GPIO); 350*c103de24SGrant Likely out_free: 351*c103de24SGrant Likely kfree(stmpe_gpio); 352*c103de24SGrant Likely return ret; 353*c103de24SGrant Likely } 354*c103de24SGrant Likely 355*c103de24SGrant Likely static int __devexit stmpe_gpio_remove(struct platform_device *pdev) 356*c103de24SGrant Likely { 357*c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev); 358*c103de24SGrant Likely struct stmpe *stmpe = stmpe_gpio->stmpe; 359*c103de24SGrant Likely struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio; 360*c103de24SGrant Likely int irq = platform_get_irq(pdev, 0); 361*c103de24SGrant Likely int ret; 362*c103de24SGrant Likely 363*c103de24SGrant Likely if (pdata && pdata->remove) 364*c103de24SGrant Likely pdata->remove(stmpe, stmpe_gpio->chip.base); 365*c103de24SGrant Likely 366*c103de24SGrant Likely ret = gpiochip_remove(&stmpe_gpio->chip); 367*c103de24SGrant Likely if (ret < 0) { 368*c103de24SGrant Likely dev_err(stmpe_gpio->dev, 369*c103de24SGrant Likely "unable to remove gpiochip: %d\n", ret); 370*c103de24SGrant Likely return ret; 371*c103de24SGrant Likely } 372*c103de24SGrant Likely 373*c103de24SGrant Likely stmpe_disable(stmpe, STMPE_BLOCK_GPIO); 374*c103de24SGrant Likely 375*c103de24SGrant Likely free_irq(irq, stmpe_gpio); 376*c103de24SGrant Likely stmpe_gpio_irq_remove(stmpe_gpio); 377*c103de24SGrant Likely platform_set_drvdata(pdev, NULL); 378*c103de24SGrant Likely kfree(stmpe_gpio); 379*c103de24SGrant Likely 380*c103de24SGrant Likely return 0; 381*c103de24SGrant Likely } 382*c103de24SGrant Likely 383*c103de24SGrant Likely static struct platform_driver stmpe_gpio_driver = { 384*c103de24SGrant Likely .driver.name = "stmpe-gpio", 385*c103de24SGrant Likely .driver.owner = THIS_MODULE, 386*c103de24SGrant Likely .probe = stmpe_gpio_probe, 387*c103de24SGrant Likely .remove = __devexit_p(stmpe_gpio_remove), 388*c103de24SGrant Likely }; 389*c103de24SGrant Likely 390*c103de24SGrant Likely static int __init stmpe_gpio_init(void) 391*c103de24SGrant Likely { 392*c103de24SGrant Likely return platform_driver_register(&stmpe_gpio_driver); 393*c103de24SGrant Likely } 394*c103de24SGrant Likely subsys_initcall(stmpe_gpio_init); 395*c103de24SGrant Likely 396*c103de24SGrant Likely static void __exit stmpe_gpio_exit(void) 397*c103de24SGrant Likely { 398*c103de24SGrant Likely platform_driver_unregister(&stmpe_gpio_driver); 399*c103de24SGrant Likely } 400*c103de24SGrant Likely module_exit(stmpe_gpio_exit); 401*c103de24SGrant Likely 402*c103de24SGrant Likely MODULE_LICENSE("GPL v2"); 403*c103de24SGrant Likely MODULE_DESCRIPTION("STMPExxxx GPIO driver"); 404*c103de24SGrant Likely MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>"); 405