1c103de24SGrant Likely /* 2c103de24SGrant Likely * Copyright (C) ST-Ericsson SA 2010 3c103de24SGrant Likely * 4c103de24SGrant Likely * License Terms: GNU General Public License, version 2 5c103de24SGrant Likely * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson 6c103de24SGrant Likely */ 7c103de24SGrant Likely 8c103de24SGrant Likely #include <linux/module.h> 9c103de24SGrant Likely #include <linux/init.h> 10c103de24SGrant Likely #include <linux/platform_device.h> 11c103de24SGrant Likely #include <linux/slab.h> 12c103de24SGrant Likely #include <linux/gpio.h> 13c103de24SGrant Likely #include <linux/irq.h> 14fc13d5a5SLee Jones #include <linux/irqdomain.h> 15c103de24SGrant Likely #include <linux/interrupt.h> 1686605cfeSVipul Kumar Samar #include <linux/of.h> 17c103de24SGrant Likely #include <linux/mfd/stmpe.h> 18c103de24SGrant Likely 19c103de24SGrant Likely /* 20c103de24SGrant Likely * These registers are modified under the irq bus lock and cached to avoid 21c103de24SGrant Likely * unnecessary writes in bus_sync_unlock. 22c103de24SGrant Likely */ 23c103de24SGrant Likely enum { REG_RE, REG_FE, REG_IE }; 24c103de24SGrant Likely 25c103de24SGrant Likely #define CACHE_NR_REGS 3 26c103de24SGrant Likely #define CACHE_NR_BANKS (STMPE_NR_GPIOS / 8) 27c103de24SGrant Likely 28c103de24SGrant Likely struct stmpe_gpio { 29c103de24SGrant Likely struct gpio_chip chip; 30c103de24SGrant Likely struct stmpe *stmpe; 31c103de24SGrant Likely struct device *dev; 32c103de24SGrant Likely struct mutex irq_lock; 33fc13d5a5SLee Jones struct irq_domain *domain; 34c103de24SGrant Likely 35c103de24SGrant Likely int irq_base; 36c103de24SGrant Likely unsigned norequest_mask; 37c103de24SGrant Likely 38c103de24SGrant Likely /* Caches of interrupt control registers for bus_lock */ 39c103de24SGrant Likely u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS]; 40c103de24SGrant Likely u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS]; 41c103de24SGrant Likely }; 42c103de24SGrant Likely 43c103de24SGrant Likely static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip) 44c103de24SGrant Likely { 45c103de24SGrant Likely return container_of(chip, struct stmpe_gpio, chip); 46c103de24SGrant Likely } 47c103de24SGrant Likely 48c103de24SGrant Likely static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset) 49c103de24SGrant Likely { 50c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 51c103de24SGrant Likely struct stmpe *stmpe = stmpe_gpio->stmpe; 52c103de24SGrant Likely u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8); 53c103de24SGrant Likely u8 mask = 1 << (offset % 8); 54c103de24SGrant Likely int ret; 55c103de24SGrant Likely 56c103de24SGrant Likely ret = stmpe_reg_read(stmpe, reg); 57c103de24SGrant Likely if (ret < 0) 58c103de24SGrant Likely return ret; 59c103de24SGrant Likely 607535b8beSBhupesh Sharma return !!(ret & mask); 61c103de24SGrant Likely } 62c103de24SGrant Likely 63c103de24SGrant Likely static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 64c103de24SGrant Likely { 65c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 66c103de24SGrant Likely struct stmpe *stmpe = stmpe_gpio->stmpe; 67c103de24SGrant Likely int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB; 68c103de24SGrant Likely u8 reg = stmpe->regs[which] - (offset / 8); 69c103de24SGrant Likely u8 mask = 1 << (offset % 8); 70c103de24SGrant Likely 71cccdceb9SViresh Kumar /* 72cccdceb9SViresh Kumar * Some variants have single register for gpio set/clear functionality. 73cccdceb9SViresh Kumar * For them we need to write 0 to clear and 1 to set. 74cccdceb9SViresh Kumar */ 75cccdceb9SViresh Kumar if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB]) 76cccdceb9SViresh Kumar stmpe_set_bits(stmpe, reg, mask, val ? mask : 0); 77cccdceb9SViresh Kumar else 78c103de24SGrant Likely stmpe_reg_write(stmpe, reg, mask); 79c103de24SGrant Likely } 80c103de24SGrant Likely 81c103de24SGrant Likely static int stmpe_gpio_direction_output(struct gpio_chip *chip, 82c103de24SGrant Likely unsigned offset, int val) 83c103de24SGrant Likely { 84c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 85c103de24SGrant Likely struct stmpe *stmpe = stmpe_gpio->stmpe; 86c103de24SGrant Likely u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); 87c103de24SGrant Likely u8 mask = 1 << (offset % 8); 88c103de24SGrant Likely 89c103de24SGrant Likely stmpe_gpio_set(chip, offset, val); 90c103de24SGrant Likely 91c103de24SGrant Likely return stmpe_set_bits(stmpe, reg, mask, mask); 92c103de24SGrant Likely } 93c103de24SGrant Likely 94c103de24SGrant Likely static int stmpe_gpio_direction_input(struct gpio_chip *chip, 95c103de24SGrant Likely unsigned offset) 96c103de24SGrant Likely { 97c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 98c103de24SGrant Likely struct stmpe *stmpe = stmpe_gpio->stmpe; 99c103de24SGrant Likely u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); 100c103de24SGrant Likely u8 mask = 1 << (offset % 8); 101c103de24SGrant Likely 102c103de24SGrant Likely return stmpe_set_bits(stmpe, reg, mask, 0); 103c103de24SGrant Likely } 104c103de24SGrant Likely 105c103de24SGrant Likely static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 106c103de24SGrant Likely { 107c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 108c103de24SGrant Likely 109fc13d5a5SLee Jones return irq_create_mapping(stmpe_gpio->domain, offset); 110c103de24SGrant Likely } 111c103de24SGrant Likely 112c103de24SGrant Likely static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset) 113c103de24SGrant Likely { 114c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 115c103de24SGrant Likely struct stmpe *stmpe = stmpe_gpio->stmpe; 116c103de24SGrant Likely 117c103de24SGrant Likely if (stmpe_gpio->norequest_mask & (1 << offset)) 118c103de24SGrant Likely return -EINVAL; 119c103de24SGrant Likely 120c103de24SGrant Likely return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO); 121c103de24SGrant Likely } 122c103de24SGrant Likely 123c103de24SGrant Likely static struct gpio_chip template_chip = { 124c103de24SGrant Likely .label = "stmpe", 125c103de24SGrant Likely .owner = THIS_MODULE, 126c103de24SGrant Likely .direction_input = stmpe_gpio_direction_input, 127c103de24SGrant Likely .get = stmpe_gpio_get, 128c103de24SGrant Likely .direction_output = stmpe_gpio_direction_output, 129c103de24SGrant Likely .set = stmpe_gpio_set, 130c103de24SGrant Likely .to_irq = stmpe_gpio_to_irq, 131c103de24SGrant Likely .request = stmpe_gpio_request, 132*9fb1f39eSLinus Walleij .can_sleep = true, 133c103de24SGrant Likely }; 134c103de24SGrant Likely 135c103de24SGrant Likely static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type) 136c103de24SGrant Likely { 137c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d); 138fc13d5a5SLee Jones int offset = d->hwirq; 139c103de24SGrant Likely int regoffset = offset / 8; 140c103de24SGrant Likely int mask = 1 << (offset % 8); 141c103de24SGrant Likely 142c103de24SGrant Likely if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH) 143c103de24SGrant Likely return -EINVAL; 144c103de24SGrant Likely 145cccdceb9SViresh Kumar /* STMPE801 doesn't have RE and FE registers */ 146cccdceb9SViresh Kumar if (stmpe_gpio->stmpe->partnum == STMPE801) 147cccdceb9SViresh Kumar return 0; 148cccdceb9SViresh Kumar 149c103de24SGrant Likely if (type == IRQ_TYPE_EDGE_RISING) 150c103de24SGrant Likely stmpe_gpio->regs[REG_RE][regoffset] |= mask; 151c103de24SGrant Likely else 152c103de24SGrant Likely stmpe_gpio->regs[REG_RE][regoffset] &= ~mask; 153c103de24SGrant Likely 154c103de24SGrant Likely if (type == IRQ_TYPE_EDGE_FALLING) 155c103de24SGrant Likely stmpe_gpio->regs[REG_FE][regoffset] |= mask; 156c103de24SGrant Likely else 157c103de24SGrant Likely stmpe_gpio->regs[REG_FE][regoffset] &= ~mask; 158c103de24SGrant Likely 159c103de24SGrant Likely return 0; 160c103de24SGrant Likely } 161c103de24SGrant Likely 162c103de24SGrant Likely static void stmpe_gpio_irq_lock(struct irq_data *d) 163c103de24SGrant Likely { 164c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d); 165c103de24SGrant Likely 166c103de24SGrant Likely mutex_lock(&stmpe_gpio->irq_lock); 167c103de24SGrant Likely } 168c103de24SGrant Likely 169c103de24SGrant Likely static void stmpe_gpio_irq_sync_unlock(struct irq_data *d) 170c103de24SGrant Likely { 171c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d); 172c103de24SGrant Likely struct stmpe *stmpe = stmpe_gpio->stmpe; 173c103de24SGrant Likely int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); 174c103de24SGrant Likely static const u8 regmap[] = { 175c103de24SGrant Likely [REG_RE] = STMPE_IDX_GPRER_LSB, 176c103de24SGrant Likely [REG_FE] = STMPE_IDX_GPFER_LSB, 177c103de24SGrant Likely [REG_IE] = STMPE_IDX_IEGPIOR_LSB, 178c103de24SGrant Likely }; 179c103de24SGrant Likely int i, j; 180c103de24SGrant Likely 181c103de24SGrant Likely for (i = 0; i < CACHE_NR_REGS; i++) { 182cccdceb9SViresh Kumar /* STMPE801 doesn't have RE and FE registers */ 183cccdceb9SViresh Kumar if ((stmpe->partnum == STMPE801) && 184cccdceb9SViresh Kumar (i != REG_IE)) 185cccdceb9SViresh Kumar continue; 186cccdceb9SViresh Kumar 187c103de24SGrant Likely for (j = 0; j < num_banks; j++) { 188c103de24SGrant Likely u8 old = stmpe_gpio->oldregs[i][j]; 189c103de24SGrant Likely u8 new = stmpe_gpio->regs[i][j]; 190c103de24SGrant Likely 191c103de24SGrant Likely if (new == old) 192c103de24SGrant Likely continue; 193c103de24SGrant Likely 194c103de24SGrant Likely stmpe_gpio->oldregs[i][j] = new; 195c103de24SGrant Likely stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new); 196c103de24SGrant Likely } 197c103de24SGrant Likely } 198c103de24SGrant Likely 199c103de24SGrant Likely mutex_unlock(&stmpe_gpio->irq_lock); 200c103de24SGrant Likely } 201c103de24SGrant Likely 202c103de24SGrant Likely static void stmpe_gpio_irq_mask(struct irq_data *d) 203c103de24SGrant Likely { 204c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d); 205fc13d5a5SLee Jones int offset = d->hwirq; 206c103de24SGrant Likely int regoffset = offset / 8; 207c103de24SGrant Likely int mask = 1 << (offset % 8); 208c103de24SGrant Likely 209c103de24SGrant Likely stmpe_gpio->regs[REG_IE][regoffset] &= ~mask; 210c103de24SGrant Likely } 211c103de24SGrant Likely 212c103de24SGrant Likely static void stmpe_gpio_irq_unmask(struct irq_data *d) 213c103de24SGrant Likely { 214c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d); 215fc13d5a5SLee Jones int offset = d->hwirq; 216c103de24SGrant Likely int regoffset = offset / 8; 217c103de24SGrant Likely int mask = 1 << (offset % 8); 218c103de24SGrant Likely 219c103de24SGrant Likely stmpe_gpio->regs[REG_IE][regoffset] |= mask; 220c103de24SGrant Likely } 221c103de24SGrant Likely 222c103de24SGrant Likely static struct irq_chip stmpe_gpio_irq_chip = { 223c103de24SGrant Likely .name = "stmpe-gpio", 224c103de24SGrant Likely .irq_bus_lock = stmpe_gpio_irq_lock, 225c103de24SGrant Likely .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock, 226c103de24SGrant Likely .irq_mask = stmpe_gpio_irq_mask, 227c103de24SGrant Likely .irq_unmask = stmpe_gpio_irq_unmask, 228c103de24SGrant Likely .irq_set_type = stmpe_gpio_irq_set_type, 229c103de24SGrant Likely }; 230c103de24SGrant Likely 231c103de24SGrant Likely static irqreturn_t stmpe_gpio_irq(int irq, void *dev) 232c103de24SGrant Likely { 233c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = dev; 234c103de24SGrant Likely struct stmpe *stmpe = stmpe_gpio->stmpe; 235c103de24SGrant Likely u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB]; 236c103de24SGrant Likely int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); 237c103de24SGrant Likely u8 status[num_banks]; 238c103de24SGrant Likely int ret; 239c103de24SGrant Likely int i; 240c103de24SGrant Likely 241c103de24SGrant Likely ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status); 242c103de24SGrant Likely if (ret < 0) 243c103de24SGrant Likely return IRQ_NONE; 244c103de24SGrant Likely 245c103de24SGrant Likely for (i = 0; i < num_banks; i++) { 246c103de24SGrant Likely int bank = num_banks - i - 1; 247c103de24SGrant Likely unsigned int enabled = stmpe_gpio->regs[REG_IE][bank]; 248c103de24SGrant Likely unsigned int stat = status[i]; 249c103de24SGrant Likely 250c103de24SGrant Likely stat &= enabled; 251c103de24SGrant Likely if (!stat) 252c103de24SGrant Likely continue; 253c103de24SGrant Likely 254c103de24SGrant Likely while (stat) { 255c103de24SGrant Likely int bit = __ffs(stat); 256c103de24SGrant Likely int line = bank * 8 + bit; 257ed05e204SLinus Walleij int child_irq = irq_find_mapping(stmpe_gpio->domain, 258ed05e204SLinus Walleij line); 259c103de24SGrant Likely 260ed05e204SLinus Walleij handle_nested_irq(child_irq); 261c103de24SGrant Likely stat &= ~(1 << bit); 262c103de24SGrant Likely } 263c103de24SGrant Likely 264c103de24SGrant Likely stmpe_reg_write(stmpe, statmsbreg + i, status[i]); 265cccdceb9SViresh Kumar 266cccdceb9SViresh Kumar /* Edge detect register is not present on 801 */ 267cccdceb9SViresh Kumar if (stmpe->partnum != STMPE801) 268cccdceb9SViresh Kumar stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB] 269cccdceb9SViresh Kumar + i, status[i]); 270c103de24SGrant Likely } 271c103de24SGrant Likely 272c103de24SGrant Likely return IRQ_HANDLED; 273c103de24SGrant Likely } 274c103de24SGrant Likely 275ed05e204SLinus Walleij static int stmpe_gpio_irq_map(struct irq_domain *d, unsigned int irq, 276fc13d5a5SLee Jones irq_hw_number_t hwirq) 277c103de24SGrant Likely { 278fc13d5a5SLee Jones struct stmpe_gpio *stmpe_gpio = d->host_data; 279c103de24SGrant Likely 280fc13d5a5SLee Jones if (!stmpe_gpio) 281fc13d5a5SLee Jones return -EINVAL; 282fc13d5a5SLee Jones 283ed05e204SLinus Walleij irq_set_chip_data(irq, stmpe_gpio); 284ed05e204SLinus Walleij irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip, 285c103de24SGrant Likely handle_simple_irq); 286ed05e204SLinus Walleij irq_set_nested_thread(irq, 1); 287c103de24SGrant Likely #ifdef CONFIG_ARM 288ed05e204SLinus Walleij set_irq_flags(irq, IRQF_VALID); 289c103de24SGrant Likely #else 290ed05e204SLinus Walleij irq_set_noprobe(irq); 291c103de24SGrant Likely #endif 292c103de24SGrant Likely 293c103de24SGrant Likely return 0; 294c103de24SGrant Likely } 295c103de24SGrant Likely 296ed05e204SLinus Walleij static void stmpe_gpio_irq_unmap(struct irq_domain *d, unsigned int irq) 297fc13d5a5SLee Jones { 298fc13d5a5SLee Jones #ifdef CONFIG_ARM 299ed05e204SLinus Walleij set_irq_flags(irq, 0); 300fc13d5a5SLee Jones #endif 301ed05e204SLinus Walleij irq_set_chip_and_handler(irq, NULL, NULL); 302ed05e204SLinus Walleij irq_set_chip_data(irq, NULL); 303fc13d5a5SLee Jones } 304fc13d5a5SLee Jones 305fc13d5a5SLee Jones static const struct irq_domain_ops stmpe_gpio_irq_simple_ops = { 306fc13d5a5SLee Jones .unmap = stmpe_gpio_irq_unmap, 307fc13d5a5SLee Jones .map = stmpe_gpio_irq_map, 308fc13d5a5SLee Jones .xlate = irq_domain_xlate_twocell, 309fc13d5a5SLee Jones }; 310fc13d5a5SLee Jones 3119afd9b70SGabriel Fernandez static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio, 3129afd9b70SGabriel Fernandez struct device_node *np) 313c103de24SGrant Likely { 3149afd9b70SGabriel Fernandez int base = 0; 315c103de24SGrant Likely 3169afd9b70SGabriel Fernandez if (!np) 3179afd9b70SGabriel Fernandez base = stmpe_gpio->irq_base; 3189afd9b70SGabriel Fernandez 3199afd9b70SGabriel Fernandez stmpe_gpio->domain = irq_domain_add_simple(np, 320fc13d5a5SLee Jones stmpe_gpio->chip.ngpio, base, 321fc13d5a5SLee Jones &stmpe_gpio_irq_simple_ops, stmpe_gpio); 322fc13d5a5SLee Jones if (!stmpe_gpio->domain) { 323fc13d5a5SLee Jones dev_err(stmpe_gpio->dev, "failed to create irqdomain\n"); 324fc13d5a5SLee Jones return -ENOSYS; 325c103de24SGrant Likely } 326fc13d5a5SLee Jones 327fc13d5a5SLee Jones return 0; 328c103de24SGrant Likely } 329c103de24SGrant Likely 3303836309dSBill Pemberton static int stmpe_gpio_probe(struct platform_device *pdev) 331c103de24SGrant Likely { 332c103de24SGrant Likely struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent); 33386605cfeSVipul Kumar Samar struct device_node *np = pdev->dev.of_node; 334c103de24SGrant Likely struct stmpe_gpio_platform_data *pdata; 335c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio; 336c103de24SGrant Likely int ret; 33738040c85SChris Blair int irq = 0; 338c103de24SGrant Likely 339c103de24SGrant Likely pdata = stmpe->pdata->gpio; 340c103de24SGrant Likely 341c103de24SGrant Likely irq = platform_get_irq(pdev, 0); 342c103de24SGrant Likely 343c103de24SGrant Likely stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL); 344c103de24SGrant Likely if (!stmpe_gpio) 345c103de24SGrant Likely return -ENOMEM; 346c103de24SGrant Likely 347c103de24SGrant Likely mutex_init(&stmpe_gpio->irq_lock); 348c103de24SGrant Likely 349c103de24SGrant Likely stmpe_gpio->dev = &pdev->dev; 350c103de24SGrant Likely stmpe_gpio->stmpe = stmpe; 351c103de24SGrant Likely stmpe_gpio->chip = template_chip; 352c103de24SGrant Likely stmpe_gpio->chip.ngpio = stmpe->num_gpios; 353c103de24SGrant Likely stmpe_gpio->chip.dev = &pdev->dev; 3549afd9b70SGabriel Fernandez #ifdef CONFIG_OF 3559afd9b70SGabriel Fernandez stmpe_gpio->chip.of_node = np; 3569afd9b70SGabriel Fernandez #endif 357c103de24SGrant Likely stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1; 358c103de24SGrant Likely 35986605cfeSVipul Kumar Samar if (pdata) 36086605cfeSVipul Kumar Samar stmpe_gpio->norequest_mask = pdata->norequest_mask; 36186605cfeSVipul Kumar Samar else if (np) 36286605cfeSVipul Kumar Samar of_property_read_u32(np, "st,norequest-mask", 36386605cfeSVipul Kumar Samar &stmpe_gpio->norequest_mask); 36486605cfeSVipul Kumar Samar 36538040c85SChris Blair if (irq >= 0) 366c103de24SGrant Likely stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0); 36738040c85SChris Blair else 36838040c85SChris Blair dev_info(&pdev->dev, 36938040c85SChris Blair "device configured in no-irq mode; " 37038040c85SChris Blair "irqs are not available\n"); 371c103de24SGrant Likely 372c103de24SGrant Likely ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO); 373c103de24SGrant Likely if (ret) 374c103de24SGrant Likely goto out_free; 375c103de24SGrant Likely 37638040c85SChris Blair if (irq >= 0) { 3779afd9b70SGabriel Fernandez ret = stmpe_gpio_irq_init(stmpe_gpio, np); 378c103de24SGrant Likely if (ret) 379c103de24SGrant Likely goto out_disable; 380c103de24SGrant Likely 38138040c85SChris Blair ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq, 38238040c85SChris Blair IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio); 383c103de24SGrant Likely if (ret) { 384c103de24SGrant Likely dev_err(&pdev->dev, "unable to get irq: %d\n", ret); 385fc13d5a5SLee Jones goto out_disable; 386c103de24SGrant Likely } 38738040c85SChris Blair } 388c103de24SGrant Likely 389c103de24SGrant Likely ret = gpiochip_add(&stmpe_gpio->chip); 390c103de24SGrant Likely if (ret) { 391c103de24SGrant Likely dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); 392c103de24SGrant Likely goto out_freeirq; 393c103de24SGrant Likely } 394c103de24SGrant Likely 395c103de24SGrant Likely if (pdata && pdata->setup) 396c103de24SGrant Likely pdata->setup(stmpe, stmpe_gpio->chip.base); 397c103de24SGrant Likely 398c103de24SGrant Likely platform_set_drvdata(pdev, stmpe_gpio); 399c103de24SGrant Likely 400c103de24SGrant Likely return 0; 401c103de24SGrant Likely 402c103de24SGrant Likely out_freeirq: 40338040c85SChris Blair if (irq >= 0) 404c103de24SGrant Likely free_irq(irq, stmpe_gpio); 405c103de24SGrant Likely out_disable: 406c103de24SGrant Likely stmpe_disable(stmpe, STMPE_BLOCK_GPIO); 407c103de24SGrant Likely out_free: 408c103de24SGrant Likely kfree(stmpe_gpio); 409c103de24SGrant Likely return ret; 410c103de24SGrant Likely } 411c103de24SGrant Likely 412206210ceSBill Pemberton static int stmpe_gpio_remove(struct platform_device *pdev) 413c103de24SGrant Likely { 414c103de24SGrant Likely struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev); 415c103de24SGrant Likely struct stmpe *stmpe = stmpe_gpio->stmpe; 416c103de24SGrant Likely struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio; 417c103de24SGrant Likely int irq = platform_get_irq(pdev, 0); 418c103de24SGrant Likely int ret; 419c103de24SGrant Likely 420c103de24SGrant Likely if (pdata && pdata->remove) 421c103de24SGrant Likely pdata->remove(stmpe, stmpe_gpio->chip.base); 422c103de24SGrant Likely 423c103de24SGrant Likely ret = gpiochip_remove(&stmpe_gpio->chip); 424c103de24SGrant Likely if (ret < 0) { 425c103de24SGrant Likely dev_err(stmpe_gpio->dev, 426c103de24SGrant Likely "unable to remove gpiochip: %d\n", ret); 427c103de24SGrant Likely return ret; 428c103de24SGrant Likely } 429c103de24SGrant Likely 430c103de24SGrant Likely stmpe_disable(stmpe, STMPE_BLOCK_GPIO); 431c103de24SGrant Likely 432fc13d5a5SLee Jones if (irq >= 0) 433c103de24SGrant Likely free_irq(irq, stmpe_gpio); 434fc13d5a5SLee Jones 435c103de24SGrant Likely kfree(stmpe_gpio); 436c103de24SGrant Likely 437c103de24SGrant Likely return 0; 438c103de24SGrant Likely } 439c103de24SGrant Likely 440c103de24SGrant Likely static struct platform_driver stmpe_gpio_driver = { 441c103de24SGrant Likely .driver.name = "stmpe-gpio", 442c103de24SGrant Likely .driver.owner = THIS_MODULE, 443c103de24SGrant Likely .probe = stmpe_gpio_probe, 4448283c4ffSBill Pemberton .remove = stmpe_gpio_remove, 445c103de24SGrant Likely }; 446c103de24SGrant Likely 447c103de24SGrant Likely static int __init stmpe_gpio_init(void) 448c103de24SGrant Likely { 449c103de24SGrant Likely return platform_driver_register(&stmpe_gpio_driver); 450c103de24SGrant Likely } 451c103de24SGrant Likely subsys_initcall(stmpe_gpio_init); 452c103de24SGrant Likely 453c103de24SGrant Likely static void __exit stmpe_gpio_exit(void) 454c103de24SGrant Likely { 455c103de24SGrant Likely platform_driver_unregister(&stmpe_gpio_driver); 456c103de24SGrant Likely } 457c103de24SGrant Likely module_exit(stmpe_gpio_exit); 458c103de24SGrant Likely 459c103de24SGrant Likely MODULE_LICENSE("GPL v2"); 460c103de24SGrant Likely MODULE_DESCRIPTION("STMPExxxx GPIO driver"); 461c103de24SGrant Likely MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>"); 462