1*c103de24SGrant Likely /* 2*c103de24SGrant Likely * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. 3*c103de24SGrant Likely * 4*c103de24SGrant Likely * This program is free software; you can redistribute it and/or modify 5*c103de24SGrant Likely * it under the terms of the GNU General Public License as published by 6*c103de24SGrant Likely * the Free Software Foundation; version 2 of the License. 7*c103de24SGrant Likely * 8*c103de24SGrant Likely * This program is distributed in the hope that it will be useful, 9*c103de24SGrant Likely * but WITHOUT ANY WARRANTY; without even the implied warranty of 10*c103de24SGrant Likely * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11*c103de24SGrant Likely * GNU General Public License for more details. 12*c103de24SGrant Likely * 13*c103de24SGrant Likely * You should have received a copy of the GNU General Public License 14*c103de24SGrant Likely * along with this program; if not, write to the Free Software 15*c103de24SGrant Likely * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 16*c103de24SGrant Likely */ 17*c103de24SGrant Likely #include <linux/kernel.h> 18*c103de24SGrant Likely #include <linux/slab.h> 19*c103de24SGrant Likely #include <linux/pci.h> 20*c103de24SGrant Likely #include <linux/gpio.h> 21*c103de24SGrant Likely 22*c103de24SGrant Likely #define PCI_VENDOR_ID_ROHM 0x10DB 23*c103de24SGrant Likely 24*c103de24SGrant Likely struct ioh_reg_comn { 25*c103de24SGrant Likely u32 ien; 26*c103de24SGrant Likely u32 istatus; 27*c103de24SGrant Likely u32 idisp; 28*c103de24SGrant Likely u32 iclr; 29*c103de24SGrant Likely u32 imask; 30*c103de24SGrant Likely u32 imaskclr; 31*c103de24SGrant Likely u32 po; 32*c103de24SGrant Likely u32 pi; 33*c103de24SGrant Likely u32 pm; 34*c103de24SGrant Likely u32 im_0; 35*c103de24SGrant Likely u32 im_1; 36*c103de24SGrant Likely u32 reserved; 37*c103de24SGrant Likely }; 38*c103de24SGrant Likely 39*c103de24SGrant Likely struct ioh_regs { 40*c103de24SGrant Likely struct ioh_reg_comn regs[8]; 41*c103de24SGrant Likely u32 reserve1[16]; 42*c103de24SGrant Likely u32 ioh_sel_reg[4]; 43*c103de24SGrant Likely u32 reserve2[11]; 44*c103de24SGrant Likely u32 srst; 45*c103de24SGrant Likely }; 46*c103de24SGrant Likely 47*c103de24SGrant Likely /** 48*c103de24SGrant Likely * struct ioh_gpio_reg_data - The register store data. 49*c103de24SGrant Likely * @po_reg: To store contents of PO register. 50*c103de24SGrant Likely * @pm_reg: To store contents of PM register. 51*c103de24SGrant Likely */ 52*c103de24SGrant Likely struct ioh_gpio_reg_data { 53*c103de24SGrant Likely u32 po_reg; 54*c103de24SGrant Likely u32 pm_reg; 55*c103de24SGrant Likely }; 56*c103de24SGrant Likely 57*c103de24SGrant Likely /** 58*c103de24SGrant Likely * struct ioh_gpio - GPIO private data structure. 59*c103de24SGrant Likely * @base: PCI base address of Memory mapped I/O register. 60*c103de24SGrant Likely * @reg: Memory mapped IOH GPIO register list. 61*c103de24SGrant Likely * @dev: Pointer to device structure. 62*c103de24SGrant Likely * @gpio: Data for GPIO infrastructure. 63*c103de24SGrant Likely * @ioh_gpio_reg: Memory mapped Register data is saved here 64*c103de24SGrant Likely * when suspend. 65*c103de24SGrant Likely * @ch: Indicate GPIO channel 66*c103de24SGrant Likely */ 67*c103de24SGrant Likely struct ioh_gpio { 68*c103de24SGrant Likely void __iomem *base; 69*c103de24SGrant Likely struct ioh_regs __iomem *reg; 70*c103de24SGrant Likely struct device *dev; 71*c103de24SGrant Likely struct gpio_chip gpio; 72*c103de24SGrant Likely struct ioh_gpio_reg_data ioh_gpio_reg; 73*c103de24SGrant Likely struct mutex lock; 74*c103de24SGrant Likely int ch; 75*c103de24SGrant Likely }; 76*c103de24SGrant Likely 77*c103de24SGrant Likely static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12}; 78*c103de24SGrant Likely 79*c103de24SGrant Likely static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val) 80*c103de24SGrant Likely { 81*c103de24SGrant Likely u32 reg_val; 82*c103de24SGrant Likely struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio); 83*c103de24SGrant Likely 84*c103de24SGrant Likely mutex_lock(&chip->lock); 85*c103de24SGrant Likely reg_val = ioread32(&chip->reg->regs[chip->ch].po); 86*c103de24SGrant Likely if (val) 87*c103de24SGrant Likely reg_val |= (1 << nr); 88*c103de24SGrant Likely else 89*c103de24SGrant Likely reg_val &= ~(1 << nr); 90*c103de24SGrant Likely 91*c103de24SGrant Likely iowrite32(reg_val, &chip->reg->regs[chip->ch].po); 92*c103de24SGrant Likely mutex_unlock(&chip->lock); 93*c103de24SGrant Likely } 94*c103de24SGrant Likely 95*c103de24SGrant Likely static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr) 96*c103de24SGrant Likely { 97*c103de24SGrant Likely struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio); 98*c103de24SGrant Likely 99*c103de24SGrant Likely return ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr); 100*c103de24SGrant Likely } 101*c103de24SGrant Likely 102*c103de24SGrant Likely static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr, 103*c103de24SGrant Likely int val) 104*c103de24SGrant Likely { 105*c103de24SGrant Likely struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio); 106*c103de24SGrant Likely u32 pm; 107*c103de24SGrant Likely u32 reg_val; 108*c103de24SGrant Likely 109*c103de24SGrant Likely mutex_lock(&chip->lock); 110*c103de24SGrant Likely pm = ioread32(&chip->reg->regs[chip->ch].pm) & 111*c103de24SGrant Likely ((1 << num_ports[chip->ch]) - 1); 112*c103de24SGrant Likely pm |= (1 << nr); 113*c103de24SGrant Likely iowrite32(pm, &chip->reg->regs[chip->ch].pm); 114*c103de24SGrant Likely 115*c103de24SGrant Likely reg_val = ioread32(&chip->reg->regs[chip->ch].po); 116*c103de24SGrant Likely if (val) 117*c103de24SGrant Likely reg_val |= (1 << nr); 118*c103de24SGrant Likely else 119*c103de24SGrant Likely reg_val &= ~(1 << nr); 120*c103de24SGrant Likely iowrite32(reg_val, &chip->reg->regs[chip->ch].po); 121*c103de24SGrant Likely 122*c103de24SGrant Likely mutex_unlock(&chip->lock); 123*c103de24SGrant Likely 124*c103de24SGrant Likely return 0; 125*c103de24SGrant Likely } 126*c103de24SGrant Likely 127*c103de24SGrant Likely static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) 128*c103de24SGrant Likely { 129*c103de24SGrant Likely struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio); 130*c103de24SGrant Likely u32 pm; 131*c103de24SGrant Likely 132*c103de24SGrant Likely mutex_lock(&chip->lock); 133*c103de24SGrant Likely pm = ioread32(&chip->reg->regs[chip->ch].pm) & 134*c103de24SGrant Likely ((1 << num_ports[chip->ch]) - 1); 135*c103de24SGrant Likely pm &= ~(1 << nr); 136*c103de24SGrant Likely iowrite32(pm, &chip->reg->regs[chip->ch].pm); 137*c103de24SGrant Likely mutex_unlock(&chip->lock); 138*c103de24SGrant Likely 139*c103de24SGrant Likely return 0; 140*c103de24SGrant Likely } 141*c103de24SGrant Likely 142*c103de24SGrant Likely #ifdef CONFIG_PM 143*c103de24SGrant Likely /* 144*c103de24SGrant Likely * Save register configuration and disable interrupts. 145*c103de24SGrant Likely */ 146*c103de24SGrant Likely static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip) 147*c103de24SGrant Likely { 148*c103de24SGrant Likely chip->ioh_gpio_reg.po_reg = ioread32(&chip->reg->regs[chip->ch].po); 149*c103de24SGrant Likely chip->ioh_gpio_reg.pm_reg = ioread32(&chip->reg->regs[chip->ch].pm); 150*c103de24SGrant Likely } 151*c103de24SGrant Likely 152*c103de24SGrant Likely /* 153*c103de24SGrant Likely * This function restores the register configuration of the GPIO device. 154*c103de24SGrant Likely */ 155*c103de24SGrant Likely static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip) 156*c103de24SGrant Likely { 157*c103de24SGrant Likely /* to store contents of PO register */ 158*c103de24SGrant Likely iowrite32(chip->ioh_gpio_reg.po_reg, &chip->reg->regs[chip->ch].po); 159*c103de24SGrant Likely /* to store contents of PM register */ 160*c103de24SGrant Likely iowrite32(chip->ioh_gpio_reg.pm_reg, &chip->reg->regs[chip->ch].pm); 161*c103de24SGrant Likely } 162*c103de24SGrant Likely #endif 163*c103de24SGrant Likely 164*c103de24SGrant Likely static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port) 165*c103de24SGrant Likely { 166*c103de24SGrant Likely struct gpio_chip *gpio = &chip->gpio; 167*c103de24SGrant Likely 168*c103de24SGrant Likely gpio->label = dev_name(chip->dev); 169*c103de24SGrant Likely gpio->owner = THIS_MODULE; 170*c103de24SGrant Likely gpio->direction_input = ioh_gpio_direction_input; 171*c103de24SGrant Likely gpio->get = ioh_gpio_get; 172*c103de24SGrant Likely gpio->direction_output = ioh_gpio_direction_output; 173*c103de24SGrant Likely gpio->set = ioh_gpio_set; 174*c103de24SGrant Likely gpio->dbg_show = NULL; 175*c103de24SGrant Likely gpio->base = -1; 176*c103de24SGrant Likely gpio->ngpio = num_port; 177*c103de24SGrant Likely gpio->can_sleep = 0; 178*c103de24SGrant Likely } 179*c103de24SGrant Likely 180*c103de24SGrant Likely static int __devinit ioh_gpio_probe(struct pci_dev *pdev, 181*c103de24SGrant Likely const struct pci_device_id *id) 182*c103de24SGrant Likely { 183*c103de24SGrant Likely int ret; 184*c103de24SGrant Likely int i; 185*c103de24SGrant Likely struct ioh_gpio *chip; 186*c103de24SGrant Likely void __iomem *base; 187*c103de24SGrant Likely void __iomem *chip_save; 188*c103de24SGrant Likely 189*c103de24SGrant Likely ret = pci_enable_device(pdev); 190*c103de24SGrant Likely if (ret) { 191*c103de24SGrant Likely dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__); 192*c103de24SGrant Likely goto err_pci_enable; 193*c103de24SGrant Likely } 194*c103de24SGrant Likely 195*c103de24SGrant Likely ret = pci_request_regions(pdev, KBUILD_MODNAME); 196*c103de24SGrant Likely if (ret) { 197*c103de24SGrant Likely dev_err(&pdev->dev, "pci_request_regions failed-%d", ret); 198*c103de24SGrant Likely goto err_request_regions; 199*c103de24SGrant Likely } 200*c103de24SGrant Likely 201*c103de24SGrant Likely base = pci_iomap(pdev, 1, 0); 202*c103de24SGrant Likely if (base == 0) { 203*c103de24SGrant Likely dev_err(&pdev->dev, "%s : pci_iomap failed", __func__); 204*c103de24SGrant Likely ret = -ENOMEM; 205*c103de24SGrant Likely goto err_iomap; 206*c103de24SGrant Likely } 207*c103de24SGrant Likely 208*c103de24SGrant Likely chip_save = kzalloc(sizeof(*chip) * 8, GFP_KERNEL); 209*c103de24SGrant Likely if (chip_save == NULL) { 210*c103de24SGrant Likely dev_err(&pdev->dev, "%s : kzalloc failed", __func__); 211*c103de24SGrant Likely ret = -ENOMEM; 212*c103de24SGrant Likely goto err_kzalloc; 213*c103de24SGrant Likely } 214*c103de24SGrant Likely 215*c103de24SGrant Likely chip = chip_save; 216*c103de24SGrant Likely for (i = 0; i < 8; i++, chip++) { 217*c103de24SGrant Likely chip->dev = &pdev->dev; 218*c103de24SGrant Likely chip->base = base; 219*c103de24SGrant Likely chip->reg = chip->base; 220*c103de24SGrant Likely chip->ch = i; 221*c103de24SGrant Likely mutex_init(&chip->lock); 222*c103de24SGrant Likely ioh_gpio_setup(chip, num_ports[i]); 223*c103de24SGrant Likely ret = gpiochip_add(&chip->gpio); 224*c103de24SGrant Likely if (ret) { 225*c103de24SGrant Likely dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n"); 226*c103de24SGrant Likely goto err_gpiochip_add; 227*c103de24SGrant Likely } 228*c103de24SGrant Likely } 229*c103de24SGrant Likely 230*c103de24SGrant Likely chip = chip_save; 231*c103de24SGrant Likely pci_set_drvdata(pdev, chip); 232*c103de24SGrant Likely 233*c103de24SGrant Likely return 0; 234*c103de24SGrant Likely 235*c103de24SGrant Likely err_gpiochip_add: 236*c103de24SGrant Likely for (; i != 0; i--) { 237*c103de24SGrant Likely chip--; 238*c103de24SGrant Likely ret = gpiochip_remove(&chip->gpio); 239*c103de24SGrant Likely if (ret) 240*c103de24SGrant Likely dev_err(&pdev->dev, "Failed gpiochip_remove(%d)\n", i); 241*c103de24SGrant Likely } 242*c103de24SGrant Likely kfree(chip_save); 243*c103de24SGrant Likely 244*c103de24SGrant Likely err_kzalloc: 245*c103de24SGrant Likely pci_iounmap(pdev, base); 246*c103de24SGrant Likely 247*c103de24SGrant Likely err_iomap: 248*c103de24SGrant Likely pci_release_regions(pdev); 249*c103de24SGrant Likely 250*c103de24SGrant Likely err_request_regions: 251*c103de24SGrant Likely pci_disable_device(pdev); 252*c103de24SGrant Likely 253*c103de24SGrant Likely err_pci_enable: 254*c103de24SGrant Likely 255*c103de24SGrant Likely dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret); 256*c103de24SGrant Likely return ret; 257*c103de24SGrant Likely } 258*c103de24SGrant Likely 259*c103de24SGrant Likely static void __devexit ioh_gpio_remove(struct pci_dev *pdev) 260*c103de24SGrant Likely { 261*c103de24SGrant Likely int err; 262*c103de24SGrant Likely int i; 263*c103de24SGrant Likely struct ioh_gpio *chip = pci_get_drvdata(pdev); 264*c103de24SGrant Likely void __iomem *chip_save; 265*c103de24SGrant Likely 266*c103de24SGrant Likely chip_save = chip; 267*c103de24SGrant Likely for (i = 0; i < 8; i++, chip++) { 268*c103de24SGrant Likely err = gpiochip_remove(&chip->gpio); 269*c103de24SGrant Likely if (err) 270*c103de24SGrant Likely dev_err(&pdev->dev, "Failed gpiochip_remove\n"); 271*c103de24SGrant Likely } 272*c103de24SGrant Likely 273*c103de24SGrant Likely chip = chip_save; 274*c103de24SGrant Likely pci_iounmap(pdev, chip->base); 275*c103de24SGrant Likely pci_release_regions(pdev); 276*c103de24SGrant Likely pci_disable_device(pdev); 277*c103de24SGrant Likely kfree(chip); 278*c103de24SGrant Likely } 279*c103de24SGrant Likely 280*c103de24SGrant Likely #ifdef CONFIG_PM 281*c103de24SGrant Likely static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state) 282*c103de24SGrant Likely { 283*c103de24SGrant Likely s32 ret; 284*c103de24SGrant Likely struct ioh_gpio *chip = pci_get_drvdata(pdev); 285*c103de24SGrant Likely 286*c103de24SGrant Likely ioh_gpio_save_reg_conf(chip); 287*c103de24SGrant Likely ioh_gpio_restore_reg_conf(chip); 288*c103de24SGrant Likely 289*c103de24SGrant Likely ret = pci_save_state(pdev); 290*c103de24SGrant Likely if (ret) { 291*c103de24SGrant Likely dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret); 292*c103de24SGrant Likely return ret; 293*c103de24SGrant Likely } 294*c103de24SGrant Likely pci_disable_device(pdev); 295*c103de24SGrant Likely pci_set_power_state(pdev, PCI_D0); 296*c103de24SGrant Likely ret = pci_enable_wake(pdev, PCI_D0, 1); 297*c103de24SGrant Likely if (ret) 298*c103de24SGrant Likely dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret); 299*c103de24SGrant Likely 300*c103de24SGrant Likely return 0; 301*c103de24SGrant Likely } 302*c103de24SGrant Likely 303*c103de24SGrant Likely static int ioh_gpio_resume(struct pci_dev *pdev) 304*c103de24SGrant Likely { 305*c103de24SGrant Likely s32 ret; 306*c103de24SGrant Likely struct ioh_gpio *chip = pci_get_drvdata(pdev); 307*c103de24SGrant Likely 308*c103de24SGrant Likely ret = pci_enable_wake(pdev, PCI_D0, 0); 309*c103de24SGrant Likely 310*c103de24SGrant Likely pci_set_power_state(pdev, PCI_D0); 311*c103de24SGrant Likely ret = pci_enable_device(pdev); 312*c103de24SGrant Likely if (ret) { 313*c103de24SGrant Likely dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret); 314*c103de24SGrant Likely return ret; 315*c103de24SGrant Likely } 316*c103de24SGrant Likely pci_restore_state(pdev); 317*c103de24SGrant Likely 318*c103de24SGrant Likely iowrite32(0x01, &chip->reg->srst); 319*c103de24SGrant Likely iowrite32(0x00, &chip->reg->srst); 320*c103de24SGrant Likely ioh_gpio_restore_reg_conf(chip); 321*c103de24SGrant Likely 322*c103de24SGrant Likely return 0; 323*c103de24SGrant Likely } 324*c103de24SGrant Likely #else 325*c103de24SGrant Likely #define ioh_gpio_suspend NULL 326*c103de24SGrant Likely #define ioh_gpio_resume NULL 327*c103de24SGrant Likely #endif 328*c103de24SGrant Likely 329*c103de24SGrant Likely static DEFINE_PCI_DEVICE_TABLE(ioh_gpio_pcidev_id) = { 330*c103de24SGrant Likely { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) }, 331*c103de24SGrant Likely { 0, } 332*c103de24SGrant Likely }; 333*c103de24SGrant Likely MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id); 334*c103de24SGrant Likely 335*c103de24SGrant Likely static struct pci_driver ioh_gpio_driver = { 336*c103de24SGrant Likely .name = "ml_ioh_gpio", 337*c103de24SGrant Likely .id_table = ioh_gpio_pcidev_id, 338*c103de24SGrant Likely .probe = ioh_gpio_probe, 339*c103de24SGrant Likely .remove = __devexit_p(ioh_gpio_remove), 340*c103de24SGrant Likely .suspend = ioh_gpio_suspend, 341*c103de24SGrant Likely .resume = ioh_gpio_resume 342*c103de24SGrant Likely }; 343*c103de24SGrant Likely 344*c103de24SGrant Likely static int __init ioh_gpio_pci_init(void) 345*c103de24SGrant Likely { 346*c103de24SGrant Likely return pci_register_driver(&ioh_gpio_driver); 347*c103de24SGrant Likely } 348*c103de24SGrant Likely module_init(ioh_gpio_pci_init); 349*c103de24SGrant Likely 350*c103de24SGrant Likely static void __exit ioh_gpio_pci_exit(void) 351*c103de24SGrant Likely { 352*c103de24SGrant Likely pci_unregister_driver(&ioh_gpio_driver); 353*c103de24SGrant Likely } 354*c103de24SGrant Likely module_exit(ioh_gpio_pci_exit); 355*c103de24SGrant Likely 356*c103de24SGrant Likely MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver"); 357*c103de24SGrant Likely MODULE_LICENSE("GPL"); 358