1 /* 2 * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver 3 * 4 * Copyright (C) 2010 Extreme Engineering Solutions. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 22 23 #include <linux/ioport.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/gpio/driver.h> 27 #include <linux/platform_device.h> 28 #include <linux/mfd/lpc_ich.h> 29 #include <linux/bitops.h> 30 31 #define DRV_NAME "gpio_ich" 32 33 /* 34 * GPIO register offsets in GPIO I/O space. 35 * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and 36 * LVLx registers. Logic in the read/write functions takes a register and 37 * an absolute bit number and determines the proper register offset and bit 38 * number in that register. For example, to read the value of GPIO bit 50 39 * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)], 40 * bit 18 (50%32). 41 */ 42 enum GPIO_REG { 43 GPIO_USE_SEL = 0, 44 GPIO_IO_SEL, 45 GPIO_LVL, 46 GPO_BLINK 47 }; 48 49 static const u8 ichx_regs[4][3] = { 50 {0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */ 51 {0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */ 52 {0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */ 53 {0x18, 0x18, 0x18}, /* BLINK offset */ 54 }; 55 56 static const u8 ichx_reglen[3] = { 57 0x30, 0x10, 0x10, 58 }; 59 60 static const u8 avoton_regs[4][3] = { 61 {0x00, 0x80, 0x00}, 62 {0x04, 0x84, 0x00}, 63 {0x08, 0x88, 0x00}, 64 }; 65 66 static const u8 avoton_reglen[3] = { 67 0x10, 0x10, 0x00, 68 }; 69 70 #define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start) 71 #define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start) 72 73 struct ichx_desc { 74 /* Max GPIO pins the chipset can have */ 75 uint ngpio; 76 77 /* chipset registers */ 78 const u8 (*regs)[3]; 79 const u8 *reglen; 80 81 /* GPO_BLINK is available on this chipset */ 82 bool have_blink; 83 84 /* Whether the chipset has GPIO in GPE0_STS in the PM IO region */ 85 bool uses_gpe0; 86 87 /* USE_SEL is bogus on some chipsets, eg 3100 */ 88 u32 use_sel_ignore[3]; 89 90 /* Some chipsets have quirks, let these use their own request/get */ 91 int (*request)(struct gpio_chip *chip, unsigned offset); 92 int (*get)(struct gpio_chip *chip, unsigned offset); 93 94 /* 95 * Some chipsets don't let reading output values on GPIO_LVL register 96 * this option allows driver caching written output values 97 */ 98 bool use_outlvl_cache; 99 }; 100 101 static struct { 102 spinlock_t lock; 103 struct device *dev; 104 struct gpio_chip chip; 105 struct resource *gpio_base; /* GPIO IO base */ 106 struct resource *pm_base; /* Power Mangagment IO base */ 107 struct ichx_desc *desc; /* Pointer to chipset-specific description */ 108 u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */ 109 u8 use_gpio; /* Which GPIO groups are usable */ 110 int outlvl_cache[3]; /* cached output values */ 111 } ichx_priv; 112 113 static int modparam_gpiobase = -1; /* dynamic */ 114 module_param_named(gpiobase, modparam_gpiobase, int, 0444); 115 MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, " 116 "which is the default."); 117 118 static int ichx_write_bit(int reg, unsigned nr, int val, int verify) 119 { 120 unsigned long flags; 121 u32 data, tmp; 122 int reg_nr = nr / 32; 123 int bit = nr & 0x1f; 124 125 spin_lock_irqsave(&ichx_priv.lock, flags); 126 127 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache) 128 data = ichx_priv.outlvl_cache[reg_nr]; 129 else 130 data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], 131 ichx_priv.gpio_base); 132 133 if (val) 134 data |= BIT(bit); 135 else 136 data &= ~BIT(bit); 137 ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr], 138 ichx_priv.gpio_base); 139 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache) 140 ichx_priv.outlvl_cache[reg_nr] = data; 141 142 tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], 143 ichx_priv.gpio_base); 144 145 spin_unlock_irqrestore(&ichx_priv.lock, flags); 146 147 return (verify && data != tmp) ? -EPERM : 0; 148 } 149 150 static int ichx_read_bit(int reg, unsigned nr) 151 { 152 unsigned long flags; 153 u32 data; 154 int reg_nr = nr / 32; 155 int bit = nr & 0x1f; 156 157 spin_lock_irqsave(&ichx_priv.lock, flags); 158 159 data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], 160 ichx_priv.gpio_base); 161 162 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache) 163 data = ichx_priv.outlvl_cache[reg_nr] | data; 164 165 spin_unlock_irqrestore(&ichx_priv.lock, flags); 166 167 return !!(data & BIT(bit)); 168 } 169 170 static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr) 171 { 172 return !!(ichx_priv.use_gpio & BIT(nr / 32)); 173 } 174 175 static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned nr) 176 { 177 return ichx_read_bit(GPIO_IO_SEL, nr); 178 } 179 180 static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) 181 { 182 /* 183 * Try setting pin as an input and verify it worked since many pins 184 * are output-only. 185 */ 186 return ichx_write_bit(GPIO_IO_SEL, nr, 1, 1); 187 } 188 189 static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr, 190 int val) 191 { 192 /* Disable blink hardware which is available for GPIOs from 0 to 31. */ 193 if (nr < 32 && ichx_priv.desc->have_blink) 194 ichx_write_bit(GPO_BLINK, nr, 0, 0); 195 196 /* Set GPIO output value. */ 197 ichx_write_bit(GPIO_LVL, nr, val, 0); 198 199 /* 200 * Try setting pin as an output and verify it worked since many pins 201 * are input-only. 202 */ 203 return ichx_write_bit(GPIO_IO_SEL, nr, 0, 1); 204 } 205 206 static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr) 207 { 208 return ichx_read_bit(GPIO_LVL, nr); 209 } 210 211 static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr) 212 { 213 unsigned long flags; 214 u32 data; 215 216 /* 217 * GPI 0 - 15 need to be read from the power management registers on 218 * a ICH6/3100 bridge. 219 */ 220 if (nr < 16) { 221 if (!ichx_priv.pm_base) 222 return -ENXIO; 223 224 spin_lock_irqsave(&ichx_priv.lock, flags); 225 226 /* GPI 0 - 15 are latched, write 1 to clear*/ 227 ICHX_WRITE(BIT(16 + nr), 0, ichx_priv.pm_base); 228 data = ICHX_READ(0, ichx_priv.pm_base); 229 230 spin_unlock_irqrestore(&ichx_priv.lock, flags); 231 232 return !!((data >> 16) & BIT(nr)); 233 } else { 234 return ichx_gpio_get(chip, nr); 235 } 236 } 237 238 static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr) 239 { 240 if (!ichx_gpio_check_available(chip, nr)) 241 return -ENXIO; 242 243 /* 244 * Note we assume the BIOS properly set a bridge's USE value. Some 245 * chips (eg Intel 3100) have bogus USE values though, so first see if 246 * the chipset's USE value can be trusted for this specific bit. 247 * If it can't be trusted, assume that the pin can be used as a GPIO. 248 */ 249 if (ichx_priv.desc->use_sel_ignore[nr / 32] & BIT(nr & 0x1f)) 250 return 0; 251 252 return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV; 253 } 254 255 static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr) 256 { 257 /* 258 * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100 259 * bridge as they are controlled by USE register bits 0 and 1. See 260 * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for 261 * additional info. 262 */ 263 if (nr == 16 || nr == 17) 264 nr -= 16; 265 266 return ichx_gpio_request(chip, nr); 267 } 268 269 static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val) 270 { 271 ichx_write_bit(GPIO_LVL, nr, val, 0); 272 } 273 274 static void ichx_gpiolib_setup(struct gpio_chip *chip) 275 { 276 chip->owner = THIS_MODULE; 277 chip->label = DRV_NAME; 278 chip->parent = ichx_priv.dev; 279 280 /* Allow chip-specific overrides of request()/get() */ 281 chip->request = ichx_priv.desc->request ? 282 ichx_priv.desc->request : ichx_gpio_request; 283 chip->get = ichx_priv.desc->get ? 284 ichx_priv.desc->get : ichx_gpio_get; 285 286 chip->set = ichx_gpio_set; 287 chip->get_direction = ichx_gpio_get_direction; 288 chip->direction_input = ichx_gpio_direction_input; 289 chip->direction_output = ichx_gpio_direction_output; 290 chip->base = modparam_gpiobase; 291 chip->ngpio = ichx_priv.desc->ngpio; 292 chip->can_sleep = false; 293 chip->dbg_show = NULL; 294 } 295 296 /* ICH6-based, 631xesb-based */ 297 static struct ichx_desc ich6_desc = { 298 /* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */ 299 .request = ich6_gpio_request, 300 .get = ich6_gpio_get, 301 302 /* GPIO 0-15 are read in the GPE0_STS PM register */ 303 .uses_gpe0 = true, 304 305 .ngpio = 50, 306 .have_blink = true, 307 .regs = ichx_regs, 308 .reglen = ichx_reglen, 309 }; 310 311 /* Intel 3100 */ 312 static struct ichx_desc i3100_desc = { 313 /* 314 * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on 315 * the Intel 3100. See "Table 712. GPIO Summary Table" of 3100 316 * Datasheet for more info. 317 */ 318 .use_sel_ignore = {0x00130000, 0x00010000, 0x0}, 319 320 /* The 3100 needs fixups for GPIO 0 - 17 */ 321 .request = ich6_gpio_request, 322 .get = ich6_gpio_get, 323 324 /* GPIO 0-15 are read in the GPE0_STS PM register */ 325 .uses_gpe0 = true, 326 327 .ngpio = 50, 328 .regs = ichx_regs, 329 .reglen = ichx_reglen, 330 }; 331 332 /* ICH7 and ICH8-based */ 333 static struct ichx_desc ich7_desc = { 334 .ngpio = 50, 335 .have_blink = true, 336 .regs = ichx_regs, 337 .reglen = ichx_reglen, 338 }; 339 340 /* ICH9-based */ 341 static struct ichx_desc ich9_desc = { 342 .ngpio = 61, 343 .have_blink = true, 344 .regs = ichx_regs, 345 .reglen = ichx_reglen, 346 }; 347 348 /* ICH10-based - Consumer/corporate versions have different amount of GPIO */ 349 static struct ichx_desc ich10_cons_desc = { 350 .ngpio = 61, 351 .have_blink = true, 352 .regs = ichx_regs, 353 .reglen = ichx_reglen, 354 }; 355 static struct ichx_desc ich10_corp_desc = { 356 .ngpio = 72, 357 .have_blink = true, 358 .regs = ichx_regs, 359 .reglen = ichx_reglen, 360 }; 361 362 /* Intel 5 series, 6 series, 3400 series, and C200 series */ 363 static struct ichx_desc intel5_desc = { 364 .ngpio = 76, 365 .regs = ichx_regs, 366 .reglen = ichx_reglen, 367 }; 368 369 /* Avoton */ 370 static struct ichx_desc avoton_desc = { 371 /* Avoton has only 59 GPIOs, but we assume the first set of register 372 * (Core) has 32 instead of 31 to keep gpio-ich compliance 373 */ 374 .ngpio = 60, 375 .regs = avoton_regs, 376 .reglen = avoton_reglen, 377 .use_outlvl_cache = true, 378 }; 379 380 static int ichx_gpio_request_regions(struct device *dev, 381 struct resource *res_base, const char *name, u8 use_gpio) 382 { 383 int i; 384 385 if (!res_base || !res_base->start || !res_base->end) 386 return -ENODEV; 387 388 for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) { 389 if (!(use_gpio & BIT(i))) 390 continue; 391 if (!devm_request_region(dev, 392 res_base->start + ichx_priv.desc->regs[0][i], 393 ichx_priv.desc->reglen[i], name)) 394 return -EBUSY; 395 } 396 return 0; 397 } 398 399 static int ichx_gpio_probe(struct platform_device *pdev) 400 { 401 struct device *dev = &pdev->dev; 402 struct lpc_ich_info *ich_info = dev_get_platdata(dev); 403 struct resource *res_base, *res_pm; 404 int err; 405 406 if (!ich_info) 407 return -ENODEV; 408 409 switch (ich_info->gpio_version) { 410 case ICH_I3100_GPIO: 411 ichx_priv.desc = &i3100_desc; 412 break; 413 case ICH_V5_GPIO: 414 ichx_priv.desc = &intel5_desc; 415 break; 416 case ICH_V6_GPIO: 417 ichx_priv.desc = &ich6_desc; 418 break; 419 case ICH_V7_GPIO: 420 ichx_priv.desc = &ich7_desc; 421 break; 422 case ICH_V9_GPIO: 423 ichx_priv.desc = &ich9_desc; 424 break; 425 case ICH_V10CORP_GPIO: 426 ichx_priv.desc = &ich10_corp_desc; 427 break; 428 case ICH_V10CONS_GPIO: 429 ichx_priv.desc = &ich10_cons_desc; 430 break; 431 case AVOTON_GPIO: 432 ichx_priv.desc = &avoton_desc; 433 break; 434 default: 435 return -ENODEV; 436 } 437 438 ichx_priv.dev = dev; 439 spin_lock_init(&ichx_priv.lock); 440 441 res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO); 442 err = ichx_gpio_request_regions(dev, res_base, pdev->name, 443 ich_info->use_gpio); 444 if (err) 445 return err; 446 447 ichx_priv.gpio_base = res_base; 448 ichx_priv.use_gpio = ich_info->use_gpio; 449 450 /* 451 * If necessary, determine the I/O address of ACPI/power management 452 * registers which are needed to read the the GPE0 register for GPI pins 453 * 0 - 15 on some chipsets. 454 */ 455 if (!ichx_priv.desc->uses_gpe0) 456 goto init; 457 458 res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0); 459 if (!res_pm) { 460 pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n"); 461 goto init; 462 } 463 464 if (!devm_request_region(dev, res_pm->start, resource_size(res_pm), 465 pdev->name)) { 466 pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n"); 467 goto init; 468 } 469 470 ichx_priv.pm_base = res_pm; 471 472 init: 473 ichx_gpiolib_setup(&ichx_priv.chip); 474 err = gpiochip_add_data(&ichx_priv.chip, NULL); 475 if (err) { 476 pr_err("Failed to register GPIOs\n"); 477 return err; 478 } 479 480 pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base, 481 ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME); 482 483 return 0; 484 } 485 486 static int ichx_gpio_remove(struct platform_device *pdev) 487 { 488 gpiochip_remove(&ichx_priv.chip); 489 490 return 0; 491 } 492 493 static struct platform_driver ichx_gpio_driver = { 494 .driver = { 495 .name = DRV_NAME, 496 }, 497 .probe = ichx_gpio_probe, 498 .remove = ichx_gpio_remove, 499 }; 500 501 module_platform_driver(ichx_gpio_driver); 502 503 MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>"); 504 MODULE_DESCRIPTION("GPIO interface for Intel ICH series"); 505 MODULE_LICENSE("GPL"); 506 MODULE_ALIAS("platform:"DRV_NAME); 507