1 /* 2 * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver 3 * 4 * Copyright (C) 2010 Extreme Engineering Solutions. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 22 #include <linux/ioport.h> 23 #include <linux/module.h> 24 #include <linux/pci.h> 25 #include <linux/gpio/driver.h> 26 #include <linux/platform_device.h> 27 #include <linux/mfd/lpc_ich.h> 28 #include <linux/bitops.h> 29 30 #define DRV_NAME "gpio_ich" 31 32 /* 33 * GPIO register offsets in GPIO I/O space. 34 * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and 35 * LVLx registers. Logic in the read/write functions takes a register and 36 * an absolute bit number and determines the proper register offset and bit 37 * number in that register. For example, to read the value of GPIO bit 50 38 * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)], 39 * bit 18 (50%32). 40 */ 41 enum GPIO_REG { 42 GPIO_USE_SEL = 0, 43 GPIO_IO_SEL, 44 GPIO_LVL, 45 GPO_BLINK 46 }; 47 48 static const u8 ichx_regs[4][3] = { 49 {0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */ 50 {0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */ 51 {0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */ 52 {0x18, 0x18, 0x18}, /* BLINK offset */ 53 }; 54 55 static const u8 ichx_reglen[3] = { 56 0x30, 0x10, 0x10, 57 }; 58 59 static const u8 avoton_regs[4][3] = { 60 {0x00, 0x80, 0x00}, 61 {0x04, 0x84, 0x00}, 62 {0x08, 0x88, 0x00}, 63 }; 64 65 static const u8 avoton_reglen[3] = { 66 0x10, 0x10, 0x00, 67 }; 68 69 #define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start) 70 #define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start) 71 72 struct ichx_desc { 73 /* Max GPIO pins the chipset can have */ 74 uint ngpio; 75 76 /* chipset registers */ 77 const u8 (*regs)[3]; 78 const u8 *reglen; 79 80 /* GPO_BLINK is available on this chipset */ 81 bool have_blink; 82 83 /* Whether the chipset has GPIO in GPE0_STS in the PM IO region */ 84 bool uses_gpe0; 85 86 /* USE_SEL is bogus on some chipsets, eg 3100 */ 87 u32 use_sel_ignore[3]; 88 89 /* Some chipsets have quirks, let these use their own request/get */ 90 int (*request)(struct gpio_chip *chip, unsigned offset); 91 int (*get)(struct gpio_chip *chip, unsigned offset); 92 93 /* 94 * Some chipsets don't let reading output values on GPIO_LVL register 95 * this option allows driver caching written output values 96 */ 97 bool use_outlvl_cache; 98 }; 99 100 static struct { 101 spinlock_t lock; 102 struct device *dev; 103 struct gpio_chip chip; 104 struct resource *gpio_base; /* GPIO IO base */ 105 struct resource *pm_base; /* Power Mangagment IO base */ 106 struct ichx_desc *desc; /* Pointer to chipset-specific description */ 107 u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */ 108 u8 use_gpio; /* Which GPIO groups are usable */ 109 int outlvl_cache[3]; /* cached output values */ 110 } ichx_priv; 111 112 static int modparam_gpiobase = -1; /* dynamic */ 113 module_param_named(gpiobase, modparam_gpiobase, int, 0444); 114 MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, " 115 "which is the default."); 116 117 static int ichx_write_bit(int reg, unsigned nr, int val, int verify) 118 { 119 unsigned long flags; 120 u32 data, tmp; 121 int reg_nr = nr / 32; 122 int bit = nr & 0x1f; 123 124 spin_lock_irqsave(&ichx_priv.lock, flags); 125 126 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache) 127 data = ichx_priv.outlvl_cache[reg_nr]; 128 else 129 data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], 130 ichx_priv.gpio_base); 131 132 if (val) 133 data |= BIT(bit); 134 else 135 data &= ~BIT(bit); 136 ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr], 137 ichx_priv.gpio_base); 138 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache) 139 ichx_priv.outlvl_cache[reg_nr] = data; 140 141 tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], 142 ichx_priv.gpio_base); 143 144 spin_unlock_irqrestore(&ichx_priv.lock, flags); 145 146 return (verify && data != tmp) ? -EPERM : 0; 147 } 148 149 static int ichx_read_bit(int reg, unsigned nr) 150 { 151 unsigned long flags; 152 u32 data; 153 int reg_nr = nr / 32; 154 int bit = nr & 0x1f; 155 156 spin_lock_irqsave(&ichx_priv.lock, flags); 157 158 data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], 159 ichx_priv.gpio_base); 160 161 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache) 162 data = ichx_priv.outlvl_cache[reg_nr] | data; 163 164 spin_unlock_irqrestore(&ichx_priv.lock, flags); 165 166 return !!(data & BIT(bit)); 167 } 168 169 static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr) 170 { 171 return !!(ichx_priv.use_gpio & BIT(nr / 32)); 172 } 173 174 static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned nr) 175 { 176 return ichx_read_bit(GPIO_IO_SEL, nr); 177 } 178 179 static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) 180 { 181 /* 182 * Try setting pin as an input and verify it worked since many pins 183 * are output-only. 184 */ 185 return ichx_write_bit(GPIO_IO_SEL, nr, 1, 1); 186 } 187 188 static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr, 189 int val) 190 { 191 /* Disable blink hardware which is available for GPIOs from 0 to 31. */ 192 if (nr < 32 && ichx_priv.desc->have_blink) 193 ichx_write_bit(GPO_BLINK, nr, 0, 0); 194 195 /* Set GPIO output value. */ 196 ichx_write_bit(GPIO_LVL, nr, val, 0); 197 198 /* 199 * Try setting pin as an output and verify it worked since many pins 200 * are input-only. 201 */ 202 return ichx_write_bit(GPIO_IO_SEL, nr, 0, 1); 203 } 204 205 static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr) 206 { 207 return ichx_read_bit(GPIO_LVL, nr); 208 } 209 210 static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr) 211 { 212 unsigned long flags; 213 u32 data; 214 215 /* 216 * GPI 0 - 15 need to be read from the power management registers on 217 * a ICH6/3100 bridge. 218 */ 219 if (nr < 16) { 220 if (!ichx_priv.pm_base) 221 return -ENXIO; 222 223 spin_lock_irqsave(&ichx_priv.lock, flags); 224 225 /* GPI 0 - 15 are latched, write 1 to clear*/ 226 ICHX_WRITE(BIT(16 + nr), 0, ichx_priv.pm_base); 227 data = ICHX_READ(0, ichx_priv.pm_base); 228 229 spin_unlock_irqrestore(&ichx_priv.lock, flags); 230 231 return !!((data >> 16) & BIT(nr)); 232 } else { 233 return ichx_gpio_get(chip, nr); 234 } 235 } 236 237 static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr) 238 { 239 if (!ichx_gpio_check_available(chip, nr)) 240 return -ENXIO; 241 242 /* 243 * Note we assume the BIOS properly set a bridge's USE value. Some 244 * chips (eg Intel 3100) have bogus USE values though, so first see if 245 * the chipset's USE value can be trusted for this specific bit. 246 * If it can't be trusted, assume that the pin can be used as a GPIO. 247 */ 248 if (ichx_priv.desc->use_sel_ignore[nr / 32] & BIT(nr & 0x1f)) 249 return 0; 250 251 return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV; 252 } 253 254 static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr) 255 { 256 /* 257 * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100 258 * bridge as they are controlled by USE register bits 0 and 1. See 259 * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for 260 * additional info. 261 */ 262 if (nr == 16 || nr == 17) 263 nr -= 16; 264 265 return ichx_gpio_request(chip, nr); 266 } 267 268 static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val) 269 { 270 ichx_write_bit(GPIO_LVL, nr, val, 0); 271 } 272 273 static void ichx_gpiolib_setup(struct gpio_chip *chip) 274 { 275 chip->owner = THIS_MODULE; 276 chip->label = DRV_NAME; 277 chip->parent = ichx_priv.dev; 278 279 /* Allow chip-specific overrides of request()/get() */ 280 chip->request = ichx_priv.desc->request ? 281 ichx_priv.desc->request : ichx_gpio_request; 282 chip->get = ichx_priv.desc->get ? 283 ichx_priv.desc->get : ichx_gpio_get; 284 285 chip->set = ichx_gpio_set; 286 chip->get_direction = ichx_gpio_get_direction; 287 chip->direction_input = ichx_gpio_direction_input; 288 chip->direction_output = ichx_gpio_direction_output; 289 chip->base = modparam_gpiobase; 290 chip->ngpio = ichx_priv.desc->ngpio; 291 chip->can_sleep = false; 292 chip->dbg_show = NULL; 293 } 294 295 /* ICH6-based, 631xesb-based */ 296 static struct ichx_desc ich6_desc = { 297 /* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */ 298 .request = ich6_gpio_request, 299 .get = ich6_gpio_get, 300 301 /* GPIO 0-15 are read in the GPE0_STS PM register */ 302 .uses_gpe0 = true, 303 304 .ngpio = 50, 305 .have_blink = true, 306 .regs = ichx_regs, 307 .reglen = ichx_reglen, 308 }; 309 310 /* Intel 3100 */ 311 static struct ichx_desc i3100_desc = { 312 /* 313 * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on 314 * the Intel 3100. See "Table 712. GPIO Summary Table" of 3100 315 * Datasheet for more info. 316 */ 317 .use_sel_ignore = {0x00130000, 0x00010000, 0x0}, 318 319 /* The 3100 needs fixups for GPIO 0 - 17 */ 320 .request = ich6_gpio_request, 321 .get = ich6_gpio_get, 322 323 /* GPIO 0-15 are read in the GPE0_STS PM register */ 324 .uses_gpe0 = true, 325 326 .ngpio = 50, 327 .regs = ichx_regs, 328 .reglen = ichx_reglen, 329 }; 330 331 /* ICH7 and ICH8-based */ 332 static struct ichx_desc ich7_desc = { 333 .ngpio = 50, 334 .have_blink = true, 335 .regs = ichx_regs, 336 .reglen = ichx_reglen, 337 }; 338 339 /* ICH9-based */ 340 static struct ichx_desc ich9_desc = { 341 .ngpio = 61, 342 .have_blink = true, 343 .regs = ichx_regs, 344 .reglen = ichx_reglen, 345 }; 346 347 /* ICH10-based - Consumer/corporate versions have different amount of GPIO */ 348 static struct ichx_desc ich10_cons_desc = { 349 .ngpio = 61, 350 .have_blink = true, 351 .regs = ichx_regs, 352 .reglen = ichx_reglen, 353 }; 354 static struct ichx_desc ich10_corp_desc = { 355 .ngpio = 72, 356 .have_blink = true, 357 .regs = ichx_regs, 358 .reglen = ichx_reglen, 359 }; 360 361 /* Intel 5 series, 6 series, 3400 series, and C200 series */ 362 static struct ichx_desc intel5_desc = { 363 .ngpio = 76, 364 .regs = ichx_regs, 365 .reglen = ichx_reglen, 366 }; 367 368 /* Avoton */ 369 static struct ichx_desc avoton_desc = { 370 /* Avoton has only 59 GPIOs, but we assume the first set of register 371 * (Core) has 32 instead of 31 to keep gpio-ich compliance 372 */ 373 .ngpio = 60, 374 .regs = avoton_regs, 375 .reglen = avoton_reglen, 376 .use_outlvl_cache = true, 377 }; 378 379 static int ichx_gpio_request_regions(struct device *dev, 380 struct resource *res_base, const char *name, u8 use_gpio) 381 { 382 int i; 383 384 if (!res_base || !res_base->start || !res_base->end) 385 return -ENODEV; 386 387 for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) { 388 if (!(use_gpio & BIT(i))) 389 continue; 390 if (!devm_request_region(dev, 391 res_base->start + ichx_priv.desc->regs[0][i], 392 ichx_priv.desc->reglen[i], name)) 393 return -EBUSY; 394 } 395 return 0; 396 } 397 398 static int ichx_gpio_probe(struct platform_device *pdev) 399 { 400 struct device *dev = &pdev->dev; 401 struct lpc_ich_info *ich_info = dev_get_platdata(dev); 402 struct resource *res_base, *res_pm; 403 int err; 404 405 if (!ich_info) 406 return -ENODEV; 407 408 switch (ich_info->gpio_version) { 409 case ICH_I3100_GPIO: 410 ichx_priv.desc = &i3100_desc; 411 break; 412 case ICH_V5_GPIO: 413 ichx_priv.desc = &intel5_desc; 414 break; 415 case ICH_V6_GPIO: 416 ichx_priv.desc = &ich6_desc; 417 break; 418 case ICH_V7_GPIO: 419 ichx_priv.desc = &ich7_desc; 420 break; 421 case ICH_V9_GPIO: 422 ichx_priv.desc = &ich9_desc; 423 break; 424 case ICH_V10CORP_GPIO: 425 ichx_priv.desc = &ich10_corp_desc; 426 break; 427 case ICH_V10CONS_GPIO: 428 ichx_priv.desc = &ich10_cons_desc; 429 break; 430 case AVOTON_GPIO: 431 ichx_priv.desc = &avoton_desc; 432 break; 433 default: 434 return -ENODEV; 435 } 436 437 ichx_priv.dev = dev; 438 spin_lock_init(&ichx_priv.lock); 439 440 res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO); 441 err = ichx_gpio_request_regions(dev, res_base, pdev->name, 442 ich_info->use_gpio); 443 if (err) 444 return err; 445 446 ichx_priv.gpio_base = res_base; 447 ichx_priv.use_gpio = ich_info->use_gpio; 448 449 /* 450 * If necessary, determine the I/O address of ACPI/power management 451 * registers which are needed to read the the GPE0 register for GPI pins 452 * 0 - 15 on some chipsets. 453 */ 454 if (!ichx_priv.desc->uses_gpe0) 455 goto init; 456 457 res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0); 458 if (!res_pm) { 459 dev_warn(dev, "ACPI BAR is unavailable, GPI 0 - 15 unavailable\n"); 460 goto init; 461 } 462 463 if (!devm_request_region(dev, res_pm->start, resource_size(res_pm), 464 pdev->name)) { 465 dev_warn(dev, "ACPI BAR is busy, GPI 0 - 15 unavailable\n"); 466 goto init; 467 } 468 469 ichx_priv.pm_base = res_pm; 470 471 init: 472 ichx_gpiolib_setup(&ichx_priv.chip); 473 err = gpiochip_add_data(&ichx_priv.chip, NULL); 474 if (err) { 475 dev_err(dev, "Failed to register GPIOs\n"); 476 return err; 477 } 478 479 dev_info(dev, "GPIO from %d to %d\n", ichx_priv.chip.base, 480 ichx_priv.chip.base + ichx_priv.chip.ngpio - 1); 481 482 return 0; 483 } 484 485 static int ichx_gpio_remove(struct platform_device *pdev) 486 { 487 gpiochip_remove(&ichx_priv.chip); 488 489 return 0; 490 } 491 492 static struct platform_driver ichx_gpio_driver = { 493 .driver = { 494 .name = DRV_NAME, 495 }, 496 .probe = ichx_gpio_probe, 497 .remove = ichx_gpio_remove, 498 }; 499 500 module_platform_driver(ichx_gpio_driver); 501 502 MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>"); 503 MODULE_DESCRIPTION("GPIO interface for Intel ICH series"); 504 MODULE_LICENSE("GPL"); 505 MODULE_ALIAS("platform:"DRV_NAME); 506