1 /* 2 * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver 3 * 4 * Copyright (C) 2010 Extreme Engineering Solutions. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 22 #include <linux/bitops.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/ioport.h> 25 #include <linux/mfd/lpc_ich.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include <linux/platform_device.h> 29 30 #define DRV_NAME "gpio_ich" 31 32 /* 33 * GPIO register offsets in GPIO I/O space. 34 * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and 35 * LVLx registers. Logic in the read/write functions takes a register and 36 * an absolute bit number and determines the proper register offset and bit 37 * number in that register. For example, to read the value of GPIO bit 50 38 * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)], 39 * bit 18 (50%32). 40 */ 41 enum GPIO_REG { 42 GPIO_USE_SEL = 0, 43 GPIO_IO_SEL, 44 GPIO_LVL, 45 GPO_BLINK 46 }; 47 48 static const u8 ichx_regs[4][3] = { 49 {0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */ 50 {0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */ 51 {0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */ 52 {0x18, 0x18, 0x18}, /* BLINK offset */ 53 }; 54 55 static const u8 ichx_reglen[3] = { 56 0x30, 0x10, 0x10, 57 }; 58 59 static const u8 avoton_regs[4][3] = { 60 {0x00, 0x80, 0x00}, 61 {0x04, 0x84, 0x00}, 62 {0x08, 0x88, 0x00}, 63 }; 64 65 static const u8 avoton_reglen[3] = { 66 0x10, 0x10, 0x00, 67 }; 68 69 #define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start) 70 #define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start) 71 72 struct ichx_desc { 73 /* Max GPIO pins the chipset can have */ 74 uint ngpio; 75 76 /* chipset registers */ 77 const u8 (*regs)[3]; 78 const u8 *reglen; 79 80 /* GPO_BLINK is available on this chipset */ 81 bool have_blink; 82 83 /* Whether the chipset has GPIO in GPE0_STS in the PM IO region */ 84 bool uses_gpe0; 85 86 /* USE_SEL is bogus on some chipsets, eg 3100 */ 87 u32 use_sel_ignore[3]; 88 89 /* Some chipsets have quirks, let these use their own request/get */ 90 int (*request)(struct gpio_chip *chip, unsigned offset); 91 int (*get)(struct gpio_chip *chip, unsigned offset); 92 93 /* 94 * Some chipsets don't let reading output values on GPIO_LVL register 95 * this option allows driver caching written output values 96 */ 97 bool use_outlvl_cache; 98 }; 99 100 static struct { 101 spinlock_t lock; 102 struct device *dev; 103 struct gpio_chip chip; 104 struct resource *gpio_base; /* GPIO IO base */ 105 struct resource *pm_base; /* Power Mangagment IO base */ 106 struct ichx_desc *desc; /* Pointer to chipset-specific description */ 107 u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */ 108 u8 use_gpio; /* Which GPIO groups are usable */ 109 int outlvl_cache[3]; /* cached output values */ 110 } ichx_priv; 111 112 static int modparam_gpiobase = -1; /* dynamic */ 113 module_param_named(gpiobase, modparam_gpiobase, int, 0444); 114 MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, which is the default."); 115 116 static int ichx_write_bit(int reg, unsigned nr, int val, int verify) 117 { 118 unsigned long flags; 119 u32 data, tmp; 120 int reg_nr = nr / 32; 121 int bit = nr & 0x1f; 122 123 spin_lock_irqsave(&ichx_priv.lock, flags); 124 125 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache) 126 data = ichx_priv.outlvl_cache[reg_nr]; 127 else 128 data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], 129 ichx_priv.gpio_base); 130 131 if (val) 132 data |= BIT(bit); 133 else 134 data &= ~BIT(bit); 135 ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr], 136 ichx_priv.gpio_base); 137 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache) 138 ichx_priv.outlvl_cache[reg_nr] = data; 139 140 tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], 141 ichx_priv.gpio_base); 142 143 spin_unlock_irqrestore(&ichx_priv.lock, flags); 144 145 return (verify && data != tmp) ? -EPERM : 0; 146 } 147 148 static int ichx_read_bit(int reg, unsigned nr) 149 { 150 unsigned long flags; 151 u32 data; 152 int reg_nr = nr / 32; 153 int bit = nr & 0x1f; 154 155 spin_lock_irqsave(&ichx_priv.lock, flags); 156 157 data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], 158 ichx_priv.gpio_base); 159 160 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache) 161 data = ichx_priv.outlvl_cache[reg_nr] | data; 162 163 spin_unlock_irqrestore(&ichx_priv.lock, flags); 164 165 return !!(data & BIT(bit)); 166 } 167 168 static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr) 169 { 170 return !!(ichx_priv.use_gpio & BIT(nr / 32)); 171 } 172 173 static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned nr) 174 { 175 return ichx_read_bit(GPIO_IO_SEL, nr); 176 } 177 178 static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) 179 { 180 /* 181 * Try setting pin as an input and verify it worked since many pins 182 * are output-only. 183 */ 184 return ichx_write_bit(GPIO_IO_SEL, nr, 1, 1); 185 } 186 187 static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr, 188 int val) 189 { 190 /* Disable blink hardware which is available for GPIOs from 0 to 31. */ 191 if (nr < 32 && ichx_priv.desc->have_blink) 192 ichx_write_bit(GPO_BLINK, nr, 0, 0); 193 194 /* Set GPIO output value. */ 195 ichx_write_bit(GPIO_LVL, nr, val, 0); 196 197 /* 198 * Try setting pin as an output and verify it worked since many pins 199 * are input-only. 200 */ 201 return ichx_write_bit(GPIO_IO_SEL, nr, 0, 1); 202 } 203 204 static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr) 205 { 206 return ichx_read_bit(GPIO_LVL, nr); 207 } 208 209 static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr) 210 { 211 unsigned long flags; 212 u32 data; 213 214 /* 215 * GPI 0 - 15 need to be read from the power management registers on 216 * a ICH6/3100 bridge. 217 */ 218 if (nr < 16) { 219 if (!ichx_priv.pm_base) 220 return -ENXIO; 221 222 spin_lock_irqsave(&ichx_priv.lock, flags); 223 224 /* GPI 0 - 15 are latched, write 1 to clear*/ 225 ICHX_WRITE(BIT(16 + nr), 0, ichx_priv.pm_base); 226 data = ICHX_READ(0, ichx_priv.pm_base); 227 228 spin_unlock_irqrestore(&ichx_priv.lock, flags); 229 230 return !!((data >> 16) & BIT(nr)); 231 } else { 232 return ichx_gpio_get(chip, nr); 233 } 234 } 235 236 static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr) 237 { 238 if (!ichx_gpio_check_available(chip, nr)) 239 return -ENXIO; 240 241 /* 242 * Note we assume the BIOS properly set a bridge's USE value. Some 243 * chips (eg Intel 3100) have bogus USE values though, so first see if 244 * the chipset's USE value can be trusted for this specific bit. 245 * If it can't be trusted, assume that the pin can be used as a GPIO. 246 */ 247 if (ichx_priv.desc->use_sel_ignore[nr / 32] & BIT(nr & 0x1f)) 248 return 0; 249 250 return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV; 251 } 252 253 static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr) 254 { 255 /* 256 * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100 257 * bridge as they are controlled by USE register bits 0 and 1. See 258 * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for 259 * additional info. 260 */ 261 if (nr == 16 || nr == 17) 262 nr -= 16; 263 264 return ichx_gpio_request(chip, nr); 265 } 266 267 static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val) 268 { 269 ichx_write_bit(GPIO_LVL, nr, val, 0); 270 } 271 272 static void ichx_gpiolib_setup(struct gpio_chip *chip) 273 { 274 chip->owner = THIS_MODULE; 275 chip->label = DRV_NAME; 276 chip->parent = ichx_priv.dev; 277 278 /* Allow chip-specific overrides of request()/get() */ 279 chip->request = ichx_priv.desc->request ? 280 ichx_priv.desc->request : ichx_gpio_request; 281 chip->get = ichx_priv.desc->get ? 282 ichx_priv.desc->get : ichx_gpio_get; 283 284 chip->set = ichx_gpio_set; 285 chip->get_direction = ichx_gpio_get_direction; 286 chip->direction_input = ichx_gpio_direction_input; 287 chip->direction_output = ichx_gpio_direction_output; 288 chip->base = modparam_gpiobase; 289 chip->ngpio = ichx_priv.desc->ngpio; 290 chip->can_sleep = false; 291 chip->dbg_show = NULL; 292 } 293 294 /* ICH6-based, 631xesb-based */ 295 static struct ichx_desc ich6_desc = { 296 /* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */ 297 .request = ich6_gpio_request, 298 .get = ich6_gpio_get, 299 300 /* GPIO 0-15 are read in the GPE0_STS PM register */ 301 .uses_gpe0 = true, 302 303 .ngpio = 50, 304 .have_blink = true, 305 .regs = ichx_regs, 306 .reglen = ichx_reglen, 307 }; 308 309 /* Intel 3100 */ 310 static struct ichx_desc i3100_desc = { 311 /* 312 * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on 313 * the Intel 3100. See "Table 712. GPIO Summary Table" of 3100 314 * Datasheet for more info. 315 */ 316 .use_sel_ignore = {0x00130000, 0x00010000, 0x0}, 317 318 /* The 3100 needs fixups for GPIO 0 - 17 */ 319 .request = ich6_gpio_request, 320 .get = ich6_gpio_get, 321 322 /* GPIO 0-15 are read in the GPE0_STS PM register */ 323 .uses_gpe0 = true, 324 325 .ngpio = 50, 326 .regs = ichx_regs, 327 .reglen = ichx_reglen, 328 }; 329 330 /* ICH7 and ICH8-based */ 331 static struct ichx_desc ich7_desc = { 332 .ngpio = 50, 333 .have_blink = true, 334 .regs = ichx_regs, 335 .reglen = ichx_reglen, 336 }; 337 338 /* ICH9-based */ 339 static struct ichx_desc ich9_desc = { 340 .ngpio = 61, 341 .have_blink = true, 342 .regs = ichx_regs, 343 .reglen = ichx_reglen, 344 }; 345 346 /* ICH10-based - Consumer/corporate versions have different amount of GPIO */ 347 static struct ichx_desc ich10_cons_desc = { 348 .ngpio = 61, 349 .have_blink = true, 350 .regs = ichx_regs, 351 .reglen = ichx_reglen, 352 }; 353 static struct ichx_desc ich10_corp_desc = { 354 .ngpio = 72, 355 .have_blink = true, 356 .regs = ichx_regs, 357 .reglen = ichx_reglen, 358 }; 359 360 /* Intel 5 series, 6 series, 3400 series, and C200 series */ 361 static struct ichx_desc intel5_desc = { 362 .ngpio = 76, 363 .regs = ichx_regs, 364 .reglen = ichx_reglen, 365 }; 366 367 /* Avoton */ 368 static struct ichx_desc avoton_desc = { 369 /* Avoton has only 59 GPIOs, but we assume the first set of register 370 * (Core) has 32 instead of 31 to keep gpio-ich compliance 371 */ 372 .ngpio = 60, 373 .regs = avoton_regs, 374 .reglen = avoton_reglen, 375 .use_outlvl_cache = true, 376 }; 377 378 static int ichx_gpio_request_regions(struct device *dev, 379 struct resource *res_base, const char *name, u8 use_gpio) 380 { 381 int i; 382 383 if (!res_base || !res_base->start || !res_base->end) 384 return -ENODEV; 385 386 for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) { 387 if (!(use_gpio & BIT(i))) 388 continue; 389 if (!devm_request_region(dev, 390 res_base->start + ichx_priv.desc->regs[0][i], 391 ichx_priv.desc->reglen[i], name)) 392 return -EBUSY; 393 } 394 return 0; 395 } 396 397 static int ichx_gpio_probe(struct platform_device *pdev) 398 { 399 struct device *dev = &pdev->dev; 400 struct lpc_ich_info *ich_info = dev_get_platdata(dev); 401 struct resource *res_base, *res_pm; 402 int err; 403 404 if (!ich_info) 405 return -ENODEV; 406 407 switch (ich_info->gpio_version) { 408 case ICH_I3100_GPIO: 409 ichx_priv.desc = &i3100_desc; 410 break; 411 case ICH_V5_GPIO: 412 ichx_priv.desc = &intel5_desc; 413 break; 414 case ICH_V6_GPIO: 415 ichx_priv.desc = &ich6_desc; 416 break; 417 case ICH_V7_GPIO: 418 ichx_priv.desc = &ich7_desc; 419 break; 420 case ICH_V9_GPIO: 421 ichx_priv.desc = &ich9_desc; 422 break; 423 case ICH_V10CORP_GPIO: 424 ichx_priv.desc = &ich10_corp_desc; 425 break; 426 case ICH_V10CONS_GPIO: 427 ichx_priv.desc = &ich10_cons_desc; 428 break; 429 case AVOTON_GPIO: 430 ichx_priv.desc = &avoton_desc; 431 break; 432 default: 433 return -ENODEV; 434 } 435 436 ichx_priv.dev = dev; 437 spin_lock_init(&ichx_priv.lock); 438 439 res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO); 440 err = ichx_gpio_request_regions(dev, res_base, pdev->name, 441 ich_info->use_gpio); 442 if (err) 443 return err; 444 445 ichx_priv.gpio_base = res_base; 446 ichx_priv.use_gpio = ich_info->use_gpio; 447 448 /* 449 * If necessary, determine the I/O address of ACPI/power management 450 * registers which are needed to read the GPE0 register for GPI pins 451 * 0 - 15 on some chipsets. 452 */ 453 if (!ichx_priv.desc->uses_gpe0) 454 goto init; 455 456 res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0); 457 if (!res_pm) { 458 dev_warn(dev, "ACPI BAR is unavailable, GPI 0 - 15 unavailable\n"); 459 goto init; 460 } 461 462 if (!devm_request_region(dev, res_pm->start, resource_size(res_pm), 463 pdev->name)) { 464 dev_warn(dev, "ACPI BAR is busy, GPI 0 - 15 unavailable\n"); 465 goto init; 466 } 467 468 ichx_priv.pm_base = res_pm; 469 470 init: 471 ichx_gpiolib_setup(&ichx_priv.chip); 472 err = gpiochip_add_data(&ichx_priv.chip, NULL); 473 if (err) { 474 dev_err(dev, "Failed to register GPIOs\n"); 475 return err; 476 } 477 478 dev_info(dev, "GPIO from %d to %d\n", ichx_priv.chip.base, 479 ichx_priv.chip.base + ichx_priv.chip.ngpio - 1); 480 481 return 0; 482 } 483 484 static int ichx_gpio_remove(struct platform_device *pdev) 485 { 486 gpiochip_remove(&ichx_priv.chip); 487 488 return 0; 489 } 490 491 static struct platform_driver ichx_gpio_driver = { 492 .driver = { 493 .name = DRV_NAME, 494 }, 495 .probe = ichx_gpio_probe, 496 .remove = ichx_gpio_remove, 497 }; 498 499 module_platform_driver(ichx_gpio_driver); 500 501 MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>"); 502 MODULE_DESCRIPTION("GPIO interface for Intel ICH series"); 503 MODULE_LICENSE("GPL"); 504 MODULE_ALIAS("platform:"DRV_NAME); 505