xref: /openbmc/linux/drivers/edac/amd76x_edac.c (revision b8f6f9755248026f21282e25cac49a1af698056c)
1806c35f5SAlan Cox /*
2806c35f5SAlan Cox  * AMD 76x Memory Controller kernel module
3806c35f5SAlan Cox  * (C) 2003 Linux Networx (http://lnxi.com)
4806c35f5SAlan Cox  * This file may be distributed under the terms of the
5806c35f5SAlan Cox  * GNU General Public License.
6806c35f5SAlan Cox  *
7806c35f5SAlan Cox  * Written by Thayne Harbaugh
8806c35f5SAlan Cox  * Based on work by Dan Hollis <goemon at anime dot net> and others.
9806c35f5SAlan Cox  *	http://www.anime.net/~goemon/linux-ecc/
10806c35f5SAlan Cox  *
11806c35f5SAlan Cox  * $Id: edac_amd76x.c,v 1.4.2.5 2005/10/05 00:43:44 dsp_llnl Exp $
12806c35f5SAlan Cox  *
13806c35f5SAlan Cox  */
14806c35f5SAlan Cox 
15806c35f5SAlan Cox #include <linux/module.h>
16806c35f5SAlan Cox #include <linux/init.h>
17806c35f5SAlan Cox #include <linux/pci.h>
18806c35f5SAlan Cox #include <linux/pci_ids.h>
19806c35f5SAlan Cox #include <linux/slab.h>
2020bcb7a8SDouglas Thompson #include "edac_core.h"
21806c35f5SAlan Cox 
2220bcb7a8SDouglas Thompson #define AMD76X_REVISION	" Ver: 2.0.2 "  __DATE__
23929a40ecSDoug Thompson #define EDAC_MOD_STR	"amd76x_edac"
2437f04581SDoug Thompson 
25537fba28SDave Peterson #define amd76x_printk(level, fmt, arg...) \
26537fba28SDave Peterson 	edac_printk(level, "amd76x", fmt, ##arg)
27537fba28SDave Peterson 
28537fba28SDave Peterson #define amd76x_mc_printk(mci, level, fmt, arg...) \
29537fba28SDave Peterson 	edac_mc_chipset_printk(mci, level, "amd76x", fmt, ##arg)
30537fba28SDave Peterson 
31806c35f5SAlan Cox #define AMD76X_NR_CSROWS 8
32806c35f5SAlan Cox #define AMD76X_NR_CHANS  1
33806c35f5SAlan Cox #define AMD76X_NR_DIMMS  4
34806c35f5SAlan Cox 
35806c35f5SAlan Cox /* AMD 76x register addresses - device 0 function 0 - PCI bridge */
36e7ecd891SDave Peterson 
37806c35f5SAlan Cox #define AMD76X_ECC_MODE_STATUS	0x48	/* Mode and status of ECC (32b)
38806c35f5SAlan Cox 					 *
39806c35f5SAlan Cox 					 * 31:16 reserved
40806c35f5SAlan Cox 					 * 15:14 SERR enabled: x1=ue 1x=ce
41806c35f5SAlan Cox 					 * 13    reserved
42806c35f5SAlan Cox 					 * 12    diag: disabled, enabled
43806c35f5SAlan Cox 					 * 11:10 mode: dis, EC, ECC, ECC+scrub
44806c35f5SAlan Cox 					 *  9:8  status: x1=ue 1x=ce
45806c35f5SAlan Cox 					 *  7:4  UE cs row
46806c35f5SAlan Cox 					 *  3:0  CE cs row
47806c35f5SAlan Cox 					 */
48e7ecd891SDave Peterson 
49806c35f5SAlan Cox #define AMD76X_DRAM_MODE_STATUS	0x58	/* DRAM Mode and status (32b)
50806c35f5SAlan Cox 					 *
51806c35f5SAlan Cox 					 * 31:26 clock disable 5 - 0
52806c35f5SAlan Cox 					 * 25    SDRAM init
53806c35f5SAlan Cox 					 * 24    reserved
54806c35f5SAlan Cox 					 * 23    mode register service
55806c35f5SAlan Cox 					 * 22:21 suspend to RAM
56806c35f5SAlan Cox 					 * 20    burst refresh enable
57806c35f5SAlan Cox 					 * 19    refresh disable
58806c35f5SAlan Cox 					 * 18    reserved
59806c35f5SAlan Cox 					 * 17:16 cycles-per-refresh
60806c35f5SAlan Cox 					 * 15:8  reserved
61806c35f5SAlan Cox 					 *  7:0  x4 mode enable 7 - 0
62806c35f5SAlan Cox 					 */
63e7ecd891SDave Peterson 
64806c35f5SAlan Cox #define AMD76X_MEM_BASE_ADDR	0xC0	/* Memory base address (8 x 32b)
65806c35f5SAlan Cox 					 *
66806c35f5SAlan Cox 					 * 31:23 chip-select base
67806c35f5SAlan Cox 					 * 22:16 reserved
68806c35f5SAlan Cox 					 * 15:7  chip-select mask
69806c35f5SAlan Cox 					 *  6:3  reserved
70806c35f5SAlan Cox 					 *  2:1  address mode
71806c35f5SAlan Cox 					 *  0    chip-select enable
72806c35f5SAlan Cox 					 */
73806c35f5SAlan Cox 
74806c35f5SAlan Cox struct amd76x_error_info {
75806c35f5SAlan Cox 	u32 ecc_mode_status;
76806c35f5SAlan Cox };
77806c35f5SAlan Cox 
78806c35f5SAlan Cox enum amd76x_chips {
79806c35f5SAlan Cox 	AMD761 = 0,
80806c35f5SAlan Cox 	AMD762
81806c35f5SAlan Cox };
82806c35f5SAlan Cox 
83806c35f5SAlan Cox struct amd76x_dev_info {
84806c35f5SAlan Cox 	const char *ctl_name;
85806c35f5SAlan Cox };
86806c35f5SAlan Cox 
87806c35f5SAlan Cox static const struct amd76x_dev_info amd76x_devs[] = {
88e7ecd891SDave Peterson 	[AMD761] = {
8967cb2b61SDouglas Thompson 		.ctl_name = "AMD761"},
90e7ecd891SDave Peterson 	[AMD762] = {
9167cb2b61SDouglas Thompson 		.ctl_name = "AMD762"},
92806c35f5SAlan Cox };
93806c35f5SAlan Cox 
94456a2f95SDave Jiang static struct edac_pci_ctl_info *amd76x_pci;
95456a2f95SDave Jiang 
96806c35f5SAlan Cox /**
97806c35f5SAlan Cox  *	amd76x_get_error_info	-	fetch error information
98806c35f5SAlan Cox  *	@mci: Memory controller
99806c35f5SAlan Cox  *	@info: Info to fill in
100806c35f5SAlan Cox  *
101806c35f5SAlan Cox  *	Fetch and store the AMD76x ECC status. Clear pending status
102806c35f5SAlan Cox  *	on the chip so that further errors will be reported
103806c35f5SAlan Cox  */
104806c35f5SAlan Cox static void amd76x_get_error_info(struct mem_ctl_info *mci,
105806c35f5SAlan Cox 				struct amd76x_error_info *info)
106806c35f5SAlan Cox {
10737f04581SDoug Thompson 	struct pci_dev *pdev;
10837f04581SDoug Thompson 
10937f04581SDoug Thompson 	pdev = to_pci_dev(mci->dev);
11037f04581SDoug Thompson 	pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS,
111806c35f5SAlan Cox 			&info->ecc_mode_status);
112806c35f5SAlan Cox 
113806c35f5SAlan Cox 	if (info->ecc_mode_status & BIT(8))
11437f04581SDoug Thompson 		pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
115806c35f5SAlan Cox 				 (u32) BIT(8), (u32) BIT(8));
116806c35f5SAlan Cox 
117806c35f5SAlan Cox 	if (info->ecc_mode_status & BIT(9))
11837f04581SDoug Thompson 		pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
119806c35f5SAlan Cox 				 (u32) BIT(9), (u32) BIT(9));
120806c35f5SAlan Cox }
121806c35f5SAlan Cox 
122806c35f5SAlan Cox /**
123806c35f5SAlan Cox  *	amd76x_process_error_info	-	Error check
124806c35f5SAlan Cox  *	@mci: Memory controller
125806c35f5SAlan Cox  *	@info: Previously fetched information from chip
126806c35f5SAlan Cox  *	@handle_errors: 1 if we should do recovery
127806c35f5SAlan Cox  *
128806c35f5SAlan Cox  *	Process the chip state and decide if an error has occurred.
129806c35f5SAlan Cox  *	A return of 1 indicates an error. Also if handle_errors is true
130806c35f5SAlan Cox  *	then attempt to handle and clean up after the error
131806c35f5SAlan Cox  */
132806c35f5SAlan Cox static int amd76x_process_error_info(struct mem_ctl_info *mci,
13367cb2b61SDouglas Thompson 				struct amd76x_error_info *info,
13467cb2b61SDouglas Thompson 				int handle_errors)
135806c35f5SAlan Cox {
136806c35f5SAlan Cox 	int error_found;
137806c35f5SAlan Cox 	u32 row;
138806c35f5SAlan Cox 
139806c35f5SAlan Cox 	error_found = 0;
140806c35f5SAlan Cox 
141806c35f5SAlan Cox 	/*
142806c35f5SAlan Cox 	 *      Check for an uncorrectable error
143806c35f5SAlan Cox 	 */
144806c35f5SAlan Cox 	if (info->ecc_mode_status & BIT(8)) {
145806c35f5SAlan Cox 		error_found = 1;
146806c35f5SAlan Cox 
147806c35f5SAlan Cox 		if (handle_errors) {
148806c35f5SAlan Cox 			row = (info->ecc_mode_status >> 4) & 0xf;
149e7ecd891SDave Peterson 			edac_mc_handle_ue(mci, mci->csrows[row].first_page, 0,
150e7ecd891SDave Peterson 					row, mci->ctl_name);
151806c35f5SAlan Cox 		}
152806c35f5SAlan Cox 	}
153806c35f5SAlan Cox 
154806c35f5SAlan Cox 	/*
155806c35f5SAlan Cox 	 *      Check for a correctable error
156806c35f5SAlan Cox 	 */
157806c35f5SAlan Cox 	if (info->ecc_mode_status & BIT(9)) {
158806c35f5SAlan Cox 		error_found = 1;
159806c35f5SAlan Cox 
160806c35f5SAlan Cox 		if (handle_errors) {
161806c35f5SAlan Cox 			row = info->ecc_mode_status & 0xf;
162e7ecd891SDave Peterson 			edac_mc_handle_ce(mci, mci->csrows[row].first_page, 0,
163e7ecd891SDave Peterson 					0, row, 0, mci->ctl_name);
164806c35f5SAlan Cox 		}
165806c35f5SAlan Cox 	}
166e7ecd891SDave Peterson 
167806c35f5SAlan Cox 	return error_found;
168806c35f5SAlan Cox }
169806c35f5SAlan Cox 
170806c35f5SAlan Cox /**
171806c35f5SAlan Cox  *	amd76x_check	-	Poll the controller
172806c35f5SAlan Cox  *	@mci: Memory controller
173806c35f5SAlan Cox  *
174806c35f5SAlan Cox  *	Called by the poll handlers this function reads the status
175806c35f5SAlan Cox  *	from the controller and checks for errors.
176806c35f5SAlan Cox  */
177806c35f5SAlan Cox static void amd76x_check(struct mem_ctl_info *mci)
178806c35f5SAlan Cox {
179806c35f5SAlan Cox 	struct amd76x_error_info info;
180537fba28SDave Peterson 	debugf3("%s()\n", __func__);
181806c35f5SAlan Cox 	amd76x_get_error_info(mci, &info);
182806c35f5SAlan Cox 	amd76x_process_error_info(mci, &info, 1);
183806c35f5SAlan Cox }
184806c35f5SAlan Cox 
18513189525SDoug Thompson static void amd76x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
18613189525SDoug Thompson 			enum edac_type edac_mode)
187806c35f5SAlan Cox {
18813189525SDoug Thompson 	struct csrow_info *csrow;
18913189525SDoug Thompson 	u32 mba, mba_base, mba_mask, dms;
190806c35f5SAlan Cox 	int index;
191806c35f5SAlan Cox 
192806c35f5SAlan Cox 	for (index = 0; index < mci->nr_csrows; index++) {
19313189525SDoug Thompson 		csrow = &mci->csrows[index];
194806c35f5SAlan Cox 
195806c35f5SAlan Cox 		/* find the DRAM Chip Select Base address and mask */
19637f04581SDoug Thompson 		pci_read_config_dword(pdev,
19767cb2b61SDouglas Thompson 				AMD76X_MEM_BASE_ADDR + (index * 4), &mba);
198806c35f5SAlan Cox 
199806c35f5SAlan Cox 		if (!(mba & BIT(0)))
200806c35f5SAlan Cox 			continue;
201806c35f5SAlan Cox 
202806c35f5SAlan Cox 		mba_base = mba & 0xff800000UL;
203806c35f5SAlan Cox 		mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL;
20437f04581SDoug Thompson 		pci_read_config_dword(pdev, AMD76X_DRAM_MODE_STATUS, &dms);
205806c35f5SAlan Cox 		csrow->first_page = mba_base >> PAGE_SHIFT;
206806c35f5SAlan Cox 		csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
207806c35f5SAlan Cox 		csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
208806c35f5SAlan Cox 		csrow->page_mask = mba_mask >> PAGE_SHIFT;
209806c35f5SAlan Cox 		csrow->grain = csrow->nr_pages << PAGE_SHIFT;
210806c35f5SAlan Cox 		csrow->mtype = MEM_RDDR;
211806c35f5SAlan Cox 		csrow->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
21213189525SDoug Thompson 		csrow->edac_mode = edac_mode;
21313189525SDoug Thompson 	}
214806c35f5SAlan Cox }
215806c35f5SAlan Cox 
21613189525SDoug Thompson /**
21713189525SDoug Thompson  *	amd76x_probe1	-	Perform set up for detected device
21813189525SDoug Thompson  *	@pdev; PCI device detected
21913189525SDoug Thompson  *	@dev_idx: Device type index
22013189525SDoug Thompson  *
22113189525SDoug Thompson  *	We have found an AMD76x and now need to set up the memory
22213189525SDoug Thompson  *	controller status reporting. We configure and set up the
22313189525SDoug Thompson  *	memory controller reporting and claim the device.
22413189525SDoug Thompson  */
22513189525SDoug Thompson static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
22613189525SDoug Thompson {
22713189525SDoug Thompson 	static const enum edac_type ems_modes[] = {
22813189525SDoug Thompson 		EDAC_NONE,
22913189525SDoug Thompson 		EDAC_EC,
23013189525SDoug Thompson 		EDAC_SECDED,
23113189525SDoug Thompson 		EDAC_SECDED
23213189525SDoug Thompson 	};
23313189525SDoug Thompson 	struct mem_ctl_info *mci = NULL;
23413189525SDoug Thompson 	u32 ems;
23513189525SDoug Thompson 	u32 ems_mode;
23613189525SDoug Thompson 	struct amd76x_error_info discard;
23713189525SDoug Thompson 
23813189525SDoug Thompson 	debugf0("%s()\n", __func__);
23913189525SDoug Thompson 	pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems);
24013189525SDoug Thompson 	ems_mode = (ems >> 10) & 0x3;
241*b8f6f975SDoug Thompson 	mci = edac_mc_alloc(0, AMD76X_NR_CSROWS, AMD76X_NR_CHANS, 0);
24213189525SDoug Thompson 
24313189525SDoug Thompson 	if (mci == NULL) {
24413189525SDoug Thompson 		return -ENOMEM;
24513189525SDoug Thompson 	}
24613189525SDoug Thompson 
24713189525SDoug Thompson 	debugf0("%s(): mci = %p\n", __func__, mci);
24813189525SDoug Thompson 	mci->dev = &pdev->dev;
24913189525SDoug Thompson 	mci->mtype_cap = MEM_FLAG_RDDR;
25013189525SDoug Thompson 	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
25113189525SDoug Thompson 	mci->edac_cap = ems_mode ?
25213189525SDoug Thompson 		(EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE;
25313189525SDoug Thompson 	mci->mod_name = EDAC_MOD_STR;
25413189525SDoug Thompson 	mci->mod_ver = AMD76X_REVISION;
25513189525SDoug Thompson 	mci->ctl_name = amd76x_devs[dev_idx].ctl_name;
256c4192705SDave Jiang 	mci->dev_name = pci_name(pdev);
25713189525SDoug Thompson 	mci->edac_check = amd76x_check;
25813189525SDoug Thompson 	mci->ctl_page_to_phys = NULL;
25913189525SDoug Thompson 
26013189525SDoug Thompson 	amd76x_init_csrows(mci, pdev, ems_modes[ems_mode]);
261749ede57SDave Peterson 	amd76x_get_error_info(mci, &discard);	/* clear counters */
262806c35f5SAlan Cox 
2632d7bbb91SDoug Thompson 	/* Here we assume that we will never see multiple instances of this
2642d7bbb91SDoug Thompson 	 * type of memory controller.  The ID is therefore hardcoded to 0.
2652d7bbb91SDoug Thompson 	 */
266*b8f6f975SDoug Thompson 	if (edac_mc_add_mc(mci)) {
267537fba28SDave Peterson 		debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
268806c35f5SAlan Cox 		goto fail;
269806c35f5SAlan Cox 	}
270806c35f5SAlan Cox 
271456a2f95SDave Jiang 	/* allocating generic PCI control info */
272456a2f95SDave Jiang 	amd76x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
273456a2f95SDave Jiang 	if (!amd76x_pci) {
274456a2f95SDave Jiang 		printk(KERN_WARNING
275456a2f95SDave Jiang 			"%s(): Unable to create PCI control\n",
276456a2f95SDave Jiang 			__func__);
277456a2f95SDave Jiang 		printk(KERN_WARNING
278456a2f95SDave Jiang 			"%s(): PCI error report via EDAC not setup\n",
279456a2f95SDave Jiang 			__func__);
280456a2f95SDave Jiang 	}
281456a2f95SDave Jiang 
282806c35f5SAlan Cox 	/* get this far and it's successful */
283537fba28SDave Peterson 	debugf3("%s(): success\n", __func__);
284806c35f5SAlan Cox 	return 0;
285806c35f5SAlan Cox 
286806c35f5SAlan Cox fail:
287806c35f5SAlan Cox 	edac_mc_free(mci);
28813189525SDoug Thompson 	return -ENODEV;
289806c35f5SAlan Cox }
290806c35f5SAlan Cox 
291806c35f5SAlan Cox /* returns count (>= 0), or negative on error */
292806c35f5SAlan Cox static int __devinit amd76x_init_one(struct pci_dev *pdev,
293806c35f5SAlan Cox 				const struct pci_device_id *ent)
294806c35f5SAlan Cox {
295537fba28SDave Peterson 	debugf0("%s()\n", __func__);
296806c35f5SAlan Cox 
297806c35f5SAlan Cox 	/* don't need to call pci_device_enable() */
298806c35f5SAlan Cox 	return amd76x_probe1(pdev, ent->driver_data);
299806c35f5SAlan Cox }
300806c35f5SAlan Cox 
301806c35f5SAlan Cox /**
302806c35f5SAlan Cox  *	amd76x_remove_one	-	driver shutdown
303806c35f5SAlan Cox  *	@pdev: PCI device being handed back
304806c35f5SAlan Cox  *
305806c35f5SAlan Cox  *	Called when the driver is unloaded. Find the matching mci
306806c35f5SAlan Cox  *	structure for the device then delete the mci and free the
307806c35f5SAlan Cox  *	resources.
308806c35f5SAlan Cox  */
309806c35f5SAlan Cox static void __devexit amd76x_remove_one(struct pci_dev *pdev)
310806c35f5SAlan Cox {
311806c35f5SAlan Cox 	struct mem_ctl_info *mci;
312806c35f5SAlan Cox 
313537fba28SDave Peterson 	debugf0("%s()\n", __func__);
314806c35f5SAlan Cox 
315456a2f95SDave Jiang 	if (amd76x_pci)
316456a2f95SDave Jiang 		edac_pci_release_generic_ctl(amd76x_pci);
317456a2f95SDave Jiang 
31837f04581SDoug Thompson 	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
319806c35f5SAlan Cox 		return;
32018dbc337SDave Peterson 
321806c35f5SAlan Cox 	edac_mc_free(mci);
322806c35f5SAlan Cox }
323806c35f5SAlan Cox 
324806c35f5SAlan Cox static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = {
325e7ecd891SDave Peterson 	{
326e7ecd891SDave Peterson 	 PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
32767cb2b61SDouglas Thompson 	 AMD762},
328e7ecd891SDave Peterson 	{
329e7ecd891SDave Peterson 	 PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
33067cb2b61SDouglas Thompson 	 AMD761},
331e7ecd891SDave Peterson 	{
332e7ecd891SDave Peterson 	 0,
333e7ecd891SDave Peterson 	 }			/* 0 terminated list. */
334806c35f5SAlan Cox };
335806c35f5SAlan Cox 
336806c35f5SAlan Cox MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl);
337806c35f5SAlan Cox 
338806c35f5SAlan Cox static struct pci_driver amd76x_driver = {
339680cbbbbSDave Peterson 	.name = EDAC_MOD_STR,
340806c35f5SAlan Cox 	.probe = amd76x_init_one,
341806c35f5SAlan Cox 	.remove = __devexit_p(amd76x_remove_one),
342806c35f5SAlan Cox 	.id_table = amd76x_pci_tbl,
343806c35f5SAlan Cox };
344806c35f5SAlan Cox 
345da9bb1d2SAlan Cox static int __init amd76x_init(void)
346806c35f5SAlan Cox {
347806c35f5SAlan Cox 	return pci_register_driver(&amd76x_driver);
348806c35f5SAlan Cox }
349806c35f5SAlan Cox 
350806c35f5SAlan Cox static void __exit amd76x_exit(void)
351806c35f5SAlan Cox {
352806c35f5SAlan Cox 	pci_unregister_driver(&amd76x_driver);
353806c35f5SAlan Cox }
354806c35f5SAlan Cox 
355806c35f5SAlan Cox module_init(amd76x_init);
356806c35f5SAlan Cox module_exit(amd76x_exit);
357806c35f5SAlan Cox 
358806c35f5SAlan Cox MODULE_LICENSE("GPL");
359806c35f5SAlan Cox MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
360806c35f5SAlan Cox MODULE_DESCRIPTION("MC support for AMD 76x memory controllers");
361