1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DMA driver for Xilinx Video DMA Engine 4 * 5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved. 6 * 7 * Based on the Freescale DMA driver. 8 * 9 * Description: 10 * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP 11 * core that provides high-bandwidth direct memory access between memory 12 * and AXI4-Stream type video target peripherals. The core provides efficient 13 * two dimensional DMA operations with independent asynchronous read (S2MM) 14 * and write (MM2S) channel operation. It can be configured to have either 15 * one channel or two channels. If configured as two channels, one is to 16 * transmit to the video device (MM2S) and another is to receive from the 17 * video device (S2MM). Initialization, status, interrupt and management 18 * registers are accessed through an AXI4-Lite slave interface. 19 * 20 * The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core that 21 * provides high-bandwidth one dimensional direct memory access between memory 22 * and AXI4-Stream target peripherals. It supports one receive and one 23 * transmit channel, both of them optional at synthesis time. 24 * 25 * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory 26 * Access (DMA) between a memory-mapped source address and a memory-mapped 27 * destination address. 28 * 29 * The AXI Multichannel Direct Memory Access (AXI MCDMA) core is a soft 30 * Xilinx IP that provides high-bandwidth direct memory access between 31 * memory and AXI4-Stream target peripherals. It provides scatter gather 32 * (SG) interface with multiple channels independent configuration support. 33 * 34 */ 35 36 #include <linux/bitops.h> 37 #include <linux/dmapool.h> 38 #include <linux/dma/xilinx_dma.h> 39 #include <linux/init.h> 40 #include <linux/interrupt.h> 41 #include <linux/io.h> 42 #include <linux/iopoll.h> 43 #include <linux/module.h> 44 #include <linux/of.h> 45 #include <linux/of_dma.h> 46 #include <linux/of_irq.h> 47 #include <linux/platform_device.h> 48 #include <linux/slab.h> 49 #include <linux/clk.h> 50 #include <linux/io-64-nonatomic-lo-hi.h> 51 52 #include "../dmaengine.h" 53 54 /* Register/Descriptor Offsets */ 55 #define XILINX_DMA_MM2S_CTRL_OFFSET 0x0000 56 #define XILINX_DMA_S2MM_CTRL_OFFSET 0x0030 57 #define XILINX_VDMA_MM2S_DESC_OFFSET 0x0050 58 #define XILINX_VDMA_S2MM_DESC_OFFSET 0x00a0 59 60 /* Control Registers */ 61 #define XILINX_DMA_REG_DMACR 0x0000 62 #define XILINX_DMA_DMACR_DELAY_MAX 0xff 63 #define XILINX_DMA_DMACR_DELAY_SHIFT 24 64 #define XILINX_DMA_DMACR_FRAME_COUNT_MAX 0xff 65 #define XILINX_DMA_DMACR_FRAME_COUNT_SHIFT 16 66 #define XILINX_DMA_DMACR_ERR_IRQ BIT(14) 67 #define XILINX_DMA_DMACR_DLY_CNT_IRQ BIT(13) 68 #define XILINX_DMA_DMACR_FRM_CNT_IRQ BIT(12) 69 #define XILINX_DMA_DMACR_MASTER_SHIFT 8 70 #define XILINX_DMA_DMACR_FSYNCSRC_SHIFT 5 71 #define XILINX_DMA_DMACR_FRAMECNT_EN BIT(4) 72 #define XILINX_DMA_DMACR_GENLOCK_EN BIT(3) 73 #define XILINX_DMA_DMACR_RESET BIT(2) 74 #define XILINX_DMA_DMACR_CIRC_EN BIT(1) 75 #define XILINX_DMA_DMACR_RUNSTOP BIT(0) 76 #define XILINX_DMA_DMACR_FSYNCSRC_MASK GENMASK(6, 5) 77 #define XILINX_DMA_DMACR_DELAY_MASK GENMASK(31, 24) 78 #define XILINX_DMA_DMACR_FRAME_COUNT_MASK GENMASK(23, 16) 79 #define XILINX_DMA_DMACR_MASTER_MASK GENMASK(11, 8) 80 81 #define XILINX_DMA_REG_DMASR 0x0004 82 #define XILINX_DMA_DMASR_EOL_LATE_ERR BIT(15) 83 #define XILINX_DMA_DMASR_ERR_IRQ BIT(14) 84 #define XILINX_DMA_DMASR_DLY_CNT_IRQ BIT(13) 85 #define XILINX_DMA_DMASR_FRM_CNT_IRQ BIT(12) 86 #define XILINX_DMA_DMASR_SOF_LATE_ERR BIT(11) 87 #define XILINX_DMA_DMASR_SG_DEC_ERR BIT(10) 88 #define XILINX_DMA_DMASR_SG_SLV_ERR BIT(9) 89 #define XILINX_DMA_DMASR_EOF_EARLY_ERR BIT(8) 90 #define XILINX_DMA_DMASR_SOF_EARLY_ERR BIT(7) 91 #define XILINX_DMA_DMASR_DMA_DEC_ERR BIT(6) 92 #define XILINX_DMA_DMASR_DMA_SLAVE_ERR BIT(5) 93 #define XILINX_DMA_DMASR_DMA_INT_ERR BIT(4) 94 #define XILINX_DMA_DMASR_SG_MASK BIT(3) 95 #define XILINX_DMA_DMASR_IDLE BIT(1) 96 #define XILINX_DMA_DMASR_HALTED BIT(0) 97 #define XILINX_DMA_DMASR_DELAY_MASK GENMASK(31, 24) 98 #define XILINX_DMA_DMASR_FRAME_COUNT_MASK GENMASK(23, 16) 99 100 #define XILINX_DMA_REG_CURDESC 0x0008 101 #define XILINX_DMA_REG_TAILDESC 0x0010 102 #define XILINX_DMA_REG_REG_INDEX 0x0014 103 #define XILINX_DMA_REG_FRMSTORE 0x0018 104 #define XILINX_DMA_REG_THRESHOLD 0x001c 105 #define XILINX_DMA_REG_FRMPTR_STS 0x0024 106 #define XILINX_DMA_REG_PARK_PTR 0x0028 107 #define XILINX_DMA_PARK_PTR_WR_REF_SHIFT 8 108 #define XILINX_DMA_PARK_PTR_WR_REF_MASK GENMASK(12, 8) 109 #define XILINX_DMA_PARK_PTR_RD_REF_SHIFT 0 110 #define XILINX_DMA_PARK_PTR_RD_REF_MASK GENMASK(4, 0) 111 #define XILINX_DMA_REG_VDMA_VERSION 0x002c 112 113 /* Register Direct Mode Registers */ 114 #define XILINX_DMA_REG_VSIZE 0x0000 115 #define XILINX_DMA_REG_HSIZE 0x0004 116 117 #define XILINX_DMA_REG_FRMDLY_STRIDE 0x0008 118 #define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT 24 119 #define XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT 0 120 121 #define XILINX_VDMA_REG_START_ADDRESS(n) (0x000c + 4 * (n)) 122 #define XILINX_VDMA_REG_START_ADDRESS_64(n) (0x000c + 8 * (n)) 123 124 #define XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP 0x00ec 125 #define XILINX_VDMA_ENABLE_VERTICAL_FLIP BIT(0) 126 127 /* HW specific definitions */ 128 #define XILINX_MCDMA_MAX_CHANS_PER_DEVICE 0x20 129 #define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x2 130 #define XILINX_CDMA_MAX_CHANS_PER_DEVICE 0x1 131 132 #define XILINX_DMA_DMAXR_ALL_IRQ_MASK \ 133 (XILINX_DMA_DMASR_FRM_CNT_IRQ | \ 134 XILINX_DMA_DMASR_DLY_CNT_IRQ | \ 135 XILINX_DMA_DMASR_ERR_IRQ) 136 137 #define XILINX_DMA_DMASR_ALL_ERR_MASK \ 138 (XILINX_DMA_DMASR_EOL_LATE_ERR | \ 139 XILINX_DMA_DMASR_SOF_LATE_ERR | \ 140 XILINX_DMA_DMASR_SG_DEC_ERR | \ 141 XILINX_DMA_DMASR_SG_SLV_ERR | \ 142 XILINX_DMA_DMASR_EOF_EARLY_ERR | \ 143 XILINX_DMA_DMASR_SOF_EARLY_ERR | \ 144 XILINX_DMA_DMASR_DMA_DEC_ERR | \ 145 XILINX_DMA_DMASR_DMA_SLAVE_ERR | \ 146 XILINX_DMA_DMASR_DMA_INT_ERR) 147 148 /* 149 * Recoverable errors are DMA Internal error, SOF Early, EOF Early 150 * and SOF Late. They are only recoverable when C_FLUSH_ON_FSYNC 151 * is enabled in the h/w system. 152 */ 153 #define XILINX_DMA_DMASR_ERR_RECOVER_MASK \ 154 (XILINX_DMA_DMASR_SOF_LATE_ERR | \ 155 XILINX_DMA_DMASR_EOF_EARLY_ERR | \ 156 XILINX_DMA_DMASR_SOF_EARLY_ERR | \ 157 XILINX_DMA_DMASR_DMA_INT_ERR) 158 159 /* Axi VDMA Flush on Fsync bits */ 160 #define XILINX_DMA_FLUSH_S2MM 3 161 #define XILINX_DMA_FLUSH_MM2S 2 162 #define XILINX_DMA_FLUSH_BOTH 1 163 164 /* Delay loop counter to prevent hardware failure */ 165 #define XILINX_DMA_LOOP_COUNT 1000000 166 167 /* AXI DMA Specific Registers/Offsets */ 168 #define XILINX_DMA_REG_SRCDSTADDR 0x18 169 #define XILINX_DMA_REG_BTT 0x28 170 171 /* AXI DMA Specific Masks/Bit fields */ 172 #define XILINX_DMA_MAX_TRANS_LEN_MIN 8 173 #define XILINX_DMA_MAX_TRANS_LEN_MAX 23 174 #define XILINX_DMA_V2_MAX_TRANS_LEN_MAX 26 175 #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16) 176 #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4) 177 #define XILINX_DMA_CR_COALESCE_SHIFT 16 178 #define XILINX_DMA_BD_SOP BIT(27) 179 #define XILINX_DMA_BD_EOP BIT(26) 180 #define XILINX_DMA_BD_COMP_MASK BIT(31) 181 #define XILINX_DMA_COALESCE_MAX 255 182 #define XILINX_DMA_NUM_DESCS 512 183 #define XILINX_DMA_NUM_APP_WORDS 5 184 185 /* AXI CDMA Specific Registers/Offsets */ 186 #define XILINX_CDMA_REG_SRCADDR 0x18 187 #define XILINX_CDMA_REG_DSTADDR 0x20 188 189 /* AXI CDMA Specific Masks */ 190 #define XILINX_CDMA_CR_SGMODE BIT(3) 191 192 #define xilinx_prep_dma_addr_t(addr) \ 193 ((dma_addr_t)((u64)addr##_##msb << 32 | (addr))) 194 195 /* AXI MCDMA Specific Registers/Offsets */ 196 #define XILINX_MCDMA_MM2S_CTRL_OFFSET 0x0000 197 #define XILINX_MCDMA_S2MM_CTRL_OFFSET 0x0500 198 #define XILINX_MCDMA_CHEN_OFFSET 0x0008 199 #define XILINX_MCDMA_CH_ERR_OFFSET 0x0010 200 #define XILINX_MCDMA_RXINT_SER_OFFSET 0x0020 201 #define XILINX_MCDMA_TXINT_SER_OFFSET 0x0028 202 #define XILINX_MCDMA_CHAN_CR_OFFSET(x) (0x40 + (x) * 0x40) 203 #define XILINX_MCDMA_CHAN_SR_OFFSET(x) (0x44 + (x) * 0x40) 204 #define XILINX_MCDMA_CHAN_CDESC_OFFSET(x) (0x48 + (x) * 0x40) 205 #define XILINX_MCDMA_CHAN_TDESC_OFFSET(x) (0x50 + (x) * 0x40) 206 207 /* AXI MCDMA Specific Masks/Shifts */ 208 #define XILINX_MCDMA_COALESCE_SHIFT 16 209 #define XILINX_MCDMA_COALESCE_MAX 24 210 #define XILINX_MCDMA_IRQ_ALL_MASK GENMASK(7, 5) 211 #define XILINX_MCDMA_COALESCE_MASK GENMASK(23, 16) 212 #define XILINX_MCDMA_CR_RUNSTOP_MASK BIT(0) 213 #define XILINX_MCDMA_IRQ_IOC_MASK BIT(5) 214 #define XILINX_MCDMA_IRQ_DELAY_MASK BIT(6) 215 #define XILINX_MCDMA_IRQ_ERR_MASK BIT(7) 216 #define XILINX_MCDMA_BD_EOP BIT(30) 217 #define XILINX_MCDMA_BD_SOP BIT(31) 218 219 /** 220 * struct xilinx_vdma_desc_hw - Hardware Descriptor 221 * @next_desc: Next Descriptor Pointer @0x00 222 * @pad1: Reserved @0x04 223 * @buf_addr: Buffer address @0x08 224 * @buf_addr_msb: MSB of Buffer address @0x0C 225 * @vsize: Vertical Size @0x10 226 * @hsize: Horizontal Size @0x14 227 * @stride: Number of bytes between the first 228 * pixels of each horizontal line @0x18 229 */ 230 struct xilinx_vdma_desc_hw { 231 u32 next_desc; 232 u32 pad1; 233 u32 buf_addr; 234 u32 buf_addr_msb; 235 u32 vsize; 236 u32 hsize; 237 u32 stride; 238 } __aligned(64); 239 240 /** 241 * struct xilinx_axidma_desc_hw - Hardware Descriptor for AXI DMA 242 * @next_desc: Next Descriptor Pointer @0x00 243 * @next_desc_msb: MSB of Next Descriptor Pointer @0x04 244 * @buf_addr: Buffer address @0x08 245 * @buf_addr_msb: MSB of Buffer address @0x0C 246 * @reserved1: Reserved @0x10 247 * @reserved2: Reserved @0x14 248 * @control: Control field @0x18 249 * @status: Status field @0x1C 250 * @app: APP Fields @0x20 - 0x30 251 */ 252 struct xilinx_axidma_desc_hw { 253 u32 next_desc; 254 u32 next_desc_msb; 255 u32 buf_addr; 256 u32 buf_addr_msb; 257 u32 reserved1; 258 u32 reserved2; 259 u32 control; 260 u32 status; 261 u32 app[XILINX_DMA_NUM_APP_WORDS]; 262 } __aligned(64); 263 264 /** 265 * struct xilinx_aximcdma_desc_hw - Hardware Descriptor for AXI MCDMA 266 * @next_desc: Next Descriptor Pointer @0x00 267 * @next_desc_msb: MSB of Next Descriptor Pointer @0x04 268 * @buf_addr: Buffer address @0x08 269 * @buf_addr_msb: MSB of Buffer address @0x0C 270 * @rsvd: Reserved field @0x10 271 * @control: Control Information field @0x14 272 * @status: Status field @0x18 273 * @sideband_status: Status of sideband signals @0x1C 274 * @app: APP Fields @0x20 - 0x30 275 */ 276 struct xilinx_aximcdma_desc_hw { 277 u32 next_desc; 278 u32 next_desc_msb; 279 u32 buf_addr; 280 u32 buf_addr_msb; 281 u32 rsvd; 282 u32 control; 283 u32 status; 284 u32 sideband_status; 285 u32 app[XILINX_DMA_NUM_APP_WORDS]; 286 } __aligned(64); 287 288 /** 289 * struct xilinx_cdma_desc_hw - Hardware Descriptor 290 * @next_desc: Next Descriptor Pointer @0x00 291 * @next_desc_msb: Next Descriptor Pointer MSB @0x04 292 * @src_addr: Source address @0x08 293 * @src_addr_msb: Source address MSB @0x0C 294 * @dest_addr: Destination address @0x10 295 * @dest_addr_msb: Destination address MSB @0x14 296 * @control: Control field @0x18 297 * @status: Status field @0x1C 298 */ 299 struct xilinx_cdma_desc_hw { 300 u32 next_desc; 301 u32 next_desc_msb; 302 u32 src_addr; 303 u32 src_addr_msb; 304 u32 dest_addr; 305 u32 dest_addr_msb; 306 u32 control; 307 u32 status; 308 } __aligned(64); 309 310 /** 311 * struct xilinx_vdma_tx_segment - Descriptor segment 312 * @hw: Hardware descriptor 313 * @node: Node in the descriptor segments list 314 * @phys: Physical address of segment 315 */ 316 struct xilinx_vdma_tx_segment { 317 struct xilinx_vdma_desc_hw hw; 318 struct list_head node; 319 dma_addr_t phys; 320 } __aligned(64); 321 322 /** 323 * struct xilinx_axidma_tx_segment - Descriptor segment 324 * @hw: Hardware descriptor 325 * @node: Node in the descriptor segments list 326 * @phys: Physical address of segment 327 */ 328 struct xilinx_axidma_tx_segment { 329 struct xilinx_axidma_desc_hw hw; 330 struct list_head node; 331 dma_addr_t phys; 332 } __aligned(64); 333 334 /** 335 * struct xilinx_aximcdma_tx_segment - Descriptor segment 336 * @hw: Hardware descriptor 337 * @node: Node in the descriptor segments list 338 * @phys: Physical address of segment 339 */ 340 struct xilinx_aximcdma_tx_segment { 341 struct xilinx_aximcdma_desc_hw hw; 342 struct list_head node; 343 dma_addr_t phys; 344 } __aligned(64); 345 346 /** 347 * struct xilinx_cdma_tx_segment - Descriptor segment 348 * @hw: Hardware descriptor 349 * @node: Node in the descriptor segments list 350 * @phys: Physical address of segment 351 */ 352 struct xilinx_cdma_tx_segment { 353 struct xilinx_cdma_desc_hw hw; 354 struct list_head node; 355 dma_addr_t phys; 356 } __aligned(64); 357 358 /** 359 * struct xilinx_dma_tx_descriptor - Per Transaction structure 360 * @async_tx: Async transaction descriptor 361 * @segments: TX segments list 362 * @node: Node in the channel descriptors list 363 * @cyclic: Check for cyclic transfers. 364 * @err: Whether the descriptor has an error. 365 * @residue: Residue of the completed descriptor 366 */ 367 struct xilinx_dma_tx_descriptor { 368 struct dma_async_tx_descriptor async_tx; 369 struct list_head segments; 370 struct list_head node; 371 bool cyclic; 372 bool err; 373 u32 residue; 374 }; 375 376 /** 377 * struct xilinx_dma_chan - Driver specific DMA channel structure 378 * @xdev: Driver specific device structure 379 * @ctrl_offset: Control registers offset 380 * @desc_offset: TX descriptor registers offset 381 * @lock: Descriptor operation lock 382 * @pending_list: Descriptors waiting 383 * @active_list: Descriptors ready to submit 384 * @done_list: Complete descriptors 385 * @free_seg_list: Free descriptors 386 * @common: DMA common channel 387 * @desc_pool: Descriptors pool 388 * @dev: The dma device 389 * @irq: Channel IRQ 390 * @id: Channel ID 391 * @direction: Transfer direction 392 * @num_frms: Number of frames 393 * @has_sg: Support scatter transfers 394 * @cyclic: Check for cyclic transfers. 395 * @genlock: Support genlock mode 396 * @err: Channel has errors 397 * @idle: Check for channel idle 398 * @terminating: Check for channel being synchronized by user 399 * @tasklet: Cleanup work after irq 400 * @config: Device configuration info 401 * @flush_on_fsync: Flush on Frame sync 402 * @desc_pendingcount: Descriptor pending count 403 * @ext_addr: Indicates 64 bit addressing is supported by dma channel 404 * @desc_submitcount: Descriptor h/w submitted count 405 * @seg_v: Statically allocated segments base 406 * @seg_mv: Statically allocated segments base for MCDMA 407 * @seg_p: Physical allocated segments base 408 * @cyclic_seg_v: Statically allocated segment base for cyclic transfers 409 * @cyclic_seg_p: Physical allocated segments base for cyclic dma 410 * @start_transfer: Differentiate b/w DMA IP's transfer 411 * @stop_transfer: Differentiate b/w DMA IP's quiesce 412 * @tdest: TDEST value for mcdma 413 * @has_vflip: S2MM vertical flip 414 */ 415 struct xilinx_dma_chan { 416 struct xilinx_dma_device *xdev; 417 u32 ctrl_offset; 418 u32 desc_offset; 419 spinlock_t lock; 420 struct list_head pending_list; 421 struct list_head active_list; 422 struct list_head done_list; 423 struct list_head free_seg_list; 424 struct dma_chan common; 425 struct dma_pool *desc_pool; 426 struct device *dev; 427 int irq; 428 int id; 429 enum dma_transfer_direction direction; 430 int num_frms; 431 bool has_sg; 432 bool cyclic; 433 bool genlock; 434 bool err; 435 bool idle; 436 bool terminating; 437 struct tasklet_struct tasklet; 438 struct xilinx_vdma_config config; 439 bool flush_on_fsync; 440 u32 desc_pendingcount; 441 bool ext_addr; 442 u32 desc_submitcount; 443 struct xilinx_axidma_tx_segment *seg_v; 444 struct xilinx_aximcdma_tx_segment *seg_mv; 445 dma_addr_t seg_p; 446 struct xilinx_axidma_tx_segment *cyclic_seg_v; 447 dma_addr_t cyclic_seg_p; 448 void (*start_transfer)(struct xilinx_dma_chan *chan); 449 int (*stop_transfer)(struct xilinx_dma_chan *chan); 450 u16 tdest; 451 bool has_vflip; 452 }; 453 454 /** 455 * enum xdma_ip_type - DMA IP type. 456 * 457 * @XDMA_TYPE_AXIDMA: Axi dma ip. 458 * @XDMA_TYPE_CDMA: Axi cdma ip. 459 * @XDMA_TYPE_VDMA: Axi vdma ip. 460 * @XDMA_TYPE_AXIMCDMA: Axi MCDMA ip. 461 * 462 */ 463 enum xdma_ip_type { 464 XDMA_TYPE_AXIDMA = 0, 465 XDMA_TYPE_CDMA, 466 XDMA_TYPE_VDMA, 467 XDMA_TYPE_AXIMCDMA 468 }; 469 470 struct xilinx_dma_config { 471 enum xdma_ip_type dmatype; 472 int (*clk_init)(struct platform_device *pdev, struct clk **axi_clk, 473 struct clk **tx_clk, struct clk **txs_clk, 474 struct clk **rx_clk, struct clk **rxs_clk); 475 irqreturn_t (*irq_handler)(int irq, void *data); 476 const int max_channels; 477 }; 478 479 /** 480 * struct xilinx_dma_device - DMA device structure 481 * @regs: I/O mapped base address 482 * @dev: Device Structure 483 * @common: DMA device structure 484 * @chan: Driver specific DMA channel 485 * @flush_on_fsync: Flush on frame sync 486 * @ext_addr: Indicates 64 bit addressing is supported by dma device 487 * @pdev: Platform device structure pointer 488 * @dma_config: DMA config structure 489 * @axi_clk: DMA Axi4-lite interace clock 490 * @tx_clk: DMA mm2s clock 491 * @txs_clk: DMA mm2s stream clock 492 * @rx_clk: DMA s2mm clock 493 * @rxs_clk: DMA s2mm stream clock 494 * @s2mm_chan_id: DMA s2mm channel identifier 495 * @mm2s_chan_id: DMA mm2s channel identifier 496 * @max_buffer_len: Max buffer length 497 * @has_axistream_connected: AXI DMA connected to AXI Stream IP 498 */ 499 struct xilinx_dma_device { 500 void __iomem *regs; 501 struct device *dev; 502 struct dma_device common; 503 struct xilinx_dma_chan *chan[XILINX_MCDMA_MAX_CHANS_PER_DEVICE]; 504 u32 flush_on_fsync; 505 bool ext_addr; 506 struct platform_device *pdev; 507 const struct xilinx_dma_config *dma_config; 508 struct clk *axi_clk; 509 struct clk *tx_clk; 510 struct clk *txs_clk; 511 struct clk *rx_clk; 512 struct clk *rxs_clk; 513 u32 s2mm_chan_id; 514 u32 mm2s_chan_id; 515 u32 max_buffer_len; 516 bool has_axistream_connected; 517 }; 518 519 /* Macros */ 520 #define to_xilinx_chan(chan) \ 521 container_of(chan, struct xilinx_dma_chan, common) 522 #define to_dma_tx_descriptor(tx) \ 523 container_of(tx, struct xilinx_dma_tx_descriptor, async_tx) 524 #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \ 525 readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \ 526 val, cond, delay_us, timeout_us) 527 528 /* IO accessors */ 529 static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg) 530 { 531 return ioread32(chan->xdev->regs + reg); 532 } 533 534 static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value) 535 { 536 iowrite32(value, chan->xdev->regs + reg); 537 } 538 539 static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg, 540 u32 value) 541 { 542 dma_write(chan, chan->desc_offset + reg, value); 543 } 544 545 static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg) 546 { 547 return dma_read(chan, chan->ctrl_offset + reg); 548 } 549 550 static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg, 551 u32 value) 552 { 553 dma_write(chan, chan->ctrl_offset + reg, value); 554 } 555 556 static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg, 557 u32 clr) 558 { 559 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr); 560 } 561 562 static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg, 563 u32 set) 564 { 565 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set); 566 } 567 568 /** 569 * vdma_desc_write_64 - 64-bit descriptor write 570 * @chan: Driver specific VDMA channel 571 * @reg: Register to write 572 * @value_lsb: lower address of the descriptor. 573 * @value_msb: upper address of the descriptor. 574 * 575 * Since vdma driver is trying to write to a register offset which is not a 576 * multiple of 64 bits(ex : 0x5c), we are writing as two separate 32 bits 577 * instead of a single 64 bit register write. 578 */ 579 static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg, 580 u32 value_lsb, u32 value_msb) 581 { 582 /* Write the lsb 32 bits*/ 583 writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg); 584 585 /* Write the msb 32 bits */ 586 writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4); 587 } 588 589 static inline void dma_writeq(struct xilinx_dma_chan *chan, u32 reg, u64 value) 590 { 591 lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg); 592 } 593 594 static inline void xilinx_write(struct xilinx_dma_chan *chan, u32 reg, 595 dma_addr_t addr) 596 { 597 if (chan->ext_addr) 598 dma_writeq(chan, reg, addr); 599 else 600 dma_ctrl_write(chan, reg, addr); 601 } 602 603 static inline void xilinx_axidma_buf(struct xilinx_dma_chan *chan, 604 struct xilinx_axidma_desc_hw *hw, 605 dma_addr_t buf_addr, size_t sg_used, 606 size_t period_len) 607 { 608 if (chan->ext_addr) { 609 hw->buf_addr = lower_32_bits(buf_addr + sg_used + period_len); 610 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used + 611 period_len); 612 } else { 613 hw->buf_addr = buf_addr + sg_used + period_len; 614 } 615 } 616 617 static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan, 618 struct xilinx_aximcdma_desc_hw *hw, 619 dma_addr_t buf_addr, size_t sg_used) 620 { 621 if (chan->ext_addr) { 622 hw->buf_addr = lower_32_bits(buf_addr + sg_used); 623 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used); 624 } else { 625 hw->buf_addr = buf_addr + sg_used; 626 } 627 } 628 629 /** 630 * xilinx_dma_get_metadata_ptr- Populate metadata pointer and payload length 631 * @tx: async transaction descriptor 632 * @payload_len: metadata payload length 633 * @max_len: metadata max length 634 * Return: The app field pointer. 635 */ 636 static void *xilinx_dma_get_metadata_ptr(struct dma_async_tx_descriptor *tx, 637 size_t *payload_len, size_t *max_len) 638 { 639 struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx); 640 struct xilinx_axidma_tx_segment *seg; 641 642 *max_len = *payload_len = sizeof(u32) * XILINX_DMA_NUM_APP_WORDS; 643 seg = list_first_entry(&desc->segments, 644 struct xilinx_axidma_tx_segment, node); 645 return seg->hw.app; 646 } 647 648 static struct dma_descriptor_metadata_ops xilinx_dma_metadata_ops = { 649 .get_ptr = xilinx_dma_get_metadata_ptr, 650 }; 651 652 /* ----------------------------------------------------------------------------- 653 * Descriptors and segments alloc and free 654 */ 655 656 /** 657 * xilinx_vdma_alloc_tx_segment - Allocate transaction segment 658 * @chan: Driver specific DMA channel 659 * 660 * Return: The allocated segment on success and NULL on failure. 661 */ 662 static struct xilinx_vdma_tx_segment * 663 xilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan) 664 { 665 struct xilinx_vdma_tx_segment *segment; 666 dma_addr_t phys; 667 668 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys); 669 if (!segment) 670 return NULL; 671 672 segment->phys = phys; 673 674 return segment; 675 } 676 677 /** 678 * xilinx_cdma_alloc_tx_segment - Allocate transaction segment 679 * @chan: Driver specific DMA channel 680 * 681 * Return: The allocated segment on success and NULL on failure. 682 */ 683 static struct xilinx_cdma_tx_segment * 684 xilinx_cdma_alloc_tx_segment(struct xilinx_dma_chan *chan) 685 { 686 struct xilinx_cdma_tx_segment *segment; 687 dma_addr_t phys; 688 689 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys); 690 if (!segment) 691 return NULL; 692 693 segment->phys = phys; 694 695 return segment; 696 } 697 698 /** 699 * xilinx_axidma_alloc_tx_segment - Allocate transaction segment 700 * @chan: Driver specific DMA channel 701 * 702 * Return: The allocated segment on success and NULL on failure. 703 */ 704 static struct xilinx_axidma_tx_segment * 705 xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan) 706 { 707 struct xilinx_axidma_tx_segment *segment = NULL; 708 unsigned long flags; 709 710 spin_lock_irqsave(&chan->lock, flags); 711 if (!list_empty(&chan->free_seg_list)) { 712 segment = list_first_entry(&chan->free_seg_list, 713 struct xilinx_axidma_tx_segment, 714 node); 715 list_del(&segment->node); 716 } 717 spin_unlock_irqrestore(&chan->lock, flags); 718 719 if (!segment) 720 dev_dbg(chan->dev, "Could not find free tx segment\n"); 721 722 return segment; 723 } 724 725 /** 726 * xilinx_aximcdma_alloc_tx_segment - Allocate transaction segment 727 * @chan: Driver specific DMA channel 728 * 729 * Return: The allocated segment on success and NULL on failure. 730 */ 731 static struct xilinx_aximcdma_tx_segment * 732 xilinx_aximcdma_alloc_tx_segment(struct xilinx_dma_chan *chan) 733 { 734 struct xilinx_aximcdma_tx_segment *segment = NULL; 735 unsigned long flags; 736 737 spin_lock_irqsave(&chan->lock, flags); 738 if (!list_empty(&chan->free_seg_list)) { 739 segment = list_first_entry(&chan->free_seg_list, 740 struct xilinx_aximcdma_tx_segment, 741 node); 742 list_del(&segment->node); 743 } 744 spin_unlock_irqrestore(&chan->lock, flags); 745 746 return segment; 747 } 748 749 static void xilinx_dma_clean_hw_desc(struct xilinx_axidma_desc_hw *hw) 750 { 751 u32 next_desc = hw->next_desc; 752 u32 next_desc_msb = hw->next_desc_msb; 753 754 memset(hw, 0, sizeof(struct xilinx_axidma_desc_hw)); 755 756 hw->next_desc = next_desc; 757 hw->next_desc_msb = next_desc_msb; 758 } 759 760 static void xilinx_mcdma_clean_hw_desc(struct xilinx_aximcdma_desc_hw *hw) 761 { 762 u32 next_desc = hw->next_desc; 763 u32 next_desc_msb = hw->next_desc_msb; 764 765 memset(hw, 0, sizeof(struct xilinx_aximcdma_desc_hw)); 766 767 hw->next_desc = next_desc; 768 hw->next_desc_msb = next_desc_msb; 769 } 770 771 /** 772 * xilinx_dma_free_tx_segment - Free transaction segment 773 * @chan: Driver specific DMA channel 774 * @segment: DMA transaction segment 775 */ 776 static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan, 777 struct xilinx_axidma_tx_segment *segment) 778 { 779 xilinx_dma_clean_hw_desc(&segment->hw); 780 781 list_add_tail(&segment->node, &chan->free_seg_list); 782 } 783 784 /** 785 * xilinx_mcdma_free_tx_segment - Free transaction segment 786 * @chan: Driver specific DMA channel 787 * @segment: DMA transaction segment 788 */ 789 static void xilinx_mcdma_free_tx_segment(struct xilinx_dma_chan *chan, 790 struct xilinx_aximcdma_tx_segment * 791 segment) 792 { 793 xilinx_mcdma_clean_hw_desc(&segment->hw); 794 795 list_add_tail(&segment->node, &chan->free_seg_list); 796 } 797 798 /** 799 * xilinx_cdma_free_tx_segment - Free transaction segment 800 * @chan: Driver specific DMA channel 801 * @segment: DMA transaction segment 802 */ 803 static void xilinx_cdma_free_tx_segment(struct xilinx_dma_chan *chan, 804 struct xilinx_cdma_tx_segment *segment) 805 { 806 dma_pool_free(chan->desc_pool, segment, segment->phys); 807 } 808 809 /** 810 * xilinx_vdma_free_tx_segment - Free transaction segment 811 * @chan: Driver specific DMA channel 812 * @segment: DMA transaction segment 813 */ 814 static void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan, 815 struct xilinx_vdma_tx_segment *segment) 816 { 817 dma_pool_free(chan->desc_pool, segment, segment->phys); 818 } 819 820 /** 821 * xilinx_dma_alloc_tx_descriptor - Allocate transaction descriptor 822 * @chan: Driver specific DMA channel 823 * 824 * Return: The allocated descriptor on success and NULL on failure. 825 */ 826 static struct xilinx_dma_tx_descriptor * 827 xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan) 828 { 829 struct xilinx_dma_tx_descriptor *desc; 830 831 desc = kzalloc(sizeof(*desc), GFP_NOWAIT); 832 if (!desc) 833 return NULL; 834 835 INIT_LIST_HEAD(&desc->segments); 836 837 return desc; 838 } 839 840 /** 841 * xilinx_dma_free_tx_descriptor - Free transaction descriptor 842 * @chan: Driver specific DMA channel 843 * @desc: DMA transaction descriptor 844 */ 845 static void 846 xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan, 847 struct xilinx_dma_tx_descriptor *desc) 848 { 849 struct xilinx_vdma_tx_segment *segment, *next; 850 struct xilinx_cdma_tx_segment *cdma_segment, *cdma_next; 851 struct xilinx_axidma_tx_segment *axidma_segment, *axidma_next; 852 struct xilinx_aximcdma_tx_segment *aximcdma_segment, *aximcdma_next; 853 854 if (!desc) 855 return; 856 857 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 858 list_for_each_entry_safe(segment, next, &desc->segments, node) { 859 list_del(&segment->node); 860 xilinx_vdma_free_tx_segment(chan, segment); 861 } 862 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 863 list_for_each_entry_safe(cdma_segment, cdma_next, 864 &desc->segments, node) { 865 list_del(&cdma_segment->node); 866 xilinx_cdma_free_tx_segment(chan, cdma_segment); 867 } 868 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 869 list_for_each_entry_safe(axidma_segment, axidma_next, 870 &desc->segments, node) { 871 list_del(&axidma_segment->node); 872 xilinx_dma_free_tx_segment(chan, axidma_segment); 873 } 874 } else { 875 list_for_each_entry_safe(aximcdma_segment, aximcdma_next, 876 &desc->segments, node) { 877 list_del(&aximcdma_segment->node); 878 xilinx_mcdma_free_tx_segment(chan, aximcdma_segment); 879 } 880 } 881 882 kfree(desc); 883 } 884 885 /* Required functions */ 886 887 /** 888 * xilinx_dma_free_desc_list - Free descriptors list 889 * @chan: Driver specific DMA channel 890 * @list: List to parse and delete the descriptor 891 */ 892 static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan, 893 struct list_head *list) 894 { 895 struct xilinx_dma_tx_descriptor *desc, *next; 896 897 list_for_each_entry_safe(desc, next, list, node) { 898 list_del(&desc->node); 899 xilinx_dma_free_tx_descriptor(chan, desc); 900 } 901 } 902 903 /** 904 * xilinx_dma_free_descriptors - Free channel descriptors 905 * @chan: Driver specific DMA channel 906 */ 907 static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan) 908 { 909 unsigned long flags; 910 911 spin_lock_irqsave(&chan->lock, flags); 912 913 xilinx_dma_free_desc_list(chan, &chan->pending_list); 914 xilinx_dma_free_desc_list(chan, &chan->done_list); 915 xilinx_dma_free_desc_list(chan, &chan->active_list); 916 917 spin_unlock_irqrestore(&chan->lock, flags); 918 } 919 920 /** 921 * xilinx_dma_free_chan_resources - Free channel resources 922 * @dchan: DMA channel 923 */ 924 static void xilinx_dma_free_chan_resources(struct dma_chan *dchan) 925 { 926 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 927 unsigned long flags; 928 929 dev_dbg(chan->dev, "Free all channel resources.\n"); 930 931 xilinx_dma_free_descriptors(chan); 932 933 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 934 spin_lock_irqsave(&chan->lock, flags); 935 INIT_LIST_HEAD(&chan->free_seg_list); 936 spin_unlock_irqrestore(&chan->lock, flags); 937 938 /* Free memory that is allocated for BD */ 939 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) * 940 XILINX_DMA_NUM_DESCS, chan->seg_v, 941 chan->seg_p); 942 943 /* Free Memory that is allocated for cyclic DMA Mode */ 944 dma_free_coherent(chan->dev, sizeof(*chan->cyclic_seg_v), 945 chan->cyclic_seg_v, chan->cyclic_seg_p); 946 } 947 948 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 949 spin_lock_irqsave(&chan->lock, flags); 950 INIT_LIST_HEAD(&chan->free_seg_list); 951 spin_unlock_irqrestore(&chan->lock, flags); 952 953 /* Free memory that is allocated for BD */ 954 dma_free_coherent(chan->dev, sizeof(*chan->seg_mv) * 955 XILINX_DMA_NUM_DESCS, chan->seg_mv, 956 chan->seg_p); 957 } 958 959 if (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA && 960 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA) { 961 dma_pool_destroy(chan->desc_pool); 962 chan->desc_pool = NULL; 963 } 964 965 } 966 967 /** 968 * xilinx_dma_get_residue - Compute residue for a given descriptor 969 * @chan: Driver specific dma channel 970 * @desc: dma transaction descriptor 971 * 972 * Return: The number of residue bytes for the descriptor. 973 */ 974 static u32 xilinx_dma_get_residue(struct xilinx_dma_chan *chan, 975 struct xilinx_dma_tx_descriptor *desc) 976 { 977 struct xilinx_cdma_tx_segment *cdma_seg; 978 struct xilinx_axidma_tx_segment *axidma_seg; 979 struct xilinx_aximcdma_tx_segment *aximcdma_seg; 980 struct xilinx_cdma_desc_hw *cdma_hw; 981 struct xilinx_axidma_desc_hw *axidma_hw; 982 struct xilinx_aximcdma_desc_hw *aximcdma_hw; 983 struct list_head *entry; 984 u32 residue = 0; 985 986 list_for_each(entry, &desc->segments) { 987 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 988 cdma_seg = list_entry(entry, 989 struct xilinx_cdma_tx_segment, 990 node); 991 cdma_hw = &cdma_seg->hw; 992 residue += (cdma_hw->control - cdma_hw->status) & 993 chan->xdev->max_buffer_len; 994 } else if (chan->xdev->dma_config->dmatype == 995 XDMA_TYPE_AXIDMA) { 996 axidma_seg = list_entry(entry, 997 struct xilinx_axidma_tx_segment, 998 node); 999 axidma_hw = &axidma_seg->hw; 1000 residue += (axidma_hw->control - axidma_hw->status) & 1001 chan->xdev->max_buffer_len; 1002 } else { 1003 aximcdma_seg = 1004 list_entry(entry, 1005 struct xilinx_aximcdma_tx_segment, 1006 node); 1007 aximcdma_hw = &aximcdma_seg->hw; 1008 residue += 1009 (aximcdma_hw->control - aximcdma_hw->status) & 1010 chan->xdev->max_buffer_len; 1011 } 1012 } 1013 1014 return residue; 1015 } 1016 1017 /** 1018 * xilinx_dma_chan_handle_cyclic - Cyclic dma callback 1019 * @chan: Driver specific dma channel 1020 * @desc: dma transaction descriptor 1021 * @flags: flags for spin lock 1022 */ 1023 static void xilinx_dma_chan_handle_cyclic(struct xilinx_dma_chan *chan, 1024 struct xilinx_dma_tx_descriptor *desc, 1025 unsigned long *flags) 1026 { 1027 struct dmaengine_desc_callback cb; 1028 1029 dmaengine_desc_get_callback(&desc->async_tx, &cb); 1030 if (dmaengine_desc_callback_valid(&cb)) { 1031 spin_unlock_irqrestore(&chan->lock, *flags); 1032 dmaengine_desc_callback_invoke(&cb, NULL); 1033 spin_lock_irqsave(&chan->lock, *flags); 1034 } 1035 } 1036 1037 /** 1038 * xilinx_dma_chan_desc_cleanup - Clean channel descriptors 1039 * @chan: Driver specific DMA channel 1040 */ 1041 static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan) 1042 { 1043 struct xilinx_dma_tx_descriptor *desc, *next; 1044 unsigned long flags; 1045 1046 spin_lock_irqsave(&chan->lock, flags); 1047 1048 list_for_each_entry_safe(desc, next, &chan->done_list, node) { 1049 struct dmaengine_result result; 1050 1051 if (desc->cyclic) { 1052 xilinx_dma_chan_handle_cyclic(chan, desc, &flags); 1053 break; 1054 } 1055 1056 /* Remove from the list of running transactions */ 1057 list_del(&desc->node); 1058 1059 if (unlikely(desc->err)) { 1060 if (chan->direction == DMA_DEV_TO_MEM) 1061 result.result = DMA_TRANS_READ_FAILED; 1062 else 1063 result.result = DMA_TRANS_WRITE_FAILED; 1064 } else { 1065 result.result = DMA_TRANS_NOERROR; 1066 } 1067 1068 result.residue = desc->residue; 1069 1070 /* Run the link descriptor callback function */ 1071 spin_unlock_irqrestore(&chan->lock, flags); 1072 dmaengine_desc_get_callback_invoke(&desc->async_tx, &result); 1073 spin_lock_irqsave(&chan->lock, flags); 1074 1075 /* Run any dependencies, then free the descriptor */ 1076 dma_run_dependencies(&desc->async_tx); 1077 xilinx_dma_free_tx_descriptor(chan, desc); 1078 1079 /* 1080 * While we ran a callback the user called a terminate function, 1081 * which takes care of cleaning up any remaining descriptors 1082 */ 1083 if (chan->terminating) 1084 break; 1085 } 1086 1087 spin_unlock_irqrestore(&chan->lock, flags); 1088 } 1089 1090 /** 1091 * xilinx_dma_do_tasklet - Schedule completion tasklet 1092 * @t: Pointer to the Xilinx DMA channel structure 1093 */ 1094 static void xilinx_dma_do_tasklet(struct tasklet_struct *t) 1095 { 1096 struct xilinx_dma_chan *chan = from_tasklet(chan, t, tasklet); 1097 1098 xilinx_dma_chan_desc_cleanup(chan); 1099 } 1100 1101 /** 1102 * xilinx_dma_alloc_chan_resources - Allocate channel resources 1103 * @dchan: DMA channel 1104 * 1105 * Return: '0' on success and failure value on error 1106 */ 1107 static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan) 1108 { 1109 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 1110 int i; 1111 1112 /* Has this channel already been allocated? */ 1113 if (chan->desc_pool) 1114 return 0; 1115 1116 /* 1117 * We need the descriptor to be aligned to 64bytes 1118 * for meeting Xilinx VDMA specification requirement. 1119 */ 1120 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 1121 /* Allocate the buffer descriptors. */ 1122 chan->seg_v = dma_alloc_coherent(chan->dev, 1123 sizeof(*chan->seg_v) * XILINX_DMA_NUM_DESCS, 1124 &chan->seg_p, GFP_KERNEL); 1125 if (!chan->seg_v) { 1126 dev_err(chan->dev, 1127 "unable to allocate channel %d descriptors\n", 1128 chan->id); 1129 return -ENOMEM; 1130 } 1131 /* 1132 * For cyclic DMA mode we need to program the tail Descriptor 1133 * register with a value which is not a part of the BD chain 1134 * so allocating a desc segment during channel allocation for 1135 * programming tail descriptor. 1136 */ 1137 chan->cyclic_seg_v = dma_alloc_coherent(chan->dev, 1138 sizeof(*chan->cyclic_seg_v), 1139 &chan->cyclic_seg_p, 1140 GFP_KERNEL); 1141 if (!chan->cyclic_seg_v) { 1142 dev_err(chan->dev, 1143 "unable to allocate desc segment for cyclic DMA\n"); 1144 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) * 1145 XILINX_DMA_NUM_DESCS, chan->seg_v, 1146 chan->seg_p); 1147 return -ENOMEM; 1148 } 1149 chan->cyclic_seg_v->phys = chan->cyclic_seg_p; 1150 1151 for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) { 1152 chan->seg_v[i].hw.next_desc = 1153 lower_32_bits(chan->seg_p + sizeof(*chan->seg_v) * 1154 ((i + 1) % XILINX_DMA_NUM_DESCS)); 1155 chan->seg_v[i].hw.next_desc_msb = 1156 upper_32_bits(chan->seg_p + sizeof(*chan->seg_v) * 1157 ((i + 1) % XILINX_DMA_NUM_DESCS)); 1158 chan->seg_v[i].phys = chan->seg_p + 1159 sizeof(*chan->seg_v) * i; 1160 list_add_tail(&chan->seg_v[i].node, 1161 &chan->free_seg_list); 1162 } 1163 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 1164 /* Allocate the buffer descriptors. */ 1165 chan->seg_mv = dma_alloc_coherent(chan->dev, 1166 sizeof(*chan->seg_mv) * 1167 XILINX_DMA_NUM_DESCS, 1168 &chan->seg_p, GFP_KERNEL); 1169 if (!chan->seg_mv) { 1170 dev_err(chan->dev, 1171 "unable to allocate channel %d descriptors\n", 1172 chan->id); 1173 return -ENOMEM; 1174 } 1175 for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) { 1176 chan->seg_mv[i].hw.next_desc = 1177 lower_32_bits(chan->seg_p + sizeof(*chan->seg_mv) * 1178 ((i + 1) % XILINX_DMA_NUM_DESCS)); 1179 chan->seg_mv[i].hw.next_desc_msb = 1180 upper_32_bits(chan->seg_p + sizeof(*chan->seg_mv) * 1181 ((i + 1) % XILINX_DMA_NUM_DESCS)); 1182 chan->seg_mv[i].phys = chan->seg_p + 1183 sizeof(*chan->seg_mv) * i; 1184 list_add_tail(&chan->seg_mv[i].node, 1185 &chan->free_seg_list); 1186 } 1187 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 1188 chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool", 1189 chan->dev, 1190 sizeof(struct xilinx_cdma_tx_segment), 1191 __alignof__(struct xilinx_cdma_tx_segment), 1192 0); 1193 } else { 1194 chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool", 1195 chan->dev, 1196 sizeof(struct xilinx_vdma_tx_segment), 1197 __alignof__(struct xilinx_vdma_tx_segment), 1198 0); 1199 } 1200 1201 if (!chan->desc_pool && 1202 ((chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) && 1203 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA)) { 1204 dev_err(chan->dev, 1205 "unable to allocate channel %d descriptor pool\n", 1206 chan->id); 1207 return -ENOMEM; 1208 } 1209 1210 dma_cookie_init(dchan); 1211 1212 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 1213 /* For AXI DMA resetting once channel will reset the 1214 * other channel as well so enable the interrupts here. 1215 */ 1216 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, 1217 XILINX_DMA_DMAXR_ALL_IRQ_MASK); 1218 } 1219 1220 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) 1221 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, 1222 XILINX_CDMA_CR_SGMODE); 1223 1224 return 0; 1225 } 1226 1227 /** 1228 * xilinx_dma_calc_copysize - Calculate the amount of data to copy 1229 * @chan: Driver specific DMA channel 1230 * @size: Total data that needs to be copied 1231 * @done: Amount of data that has been already copied 1232 * 1233 * Return: Amount of data that has to be copied 1234 */ 1235 static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan, 1236 int size, int done) 1237 { 1238 size_t copy; 1239 1240 copy = min_t(size_t, size - done, 1241 chan->xdev->max_buffer_len); 1242 1243 if ((copy + done < size) && 1244 chan->xdev->common.copy_align) { 1245 /* 1246 * If this is not the last descriptor, make sure 1247 * the next one will be properly aligned 1248 */ 1249 copy = rounddown(copy, 1250 (1 << chan->xdev->common.copy_align)); 1251 } 1252 return copy; 1253 } 1254 1255 /** 1256 * xilinx_dma_tx_status - Get DMA transaction status 1257 * @dchan: DMA channel 1258 * @cookie: Transaction identifier 1259 * @txstate: Transaction state 1260 * 1261 * Return: DMA transaction status 1262 */ 1263 static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan, 1264 dma_cookie_t cookie, 1265 struct dma_tx_state *txstate) 1266 { 1267 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 1268 struct xilinx_dma_tx_descriptor *desc; 1269 enum dma_status ret; 1270 unsigned long flags; 1271 u32 residue = 0; 1272 1273 ret = dma_cookie_status(dchan, cookie, txstate); 1274 if (ret == DMA_COMPLETE || !txstate) 1275 return ret; 1276 1277 spin_lock_irqsave(&chan->lock, flags); 1278 if (!list_empty(&chan->active_list)) { 1279 desc = list_last_entry(&chan->active_list, 1280 struct xilinx_dma_tx_descriptor, node); 1281 /* 1282 * VDMA and simple mode do not support residue reporting, so the 1283 * residue field will always be 0. 1284 */ 1285 if (chan->has_sg && chan->xdev->dma_config->dmatype != XDMA_TYPE_VDMA) 1286 residue = xilinx_dma_get_residue(chan, desc); 1287 } 1288 spin_unlock_irqrestore(&chan->lock, flags); 1289 1290 dma_set_residue(txstate, residue); 1291 1292 return ret; 1293 } 1294 1295 /** 1296 * xilinx_dma_stop_transfer - Halt DMA channel 1297 * @chan: Driver specific DMA channel 1298 * 1299 * Return: '0' on success and failure value on error 1300 */ 1301 static int xilinx_dma_stop_transfer(struct xilinx_dma_chan *chan) 1302 { 1303 u32 val; 1304 1305 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP); 1306 1307 /* Wait for the hardware to halt */ 1308 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, 1309 val & XILINX_DMA_DMASR_HALTED, 0, 1310 XILINX_DMA_LOOP_COUNT); 1311 } 1312 1313 /** 1314 * xilinx_cdma_stop_transfer - Wait for the current transfer to complete 1315 * @chan: Driver specific DMA channel 1316 * 1317 * Return: '0' on success and failure value on error 1318 */ 1319 static int xilinx_cdma_stop_transfer(struct xilinx_dma_chan *chan) 1320 { 1321 u32 val; 1322 1323 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, 1324 val & XILINX_DMA_DMASR_IDLE, 0, 1325 XILINX_DMA_LOOP_COUNT); 1326 } 1327 1328 /** 1329 * xilinx_dma_start - Start DMA channel 1330 * @chan: Driver specific DMA channel 1331 */ 1332 static void xilinx_dma_start(struct xilinx_dma_chan *chan) 1333 { 1334 int err; 1335 u32 val; 1336 1337 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP); 1338 1339 /* Wait for the hardware to start */ 1340 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, 1341 !(val & XILINX_DMA_DMASR_HALTED), 0, 1342 XILINX_DMA_LOOP_COUNT); 1343 1344 if (err) { 1345 dev_err(chan->dev, "Cannot start channel %p: %x\n", 1346 chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); 1347 1348 chan->err = true; 1349 } 1350 } 1351 1352 /** 1353 * xilinx_vdma_start_transfer - Starts VDMA transfer 1354 * @chan: Driver specific channel struct pointer 1355 */ 1356 static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) 1357 { 1358 struct xilinx_vdma_config *config = &chan->config; 1359 struct xilinx_dma_tx_descriptor *desc; 1360 u32 reg, j; 1361 struct xilinx_vdma_tx_segment *segment, *last = NULL; 1362 int i = 0; 1363 1364 /* This function was invoked with lock held */ 1365 if (chan->err) 1366 return; 1367 1368 if (!chan->idle) 1369 return; 1370 1371 if (list_empty(&chan->pending_list)) 1372 return; 1373 1374 desc = list_first_entry(&chan->pending_list, 1375 struct xilinx_dma_tx_descriptor, node); 1376 1377 /* Configure the hardware using info in the config structure */ 1378 if (chan->has_vflip) { 1379 reg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP); 1380 reg &= ~XILINX_VDMA_ENABLE_VERTICAL_FLIP; 1381 reg |= config->vflip_en; 1382 dma_write(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP, 1383 reg); 1384 } 1385 1386 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 1387 1388 if (config->frm_cnt_en) 1389 reg |= XILINX_DMA_DMACR_FRAMECNT_EN; 1390 else 1391 reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN; 1392 1393 /* If not parking, enable circular mode */ 1394 if (config->park) 1395 reg &= ~XILINX_DMA_DMACR_CIRC_EN; 1396 else 1397 reg |= XILINX_DMA_DMACR_CIRC_EN; 1398 1399 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); 1400 1401 j = chan->desc_submitcount; 1402 reg = dma_read(chan, XILINX_DMA_REG_PARK_PTR); 1403 if (chan->direction == DMA_MEM_TO_DEV) { 1404 reg &= ~XILINX_DMA_PARK_PTR_RD_REF_MASK; 1405 reg |= j << XILINX_DMA_PARK_PTR_RD_REF_SHIFT; 1406 } else { 1407 reg &= ~XILINX_DMA_PARK_PTR_WR_REF_MASK; 1408 reg |= j << XILINX_DMA_PARK_PTR_WR_REF_SHIFT; 1409 } 1410 dma_write(chan, XILINX_DMA_REG_PARK_PTR, reg); 1411 1412 /* Start the hardware */ 1413 xilinx_dma_start(chan); 1414 1415 if (chan->err) 1416 return; 1417 1418 /* Start the transfer */ 1419 if (chan->desc_submitcount < chan->num_frms) 1420 i = chan->desc_submitcount; 1421 1422 list_for_each_entry(segment, &desc->segments, node) { 1423 if (chan->ext_addr) 1424 vdma_desc_write_64(chan, 1425 XILINX_VDMA_REG_START_ADDRESS_64(i++), 1426 segment->hw.buf_addr, 1427 segment->hw.buf_addr_msb); 1428 else 1429 vdma_desc_write(chan, 1430 XILINX_VDMA_REG_START_ADDRESS(i++), 1431 segment->hw.buf_addr); 1432 1433 last = segment; 1434 } 1435 1436 if (!last) 1437 return; 1438 1439 /* HW expects these parameters to be same for one transaction */ 1440 vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); 1441 vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE, 1442 last->hw.stride); 1443 vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); 1444 1445 chan->desc_submitcount++; 1446 chan->desc_pendingcount--; 1447 list_move_tail(&desc->node, &chan->active_list); 1448 if (chan->desc_submitcount == chan->num_frms) 1449 chan->desc_submitcount = 0; 1450 1451 chan->idle = false; 1452 } 1453 1454 /** 1455 * xilinx_cdma_start_transfer - Starts cdma transfer 1456 * @chan: Driver specific channel struct pointer 1457 */ 1458 static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan) 1459 { 1460 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; 1461 struct xilinx_cdma_tx_segment *tail_segment; 1462 u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR); 1463 1464 if (chan->err) 1465 return; 1466 1467 if (!chan->idle) 1468 return; 1469 1470 if (list_empty(&chan->pending_list)) 1471 return; 1472 1473 head_desc = list_first_entry(&chan->pending_list, 1474 struct xilinx_dma_tx_descriptor, node); 1475 tail_desc = list_last_entry(&chan->pending_list, 1476 struct xilinx_dma_tx_descriptor, node); 1477 tail_segment = list_last_entry(&tail_desc->segments, 1478 struct xilinx_cdma_tx_segment, node); 1479 1480 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { 1481 ctrl_reg &= ~XILINX_DMA_CR_COALESCE_MAX; 1482 ctrl_reg |= chan->desc_pendingcount << 1483 XILINX_DMA_CR_COALESCE_SHIFT; 1484 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg); 1485 } 1486 1487 if (chan->has_sg) { 1488 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, 1489 XILINX_CDMA_CR_SGMODE); 1490 1491 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, 1492 XILINX_CDMA_CR_SGMODE); 1493 1494 xilinx_write(chan, XILINX_DMA_REG_CURDESC, 1495 head_desc->async_tx.phys); 1496 1497 /* Update tail ptr register which will start the transfer */ 1498 xilinx_write(chan, XILINX_DMA_REG_TAILDESC, 1499 tail_segment->phys); 1500 } else { 1501 /* In simple mode */ 1502 struct xilinx_cdma_tx_segment *segment; 1503 struct xilinx_cdma_desc_hw *hw; 1504 1505 segment = list_first_entry(&head_desc->segments, 1506 struct xilinx_cdma_tx_segment, 1507 node); 1508 1509 hw = &segment->hw; 1510 1511 xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, 1512 xilinx_prep_dma_addr_t(hw->src_addr)); 1513 xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, 1514 xilinx_prep_dma_addr_t(hw->dest_addr)); 1515 1516 /* Start the transfer */ 1517 dma_ctrl_write(chan, XILINX_DMA_REG_BTT, 1518 hw->control & chan->xdev->max_buffer_len); 1519 } 1520 1521 list_splice_tail_init(&chan->pending_list, &chan->active_list); 1522 chan->desc_pendingcount = 0; 1523 chan->idle = false; 1524 } 1525 1526 /** 1527 * xilinx_dma_start_transfer - Starts DMA transfer 1528 * @chan: Driver specific channel struct pointer 1529 */ 1530 static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan) 1531 { 1532 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; 1533 struct xilinx_axidma_tx_segment *tail_segment; 1534 u32 reg; 1535 1536 if (chan->err) 1537 return; 1538 1539 if (list_empty(&chan->pending_list)) 1540 return; 1541 1542 if (!chan->idle) 1543 return; 1544 1545 head_desc = list_first_entry(&chan->pending_list, 1546 struct xilinx_dma_tx_descriptor, node); 1547 tail_desc = list_last_entry(&chan->pending_list, 1548 struct xilinx_dma_tx_descriptor, node); 1549 tail_segment = list_last_entry(&tail_desc->segments, 1550 struct xilinx_axidma_tx_segment, node); 1551 1552 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 1553 1554 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { 1555 reg &= ~XILINX_DMA_CR_COALESCE_MAX; 1556 reg |= chan->desc_pendingcount << 1557 XILINX_DMA_CR_COALESCE_SHIFT; 1558 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); 1559 } 1560 1561 if (chan->has_sg) 1562 xilinx_write(chan, XILINX_DMA_REG_CURDESC, 1563 head_desc->async_tx.phys); 1564 1565 xilinx_dma_start(chan); 1566 1567 if (chan->err) 1568 return; 1569 1570 /* Start the transfer */ 1571 if (chan->has_sg) { 1572 if (chan->cyclic) 1573 xilinx_write(chan, XILINX_DMA_REG_TAILDESC, 1574 chan->cyclic_seg_v->phys); 1575 else 1576 xilinx_write(chan, XILINX_DMA_REG_TAILDESC, 1577 tail_segment->phys); 1578 } else { 1579 struct xilinx_axidma_tx_segment *segment; 1580 struct xilinx_axidma_desc_hw *hw; 1581 1582 segment = list_first_entry(&head_desc->segments, 1583 struct xilinx_axidma_tx_segment, 1584 node); 1585 hw = &segment->hw; 1586 1587 xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR, 1588 xilinx_prep_dma_addr_t(hw->buf_addr)); 1589 1590 /* Start the transfer */ 1591 dma_ctrl_write(chan, XILINX_DMA_REG_BTT, 1592 hw->control & chan->xdev->max_buffer_len); 1593 } 1594 1595 list_splice_tail_init(&chan->pending_list, &chan->active_list); 1596 chan->desc_pendingcount = 0; 1597 chan->idle = false; 1598 } 1599 1600 /** 1601 * xilinx_mcdma_start_transfer - Starts MCDMA transfer 1602 * @chan: Driver specific channel struct pointer 1603 */ 1604 static void xilinx_mcdma_start_transfer(struct xilinx_dma_chan *chan) 1605 { 1606 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; 1607 struct xilinx_aximcdma_tx_segment *tail_segment; 1608 u32 reg; 1609 1610 /* 1611 * lock has been held by calling functions, so we don't need it 1612 * to take it here again. 1613 */ 1614 1615 if (chan->err) 1616 return; 1617 1618 if (!chan->idle) 1619 return; 1620 1621 if (list_empty(&chan->pending_list)) 1622 return; 1623 1624 head_desc = list_first_entry(&chan->pending_list, 1625 struct xilinx_dma_tx_descriptor, node); 1626 tail_desc = list_last_entry(&chan->pending_list, 1627 struct xilinx_dma_tx_descriptor, node); 1628 tail_segment = list_last_entry(&tail_desc->segments, 1629 struct xilinx_aximcdma_tx_segment, node); 1630 1631 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest)); 1632 1633 if (chan->desc_pendingcount <= XILINX_MCDMA_COALESCE_MAX) { 1634 reg &= ~XILINX_MCDMA_COALESCE_MASK; 1635 reg |= chan->desc_pendingcount << 1636 XILINX_MCDMA_COALESCE_SHIFT; 1637 } 1638 1639 reg |= XILINX_MCDMA_IRQ_ALL_MASK; 1640 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); 1641 1642 /* Program current descriptor */ 1643 xilinx_write(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET(chan->tdest), 1644 head_desc->async_tx.phys); 1645 1646 /* Program channel enable register */ 1647 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHEN_OFFSET); 1648 reg |= BIT(chan->tdest); 1649 dma_ctrl_write(chan, XILINX_MCDMA_CHEN_OFFSET, reg); 1650 1651 /* Start the fetch of BDs for the channel */ 1652 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest)); 1653 reg |= XILINX_MCDMA_CR_RUNSTOP_MASK; 1654 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); 1655 1656 xilinx_dma_start(chan); 1657 1658 if (chan->err) 1659 return; 1660 1661 /* Start the transfer */ 1662 xilinx_write(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET(chan->tdest), 1663 tail_segment->phys); 1664 1665 list_splice_tail_init(&chan->pending_list, &chan->active_list); 1666 chan->desc_pendingcount = 0; 1667 chan->idle = false; 1668 } 1669 1670 /** 1671 * xilinx_dma_issue_pending - Issue pending transactions 1672 * @dchan: DMA channel 1673 */ 1674 static void xilinx_dma_issue_pending(struct dma_chan *dchan) 1675 { 1676 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 1677 unsigned long flags; 1678 1679 spin_lock_irqsave(&chan->lock, flags); 1680 chan->start_transfer(chan); 1681 spin_unlock_irqrestore(&chan->lock, flags); 1682 } 1683 1684 /** 1685 * xilinx_dma_device_config - Configure the DMA channel 1686 * @dchan: DMA channel 1687 * @config: channel configuration 1688 * 1689 * Return: 0 always. 1690 */ 1691 static int xilinx_dma_device_config(struct dma_chan *dchan, 1692 struct dma_slave_config *config) 1693 { 1694 return 0; 1695 } 1696 1697 /** 1698 * xilinx_dma_complete_descriptor - Mark the active descriptor as complete 1699 * @chan : xilinx DMA channel 1700 * 1701 * CONTEXT: hardirq 1702 */ 1703 static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan) 1704 { 1705 struct xilinx_dma_tx_descriptor *desc, *next; 1706 1707 /* This function was invoked with lock held */ 1708 if (list_empty(&chan->active_list)) 1709 return; 1710 1711 list_for_each_entry_safe(desc, next, &chan->active_list, node) { 1712 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 1713 struct xilinx_axidma_tx_segment *seg; 1714 1715 seg = list_last_entry(&desc->segments, 1716 struct xilinx_axidma_tx_segment, node); 1717 if (!(seg->hw.status & XILINX_DMA_BD_COMP_MASK) && chan->has_sg) 1718 break; 1719 } 1720 if (chan->has_sg && chan->xdev->dma_config->dmatype != 1721 XDMA_TYPE_VDMA) 1722 desc->residue = xilinx_dma_get_residue(chan, desc); 1723 else 1724 desc->residue = 0; 1725 desc->err = chan->err; 1726 1727 list_del(&desc->node); 1728 if (!desc->cyclic) 1729 dma_cookie_complete(&desc->async_tx); 1730 list_add_tail(&desc->node, &chan->done_list); 1731 } 1732 } 1733 1734 /** 1735 * xilinx_dma_reset - Reset DMA channel 1736 * @chan: Driver specific DMA channel 1737 * 1738 * Return: '0' on success and failure value on error 1739 */ 1740 static int xilinx_dma_reset(struct xilinx_dma_chan *chan) 1741 { 1742 int err; 1743 u32 tmp; 1744 1745 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET); 1746 1747 /* Wait for the hardware to finish reset */ 1748 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp, 1749 !(tmp & XILINX_DMA_DMACR_RESET), 0, 1750 XILINX_DMA_LOOP_COUNT); 1751 1752 if (err) { 1753 dev_err(chan->dev, "reset timeout, cr %x, sr %x\n", 1754 dma_ctrl_read(chan, XILINX_DMA_REG_DMACR), 1755 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); 1756 return -ETIMEDOUT; 1757 } 1758 1759 chan->err = false; 1760 chan->idle = true; 1761 chan->desc_pendingcount = 0; 1762 chan->desc_submitcount = 0; 1763 1764 return err; 1765 } 1766 1767 /** 1768 * xilinx_dma_chan_reset - Reset DMA channel and enable interrupts 1769 * @chan: Driver specific DMA channel 1770 * 1771 * Return: '0' on success and failure value on error 1772 */ 1773 static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan) 1774 { 1775 int err; 1776 1777 /* Reset VDMA */ 1778 err = xilinx_dma_reset(chan); 1779 if (err) 1780 return err; 1781 1782 /* Enable interrupts */ 1783 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, 1784 XILINX_DMA_DMAXR_ALL_IRQ_MASK); 1785 1786 return 0; 1787 } 1788 1789 /** 1790 * xilinx_mcdma_irq_handler - MCDMA Interrupt handler 1791 * @irq: IRQ number 1792 * @data: Pointer to the Xilinx MCDMA channel structure 1793 * 1794 * Return: IRQ_HANDLED/IRQ_NONE 1795 */ 1796 static irqreturn_t xilinx_mcdma_irq_handler(int irq, void *data) 1797 { 1798 struct xilinx_dma_chan *chan = data; 1799 u32 status, ser_offset, chan_sermask, chan_offset = 0, chan_id; 1800 1801 if (chan->direction == DMA_DEV_TO_MEM) 1802 ser_offset = XILINX_MCDMA_RXINT_SER_OFFSET; 1803 else 1804 ser_offset = XILINX_MCDMA_TXINT_SER_OFFSET; 1805 1806 /* Read the channel id raising the interrupt*/ 1807 chan_sermask = dma_ctrl_read(chan, ser_offset); 1808 chan_id = ffs(chan_sermask); 1809 1810 if (!chan_id) 1811 return IRQ_NONE; 1812 1813 if (chan->direction == DMA_DEV_TO_MEM) 1814 chan_offset = chan->xdev->dma_config->max_channels / 2; 1815 1816 chan_offset = chan_offset + (chan_id - 1); 1817 chan = chan->xdev->chan[chan_offset]; 1818 /* Read the status and ack the interrupts. */ 1819 status = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest)); 1820 if (!(status & XILINX_MCDMA_IRQ_ALL_MASK)) 1821 return IRQ_NONE; 1822 1823 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest), 1824 status & XILINX_MCDMA_IRQ_ALL_MASK); 1825 1826 if (status & XILINX_MCDMA_IRQ_ERR_MASK) { 1827 dev_err(chan->dev, "Channel %p has errors %x cdr %x tdr %x\n", 1828 chan, 1829 dma_ctrl_read(chan, XILINX_MCDMA_CH_ERR_OFFSET), 1830 dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET 1831 (chan->tdest)), 1832 dma_ctrl_read(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET 1833 (chan->tdest))); 1834 chan->err = true; 1835 } 1836 1837 if (status & XILINX_MCDMA_IRQ_DELAY_MASK) { 1838 /* 1839 * Device takes too long to do the transfer when user requires 1840 * responsiveness. 1841 */ 1842 dev_dbg(chan->dev, "Inter-packet latency too long\n"); 1843 } 1844 1845 if (status & XILINX_MCDMA_IRQ_IOC_MASK) { 1846 spin_lock(&chan->lock); 1847 xilinx_dma_complete_descriptor(chan); 1848 chan->idle = true; 1849 chan->start_transfer(chan); 1850 spin_unlock(&chan->lock); 1851 } 1852 1853 tasklet_hi_schedule(&chan->tasklet); 1854 return IRQ_HANDLED; 1855 } 1856 1857 /** 1858 * xilinx_dma_irq_handler - DMA Interrupt handler 1859 * @irq: IRQ number 1860 * @data: Pointer to the Xilinx DMA channel structure 1861 * 1862 * Return: IRQ_HANDLED/IRQ_NONE 1863 */ 1864 static irqreturn_t xilinx_dma_irq_handler(int irq, void *data) 1865 { 1866 struct xilinx_dma_chan *chan = data; 1867 u32 status; 1868 1869 /* Read the status and ack the interrupts. */ 1870 status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR); 1871 if (!(status & XILINX_DMA_DMAXR_ALL_IRQ_MASK)) 1872 return IRQ_NONE; 1873 1874 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR, 1875 status & XILINX_DMA_DMAXR_ALL_IRQ_MASK); 1876 1877 if (status & XILINX_DMA_DMASR_ERR_IRQ) { 1878 /* 1879 * An error occurred. If C_FLUSH_ON_FSYNC is enabled and the 1880 * error is recoverable, ignore it. Otherwise flag the error. 1881 * 1882 * Only recoverable errors can be cleared in the DMASR register, 1883 * make sure not to write to other error bits to 1. 1884 */ 1885 u32 errors = status & XILINX_DMA_DMASR_ALL_ERR_MASK; 1886 1887 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR, 1888 errors & XILINX_DMA_DMASR_ERR_RECOVER_MASK); 1889 1890 if (!chan->flush_on_fsync || 1891 (errors & ~XILINX_DMA_DMASR_ERR_RECOVER_MASK)) { 1892 dev_err(chan->dev, 1893 "Channel %p has errors %x, cdr %x tdr %x\n", 1894 chan, errors, 1895 dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC), 1896 dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC)); 1897 chan->err = true; 1898 } 1899 } 1900 1901 if (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) { 1902 /* 1903 * Device takes too long to do the transfer when user requires 1904 * responsiveness. 1905 */ 1906 dev_dbg(chan->dev, "Inter-packet latency too long\n"); 1907 } 1908 1909 if (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) { 1910 spin_lock(&chan->lock); 1911 xilinx_dma_complete_descriptor(chan); 1912 chan->idle = true; 1913 chan->start_transfer(chan); 1914 spin_unlock(&chan->lock); 1915 } 1916 1917 tasklet_schedule(&chan->tasklet); 1918 return IRQ_HANDLED; 1919 } 1920 1921 /** 1922 * append_desc_queue - Queuing descriptor 1923 * @chan: Driver specific dma channel 1924 * @desc: dma transaction descriptor 1925 */ 1926 static void append_desc_queue(struct xilinx_dma_chan *chan, 1927 struct xilinx_dma_tx_descriptor *desc) 1928 { 1929 struct xilinx_vdma_tx_segment *tail_segment; 1930 struct xilinx_dma_tx_descriptor *tail_desc; 1931 struct xilinx_axidma_tx_segment *axidma_tail_segment; 1932 struct xilinx_aximcdma_tx_segment *aximcdma_tail_segment; 1933 struct xilinx_cdma_tx_segment *cdma_tail_segment; 1934 1935 if (list_empty(&chan->pending_list)) 1936 goto append; 1937 1938 /* 1939 * Add the hardware descriptor to the chain of hardware descriptors 1940 * that already exists in memory. 1941 */ 1942 tail_desc = list_last_entry(&chan->pending_list, 1943 struct xilinx_dma_tx_descriptor, node); 1944 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 1945 tail_segment = list_last_entry(&tail_desc->segments, 1946 struct xilinx_vdma_tx_segment, 1947 node); 1948 tail_segment->hw.next_desc = (u32)desc->async_tx.phys; 1949 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 1950 cdma_tail_segment = list_last_entry(&tail_desc->segments, 1951 struct xilinx_cdma_tx_segment, 1952 node); 1953 cdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; 1954 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 1955 axidma_tail_segment = list_last_entry(&tail_desc->segments, 1956 struct xilinx_axidma_tx_segment, 1957 node); 1958 axidma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; 1959 } else { 1960 aximcdma_tail_segment = 1961 list_last_entry(&tail_desc->segments, 1962 struct xilinx_aximcdma_tx_segment, 1963 node); 1964 aximcdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; 1965 } 1966 1967 /* 1968 * Add the software descriptor and all children to the list 1969 * of pending transactions 1970 */ 1971 append: 1972 list_add_tail(&desc->node, &chan->pending_list); 1973 chan->desc_pendingcount++; 1974 1975 if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) 1976 && unlikely(chan->desc_pendingcount > chan->num_frms)) { 1977 dev_dbg(chan->dev, "desc pendingcount is too high\n"); 1978 chan->desc_pendingcount = chan->num_frms; 1979 } 1980 } 1981 1982 /** 1983 * xilinx_dma_tx_submit - Submit DMA transaction 1984 * @tx: Async transaction descriptor 1985 * 1986 * Return: cookie value on success and failure value on error 1987 */ 1988 static dma_cookie_t xilinx_dma_tx_submit(struct dma_async_tx_descriptor *tx) 1989 { 1990 struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx); 1991 struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan); 1992 dma_cookie_t cookie; 1993 unsigned long flags; 1994 int err; 1995 1996 if (chan->cyclic) { 1997 xilinx_dma_free_tx_descriptor(chan, desc); 1998 return -EBUSY; 1999 } 2000 2001 if (chan->err) { 2002 /* 2003 * If reset fails, need to hard reset the system. 2004 * Channel is no longer functional 2005 */ 2006 err = xilinx_dma_chan_reset(chan); 2007 if (err < 0) 2008 return err; 2009 } 2010 2011 spin_lock_irqsave(&chan->lock, flags); 2012 2013 cookie = dma_cookie_assign(tx); 2014 2015 /* Put this transaction onto the tail of the pending queue */ 2016 append_desc_queue(chan, desc); 2017 2018 if (desc->cyclic) 2019 chan->cyclic = true; 2020 2021 chan->terminating = false; 2022 2023 spin_unlock_irqrestore(&chan->lock, flags); 2024 2025 return cookie; 2026 } 2027 2028 /** 2029 * xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a 2030 * DMA_SLAVE transaction 2031 * @dchan: DMA channel 2032 * @xt: Interleaved template pointer 2033 * @flags: transfer ack flags 2034 * 2035 * Return: Async transaction descriptor on success and NULL on failure 2036 */ 2037 static struct dma_async_tx_descriptor * 2038 xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan, 2039 struct dma_interleaved_template *xt, 2040 unsigned long flags) 2041 { 2042 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2043 struct xilinx_dma_tx_descriptor *desc; 2044 struct xilinx_vdma_tx_segment *segment; 2045 struct xilinx_vdma_desc_hw *hw; 2046 2047 if (!is_slave_direction(xt->dir)) 2048 return NULL; 2049 2050 if (!xt->numf || !xt->sgl[0].size) 2051 return NULL; 2052 2053 if (xt->frame_size != 1) 2054 return NULL; 2055 2056 /* Allocate a transaction descriptor. */ 2057 desc = xilinx_dma_alloc_tx_descriptor(chan); 2058 if (!desc) 2059 return NULL; 2060 2061 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2062 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2063 async_tx_ack(&desc->async_tx); 2064 2065 /* Allocate the link descriptor from DMA pool */ 2066 segment = xilinx_vdma_alloc_tx_segment(chan); 2067 if (!segment) 2068 goto error; 2069 2070 /* Fill in the hardware descriptor */ 2071 hw = &segment->hw; 2072 hw->vsize = xt->numf; 2073 hw->hsize = xt->sgl[0].size; 2074 hw->stride = (xt->sgl[0].icg + xt->sgl[0].size) << 2075 XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT; 2076 hw->stride |= chan->config.frm_dly << 2077 XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT; 2078 2079 if (xt->dir != DMA_MEM_TO_DEV) { 2080 if (chan->ext_addr) { 2081 hw->buf_addr = lower_32_bits(xt->dst_start); 2082 hw->buf_addr_msb = upper_32_bits(xt->dst_start); 2083 } else { 2084 hw->buf_addr = xt->dst_start; 2085 } 2086 } else { 2087 if (chan->ext_addr) { 2088 hw->buf_addr = lower_32_bits(xt->src_start); 2089 hw->buf_addr_msb = upper_32_bits(xt->src_start); 2090 } else { 2091 hw->buf_addr = xt->src_start; 2092 } 2093 } 2094 2095 /* Insert the segment into the descriptor segments list. */ 2096 list_add_tail(&segment->node, &desc->segments); 2097 2098 /* Link the last hardware descriptor with the first. */ 2099 segment = list_first_entry(&desc->segments, 2100 struct xilinx_vdma_tx_segment, node); 2101 desc->async_tx.phys = segment->phys; 2102 2103 return &desc->async_tx; 2104 2105 error: 2106 xilinx_dma_free_tx_descriptor(chan, desc); 2107 return NULL; 2108 } 2109 2110 /** 2111 * xilinx_cdma_prep_memcpy - prepare descriptors for a memcpy transaction 2112 * @dchan: DMA channel 2113 * @dma_dst: destination address 2114 * @dma_src: source address 2115 * @len: transfer length 2116 * @flags: transfer ack flags 2117 * 2118 * Return: Async transaction descriptor on success and NULL on failure 2119 */ 2120 static struct dma_async_tx_descriptor * 2121 xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst, 2122 dma_addr_t dma_src, size_t len, unsigned long flags) 2123 { 2124 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2125 struct xilinx_dma_tx_descriptor *desc; 2126 struct xilinx_cdma_tx_segment *segment; 2127 struct xilinx_cdma_desc_hw *hw; 2128 2129 if (!len || len > chan->xdev->max_buffer_len) 2130 return NULL; 2131 2132 desc = xilinx_dma_alloc_tx_descriptor(chan); 2133 if (!desc) 2134 return NULL; 2135 2136 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2137 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2138 2139 /* Allocate the link descriptor from DMA pool */ 2140 segment = xilinx_cdma_alloc_tx_segment(chan); 2141 if (!segment) 2142 goto error; 2143 2144 hw = &segment->hw; 2145 hw->control = len; 2146 hw->src_addr = dma_src; 2147 hw->dest_addr = dma_dst; 2148 if (chan->ext_addr) { 2149 hw->src_addr_msb = upper_32_bits(dma_src); 2150 hw->dest_addr_msb = upper_32_bits(dma_dst); 2151 } 2152 2153 /* Insert the segment into the descriptor segments list. */ 2154 list_add_tail(&segment->node, &desc->segments); 2155 2156 desc->async_tx.phys = segment->phys; 2157 hw->next_desc = segment->phys; 2158 2159 return &desc->async_tx; 2160 2161 error: 2162 xilinx_dma_free_tx_descriptor(chan, desc); 2163 return NULL; 2164 } 2165 2166 /** 2167 * xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction 2168 * @dchan: DMA channel 2169 * @sgl: scatterlist to transfer to/from 2170 * @sg_len: number of entries in @scatterlist 2171 * @direction: DMA direction 2172 * @flags: transfer ack flags 2173 * @context: APP words of the descriptor 2174 * 2175 * Return: Async transaction descriptor on success and NULL on failure 2176 */ 2177 static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( 2178 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, 2179 enum dma_transfer_direction direction, unsigned long flags, 2180 void *context) 2181 { 2182 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2183 struct xilinx_dma_tx_descriptor *desc; 2184 struct xilinx_axidma_tx_segment *segment = NULL; 2185 u32 *app_w = (u32 *)context; 2186 struct scatterlist *sg; 2187 size_t copy; 2188 size_t sg_used; 2189 unsigned int i; 2190 2191 if (!is_slave_direction(direction)) 2192 return NULL; 2193 2194 /* Allocate a transaction descriptor. */ 2195 desc = xilinx_dma_alloc_tx_descriptor(chan); 2196 if (!desc) 2197 return NULL; 2198 2199 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2200 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2201 2202 /* Build transactions using information in the scatter gather list */ 2203 for_each_sg(sgl, sg, sg_len, i) { 2204 sg_used = 0; 2205 2206 /* Loop until the entire scatterlist entry is used */ 2207 while (sg_used < sg_dma_len(sg)) { 2208 struct xilinx_axidma_desc_hw *hw; 2209 2210 /* Get a free segment */ 2211 segment = xilinx_axidma_alloc_tx_segment(chan); 2212 if (!segment) 2213 goto error; 2214 2215 /* 2216 * Calculate the maximum number of bytes to transfer, 2217 * making sure it is less than the hw limit 2218 */ 2219 copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg), 2220 sg_used); 2221 hw = &segment->hw; 2222 2223 /* Fill in the descriptor */ 2224 xilinx_axidma_buf(chan, hw, sg_dma_address(sg), 2225 sg_used, 0); 2226 2227 hw->control = copy; 2228 2229 if (chan->direction == DMA_MEM_TO_DEV) { 2230 if (app_w) 2231 memcpy(hw->app, app_w, sizeof(u32) * 2232 XILINX_DMA_NUM_APP_WORDS); 2233 } 2234 2235 sg_used += copy; 2236 2237 /* 2238 * Insert the segment into the descriptor segments 2239 * list. 2240 */ 2241 list_add_tail(&segment->node, &desc->segments); 2242 } 2243 } 2244 2245 segment = list_first_entry(&desc->segments, 2246 struct xilinx_axidma_tx_segment, node); 2247 desc->async_tx.phys = segment->phys; 2248 2249 /* For the last DMA_MEM_TO_DEV transfer, set EOP */ 2250 if (chan->direction == DMA_MEM_TO_DEV) { 2251 segment->hw.control |= XILINX_DMA_BD_SOP; 2252 segment = list_last_entry(&desc->segments, 2253 struct xilinx_axidma_tx_segment, 2254 node); 2255 segment->hw.control |= XILINX_DMA_BD_EOP; 2256 } 2257 2258 if (chan->xdev->has_axistream_connected) 2259 desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops; 2260 2261 return &desc->async_tx; 2262 2263 error: 2264 xilinx_dma_free_tx_descriptor(chan, desc); 2265 return NULL; 2266 } 2267 2268 /** 2269 * xilinx_dma_prep_dma_cyclic - prepare descriptors for a DMA_SLAVE transaction 2270 * @dchan: DMA channel 2271 * @buf_addr: Physical address of the buffer 2272 * @buf_len: Total length of the cyclic buffers 2273 * @period_len: length of individual cyclic buffer 2274 * @direction: DMA direction 2275 * @flags: transfer ack flags 2276 * 2277 * Return: Async transaction descriptor on success and NULL on failure 2278 */ 2279 static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic( 2280 struct dma_chan *dchan, dma_addr_t buf_addr, size_t buf_len, 2281 size_t period_len, enum dma_transfer_direction direction, 2282 unsigned long flags) 2283 { 2284 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2285 struct xilinx_dma_tx_descriptor *desc; 2286 struct xilinx_axidma_tx_segment *segment, *head_segment, *prev = NULL; 2287 size_t copy, sg_used; 2288 unsigned int num_periods; 2289 int i; 2290 u32 reg; 2291 2292 if (!period_len) 2293 return NULL; 2294 2295 num_periods = buf_len / period_len; 2296 2297 if (!num_periods) 2298 return NULL; 2299 2300 if (!is_slave_direction(direction)) 2301 return NULL; 2302 2303 /* Allocate a transaction descriptor. */ 2304 desc = xilinx_dma_alloc_tx_descriptor(chan); 2305 if (!desc) 2306 return NULL; 2307 2308 chan->direction = direction; 2309 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2310 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2311 2312 for (i = 0; i < num_periods; ++i) { 2313 sg_used = 0; 2314 2315 while (sg_used < period_len) { 2316 struct xilinx_axidma_desc_hw *hw; 2317 2318 /* Get a free segment */ 2319 segment = xilinx_axidma_alloc_tx_segment(chan); 2320 if (!segment) 2321 goto error; 2322 2323 /* 2324 * Calculate the maximum number of bytes to transfer, 2325 * making sure it is less than the hw limit 2326 */ 2327 copy = xilinx_dma_calc_copysize(chan, period_len, 2328 sg_used); 2329 hw = &segment->hw; 2330 xilinx_axidma_buf(chan, hw, buf_addr, sg_used, 2331 period_len * i); 2332 hw->control = copy; 2333 2334 if (prev) 2335 prev->hw.next_desc = segment->phys; 2336 2337 prev = segment; 2338 sg_used += copy; 2339 2340 /* 2341 * Insert the segment into the descriptor segments 2342 * list. 2343 */ 2344 list_add_tail(&segment->node, &desc->segments); 2345 } 2346 } 2347 2348 head_segment = list_first_entry(&desc->segments, 2349 struct xilinx_axidma_tx_segment, node); 2350 desc->async_tx.phys = head_segment->phys; 2351 2352 desc->cyclic = true; 2353 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 2354 reg |= XILINX_DMA_CR_CYCLIC_BD_EN_MASK; 2355 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); 2356 2357 segment = list_last_entry(&desc->segments, 2358 struct xilinx_axidma_tx_segment, 2359 node); 2360 segment->hw.next_desc = (u32) head_segment->phys; 2361 2362 /* For the last DMA_MEM_TO_DEV transfer, set EOP */ 2363 if (direction == DMA_MEM_TO_DEV) { 2364 head_segment->hw.control |= XILINX_DMA_BD_SOP; 2365 segment->hw.control |= XILINX_DMA_BD_EOP; 2366 } 2367 2368 return &desc->async_tx; 2369 2370 error: 2371 xilinx_dma_free_tx_descriptor(chan, desc); 2372 return NULL; 2373 } 2374 2375 /** 2376 * xilinx_mcdma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction 2377 * @dchan: DMA channel 2378 * @sgl: scatterlist to transfer to/from 2379 * @sg_len: number of entries in @scatterlist 2380 * @direction: DMA direction 2381 * @flags: transfer ack flags 2382 * @context: APP words of the descriptor 2383 * 2384 * Return: Async transaction descriptor on success and NULL on failure 2385 */ 2386 static struct dma_async_tx_descriptor * 2387 xilinx_mcdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, 2388 unsigned int sg_len, 2389 enum dma_transfer_direction direction, 2390 unsigned long flags, void *context) 2391 { 2392 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2393 struct xilinx_dma_tx_descriptor *desc; 2394 struct xilinx_aximcdma_tx_segment *segment = NULL; 2395 u32 *app_w = (u32 *)context; 2396 struct scatterlist *sg; 2397 size_t copy; 2398 size_t sg_used; 2399 unsigned int i; 2400 2401 if (!is_slave_direction(direction)) 2402 return NULL; 2403 2404 /* Allocate a transaction descriptor. */ 2405 desc = xilinx_dma_alloc_tx_descriptor(chan); 2406 if (!desc) 2407 return NULL; 2408 2409 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2410 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2411 2412 /* Build transactions using information in the scatter gather list */ 2413 for_each_sg(sgl, sg, sg_len, i) { 2414 sg_used = 0; 2415 2416 /* Loop until the entire scatterlist entry is used */ 2417 while (sg_used < sg_dma_len(sg)) { 2418 struct xilinx_aximcdma_desc_hw *hw; 2419 2420 /* Get a free segment */ 2421 segment = xilinx_aximcdma_alloc_tx_segment(chan); 2422 if (!segment) 2423 goto error; 2424 2425 /* 2426 * Calculate the maximum number of bytes to transfer, 2427 * making sure it is less than the hw limit 2428 */ 2429 copy = min_t(size_t, sg_dma_len(sg) - sg_used, 2430 chan->xdev->max_buffer_len); 2431 hw = &segment->hw; 2432 2433 /* Fill in the descriptor */ 2434 xilinx_aximcdma_buf(chan, hw, sg_dma_address(sg), 2435 sg_used); 2436 hw->control = copy; 2437 2438 if (chan->direction == DMA_MEM_TO_DEV && app_w) { 2439 memcpy(hw->app, app_w, sizeof(u32) * 2440 XILINX_DMA_NUM_APP_WORDS); 2441 } 2442 2443 sg_used += copy; 2444 /* 2445 * Insert the segment into the descriptor segments 2446 * list. 2447 */ 2448 list_add_tail(&segment->node, &desc->segments); 2449 } 2450 } 2451 2452 segment = list_first_entry(&desc->segments, 2453 struct xilinx_aximcdma_tx_segment, node); 2454 desc->async_tx.phys = segment->phys; 2455 2456 /* For the last DMA_MEM_TO_DEV transfer, set EOP */ 2457 if (chan->direction == DMA_MEM_TO_DEV) { 2458 segment->hw.control |= XILINX_MCDMA_BD_SOP; 2459 segment = list_last_entry(&desc->segments, 2460 struct xilinx_aximcdma_tx_segment, 2461 node); 2462 segment->hw.control |= XILINX_MCDMA_BD_EOP; 2463 } 2464 2465 return &desc->async_tx; 2466 2467 error: 2468 xilinx_dma_free_tx_descriptor(chan, desc); 2469 2470 return NULL; 2471 } 2472 2473 /** 2474 * xilinx_dma_terminate_all - Halt the channel and free descriptors 2475 * @dchan: Driver specific DMA Channel pointer 2476 * 2477 * Return: '0' always. 2478 */ 2479 static int xilinx_dma_terminate_all(struct dma_chan *dchan) 2480 { 2481 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2482 u32 reg; 2483 int err; 2484 2485 if (!chan->cyclic) { 2486 err = chan->stop_transfer(chan); 2487 if (err) { 2488 dev_err(chan->dev, "Cannot stop channel %p: %x\n", 2489 chan, dma_ctrl_read(chan, 2490 XILINX_DMA_REG_DMASR)); 2491 chan->err = true; 2492 } 2493 } 2494 2495 xilinx_dma_chan_reset(chan); 2496 /* Remove and free all of the descriptors in the lists */ 2497 chan->terminating = true; 2498 xilinx_dma_free_descriptors(chan); 2499 chan->idle = true; 2500 2501 if (chan->cyclic) { 2502 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 2503 reg &= ~XILINX_DMA_CR_CYCLIC_BD_EN_MASK; 2504 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); 2505 chan->cyclic = false; 2506 } 2507 2508 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) 2509 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, 2510 XILINX_CDMA_CR_SGMODE); 2511 2512 return 0; 2513 } 2514 2515 static void xilinx_dma_synchronize(struct dma_chan *dchan) 2516 { 2517 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2518 2519 tasklet_kill(&chan->tasklet); 2520 } 2521 2522 /** 2523 * xilinx_vdma_channel_set_config - Configure VDMA channel 2524 * Run-time configuration for Axi VDMA, supports: 2525 * . halt the channel 2526 * . configure interrupt coalescing and inter-packet delay threshold 2527 * . start/stop parking 2528 * . enable genlock 2529 * 2530 * @dchan: DMA channel 2531 * @cfg: VDMA device configuration pointer 2532 * 2533 * Return: '0' on success and failure value on error 2534 */ 2535 int xilinx_vdma_channel_set_config(struct dma_chan *dchan, 2536 struct xilinx_vdma_config *cfg) 2537 { 2538 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2539 u32 dmacr; 2540 2541 if (cfg->reset) 2542 return xilinx_dma_chan_reset(chan); 2543 2544 dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 2545 2546 chan->config.frm_dly = cfg->frm_dly; 2547 chan->config.park = cfg->park; 2548 2549 /* genlock settings */ 2550 chan->config.gen_lock = cfg->gen_lock; 2551 chan->config.master = cfg->master; 2552 2553 dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN; 2554 if (cfg->gen_lock && chan->genlock) { 2555 dmacr |= XILINX_DMA_DMACR_GENLOCK_EN; 2556 dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK; 2557 dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT; 2558 } 2559 2560 chan->config.frm_cnt_en = cfg->frm_cnt_en; 2561 chan->config.vflip_en = cfg->vflip_en; 2562 2563 if (cfg->park) 2564 chan->config.park_frm = cfg->park_frm; 2565 else 2566 chan->config.park_frm = -1; 2567 2568 chan->config.coalesc = cfg->coalesc; 2569 chan->config.delay = cfg->delay; 2570 2571 if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) { 2572 dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK; 2573 dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT; 2574 chan->config.coalesc = cfg->coalesc; 2575 } 2576 2577 if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) { 2578 dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK; 2579 dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT; 2580 chan->config.delay = cfg->delay; 2581 } 2582 2583 /* FSync Source selection */ 2584 dmacr &= ~XILINX_DMA_DMACR_FSYNCSRC_MASK; 2585 dmacr |= cfg->ext_fsync << XILINX_DMA_DMACR_FSYNCSRC_SHIFT; 2586 2587 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr); 2588 2589 return 0; 2590 } 2591 EXPORT_SYMBOL(xilinx_vdma_channel_set_config); 2592 2593 /* ----------------------------------------------------------------------------- 2594 * Probe and remove 2595 */ 2596 2597 /** 2598 * xilinx_dma_chan_remove - Per Channel remove function 2599 * @chan: Driver specific DMA channel 2600 */ 2601 static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan) 2602 { 2603 /* Disable all interrupts */ 2604 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, 2605 XILINX_DMA_DMAXR_ALL_IRQ_MASK); 2606 2607 if (chan->irq > 0) 2608 free_irq(chan->irq, chan); 2609 2610 tasklet_kill(&chan->tasklet); 2611 2612 list_del(&chan->common.device_node); 2613 } 2614 2615 static int axidma_clk_init(struct platform_device *pdev, struct clk **axi_clk, 2616 struct clk **tx_clk, struct clk **rx_clk, 2617 struct clk **sg_clk, struct clk **tmp_clk) 2618 { 2619 int err; 2620 2621 *tmp_clk = NULL; 2622 2623 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); 2624 if (IS_ERR(*axi_clk)) 2625 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n"); 2626 2627 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk"); 2628 if (IS_ERR(*tx_clk)) 2629 *tx_clk = NULL; 2630 2631 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk"); 2632 if (IS_ERR(*rx_clk)) 2633 *rx_clk = NULL; 2634 2635 *sg_clk = devm_clk_get(&pdev->dev, "m_axi_sg_aclk"); 2636 if (IS_ERR(*sg_clk)) 2637 *sg_clk = NULL; 2638 2639 err = clk_prepare_enable(*axi_clk); 2640 if (err) { 2641 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err); 2642 return err; 2643 } 2644 2645 err = clk_prepare_enable(*tx_clk); 2646 if (err) { 2647 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); 2648 goto err_disable_axiclk; 2649 } 2650 2651 err = clk_prepare_enable(*rx_clk); 2652 if (err) { 2653 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); 2654 goto err_disable_txclk; 2655 } 2656 2657 err = clk_prepare_enable(*sg_clk); 2658 if (err) { 2659 dev_err(&pdev->dev, "failed to enable sg_clk (%d)\n", err); 2660 goto err_disable_rxclk; 2661 } 2662 2663 return 0; 2664 2665 err_disable_rxclk: 2666 clk_disable_unprepare(*rx_clk); 2667 err_disable_txclk: 2668 clk_disable_unprepare(*tx_clk); 2669 err_disable_axiclk: 2670 clk_disable_unprepare(*axi_clk); 2671 2672 return err; 2673 } 2674 2675 static int axicdma_clk_init(struct platform_device *pdev, struct clk **axi_clk, 2676 struct clk **dev_clk, struct clk **tmp_clk, 2677 struct clk **tmp1_clk, struct clk **tmp2_clk) 2678 { 2679 int err; 2680 2681 *tmp_clk = NULL; 2682 *tmp1_clk = NULL; 2683 *tmp2_clk = NULL; 2684 2685 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); 2686 if (IS_ERR(*axi_clk)) 2687 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n"); 2688 2689 *dev_clk = devm_clk_get(&pdev->dev, "m_axi_aclk"); 2690 if (IS_ERR(*dev_clk)) 2691 return dev_err_probe(&pdev->dev, PTR_ERR(*dev_clk), "failed to get dev_clk\n"); 2692 2693 err = clk_prepare_enable(*axi_clk); 2694 if (err) { 2695 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err); 2696 return err; 2697 } 2698 2699 err = clk_prepare_enable(*dev_clk); 2700 if (err) { 2701 dev_err(&pdev->dev, "failed to enable dev_clk (%d)\n", err); 2702 goto err_disable_axiclk; 2703 } 2704 2705 return 0; 2706 2707 err_disable_axiclk: 2708 clk_disable_unprepare(*axi_clk); 2709 2710 return err; 2711 } 2712 2713 static int axivdma_clk_init(struct platform_device *pdev, struct clk **axi_clk, 2714 struct clk **tx_clk, struct clk **txs_clk, 2715 struct clk **rx_clk, struct clk **rxs_clk) 2716 { 2717 int err; 2718 2719 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); 2720 if (IS_ERR(*axi_clk)) 2721 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n"); 2722 2723 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk"); 2724 if (IS_ERR(*tx_clk)) 2725 *tx_clk = NULL; 2726 2727 *txs_clk = devm_clk_get(&pdev->dev, "m_axis_mm2s_aclk"); 2728 if (IS_ERR(*txs_clk)) 2729 *txs_clk = NULL; 2730 2731 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk"); 2732 if (IS_ERR(*rx_clk)) 2733 *rx_clk = NULL; 2734 2735 *rxs_clk = devm_clk_get(&pdev->dev, "s_axis_s2mm_aclk"); 2736 if (IS_ERR(*rxs_clk)) 2737 *rxs_clk = NULL; 2738 2739 err = clk_prepare_enable(*axi_clk); 2740 if (err) { 2741 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", 2742 err); 2743 return err; 2744 } 2745 2746 err = clk_prepare_enable(*tx_clk); 2747 if (err) { 2748 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); 2749 goto err_disable_axiclk; 2750 } 2751 2752 err = clk_prepare_enable(*txs_clk); 2753 if (err) { 2754 dev_err(&pdev->dev, "failed to enable txs_clk (%d)\n", err); 2755 goto err_disable_txclk; 2756 } 2757 2758 err = clk_prepare_enable(*rx_clk); 2759 if (err) { 2760 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); 2761 goto err_disable_txsclk; 2762 } 2763 2764 err = clk_prepare_enable(*rxs_clk); 2765 if (err) { 2766 dev_err(&pdev->dev, "failed to enable rxs_clk (%d)\n", err); 2767 goto err_disable_rxclk; 2768 } 2769 2770 return 0; 2771 2772 err_disable_rxclk: 2773 clk_disable_unprepare(*rx_clk); 2774 err_disable_txsclk: 2775 clk_disable_unprepare(*txs_clk); 2776 err_disable_txclk: 2777 clk_disable_unprepare(*tx_clk); 2778 err_disable_axiclk: 2779 clk_disable_unprepare(*axi_clk); 2780 2781 return err; 2782 } 2783 2784 static void xdma_disable_allclks(struct xilinx_dma_device *xdev) 2785 { 2786 clk_disable_unprepare(xdev->rxs_clk); 2787 clk_disable_unprepare(xdev->rx_clk); 2788 clk_disable_unprepare(xdev->txs_clk); 2789 clk_disable_unprepare(xdev->tx_clk); 2790 clk_disable_unprepare(xdev->axi_clk); 2791 } 2792 2793 /** 2794 * xilinx_dma_chan_probe - Per Channel Probing 2795 * It get channel features from the device tree entry and 2796 * initialize special channel handling routines 2797 * 2798 * @xdev: Driver specific device structure 2799 * @node: Device node 2800 * 2801 * Return: '0' on success and failure value on error 2802 */ 2803 static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, 2804 struct device_node *node) 2805 { 2806 struct xilinx_dma_chan *chan; 2807 bool has_dre = false; 2808 u32 value, width; 2809 int err; 2810 2811 /* Allocate and initialize the channel structure */ 2812 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL); 2813 if (!chan) 2814 return -ENOMEM; 2815 2816 chan->dev = xdev->dev; 2817 chan->xdev = xdev; 2818 chan->desc_pendingcount = 0x0; 2819 chan->ext_addr = xdev->ext_addr; 2820 /* This variable ensures that descriptors are not 2821 * Submitted when dma engine is in progress. This variable is 2822 * Added to avoid polling for a bit in the status register to 2823 * Know dma state in the driver hot path. 2824 */ 2825 chan->idle = true; 2826 2827 spin_lock_init(&chan->lock); 2828 INIT_LIST_HEAD(&chan->pending_list); 2829 INIT_LIST_HEAD(&chan->done_list); 2830 INIT_LIST_HEAD(&chan->active_list); 2831 INIT_LIST_HEAD(&chan->free_seg_list); 2832 2833 /* Retrieve the channel properties from the device tree */ 2834 has_dre = of_property_read_bool(node, "xlnx,include-dre"); 2835 2836 chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode"); 2837 2838 err = of_property_read_u32(node, "xlnx,datawidth", &value); 2839 if (err) { 2840 dev_err(xdev->dev, "missing xlnx,datawidth property\n"); 2841 return err; 2842 } 2843 width = value >> 3; /* Convert bits to bytes */ 2844 2845 /* If data width is greater than 8 bytes, DRE is not in hw */ 2846 if (width > 8) 2847 has_dre = false; 2848 2849 if (!has_dre) 2850 xdev->common.copy_align = (enum dmaengine_alignment)fls(width - 1); 2851 2852 if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel") || 2853 of_device_is_compatible(node, "xlnx,axi-dma-mm2s-channel") || 2854 of_device_is_compatible(node, "xlnx,axi-cdma-channel")) { 2855 chan->direction = DMA_MEM_TO_DEV; 2856 chan->id = xdev->mm2s_chan_id++; 2857 chan->tdest = chan->id; 2858 2859 chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; 2860 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 2861 chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET; 2862 chan->config.park = 1; 2863 2864 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH || 2865 xdev->flush_on_fsync == XILINX_DMA_FLUSH_MM2S) 2866 chan->flush_on_fsync = true; 2867 } 2868 } else if (of_device_is_compatible(node, 2869 "xlnx,axi-vdma-s2mm-channel") || 2870 of_device_is_compatible(node, 2871 "xlnx,axi-dma-s2mm-channel")) { 2872 chan->direction = DMA_DEV_TO_MEM; 2873 chan->id = xdev->s2mm_chan_id++; 2874 chan->tdest = chan->id - xdev->dma_config->max_channels / 2; 2875 chan->has_vflip = of_property_read_bool(node, 2876 "xlnx,enable-vert-flip"); 2877 if (chan->has_vflip) { 2878 chan->config.vflip_en = dma_read(chan, 2879 XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP) & 2880 XILINX_VDMA_ENABLE_VERTICAL_FLIP; 2881 } 2882 2883 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) 2884 chan->ctrl_offset = XILINX_MCDMA_S2MM_CTRL_OFFSET; 2885 else 2886 chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; 2887 2888 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 2889 chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET; 2890 chan->config.park = 1; 2891 2892 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH || 2893 xdev->flush_on_fsync == XILINX_DMA_FLUSH_S2MM) 2894 chan->flush_on_fsync = true; 2895 } 2896 } else { 2897 dev_err(xdev->dev, "Invalid channel compatible node\n"); 2898 return -EINVAL; 2899 } 2900 2901 /* Request the interrupt */ 2902 chan->irq = of_irq_get(node, chan->tdest); 2903 if (chan->irq < 0) 2904 return dev_err_probe(xdev->dev, chan->irq, "failed to get irq\n"); 2905 err = request_irq(chan->irq, xdev->dma_config->irq_handler, 2906 IRQF_SHARED, "xilinx-dma-controller", chan); 2907 if (err) { 2908 dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq); 2909 return err; 2910 } 2911 2912 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 2913 chan->start_transfer = xilinx_dma_start_transfer; 2914 chan->stop_transfer = xilinx_dma_stop_transfer; 2915 } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 2916 chan->start_transfer = xilinx_mcdma_start_transfer; 2917 chan->stop_transfer = xilinx_dma_stop_transfer; 2918 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 2919 chan->start_transfer = xilinx_cdma_start_transfer; 2920 chan->stop_transfer = xilinx_cdma_stop_transfer; 2921 } else { 2922 chan->start_transfer = xilinx_vdma_start_transfer; 2923 chan->stop_transfer = xilinx_dma_stop_transfer; 2924 } 2925 2926 /* check if SG is enabled (only for AXIDMA, AXIMCDMA, and CDMA) */ 2927 if (xdev->dma_config->dmatype != XDMA_TYPE_VDMA) { 2928 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA || 2929 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) & 2930 XILINX_DMA_DMASR_SG_MASK) 2931 chan->has_sg = true; 2932 dev_dbg(chan->dev, "ch %d: SG %s\n", chan->id, 2933 chan->has_sg ? "enabled" : "disabled"); 2934 } 2935 2936 /* Initialize the tasklet */ 2937 tasklet_setup(&chan->tasklet, xilinx_dma_do_tasklet); 2938 2939 /* 2940 * Initialize the DMA channel and add it to the DMA engine channels 2941 * list. 2942 */ 2943 chan->common.device = &xdev->common; 2944 2945 list_add_tail(&chan->common.device_node, &xdev->common.channels); 2946 xdev->chan[chan->id] = chan; 2947 2948 /* Reset the channel */ 2949 err = xilinx_dma_chan_reset(chan); 2950 if (err < 0) { 2951 dev_err(xdev->dev, "Reset channel failed\n"); 2952 return err; 2953 } 2954 2955 return 0; 2956 } 2957 2958 /** 2959 * xilinx_dma_child_probe - Per child node probe 2960 * It get number of dma-channels per child node from 2961 * device-tree and initializes all the channels. 2962 * 2963 * @xdev: Driver specific device structure 2964 * @node: Device node 2965 * 2966 * Return: '0' on success and failure value on error. 2967 */ 2968 static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev, 2969 struct device_node *node) 2970 { 2971 int ret, i; 2972 u32 nr_channels = 1; 2973 2974 ret = of_property_read_u32(node, "dma-channels", &nr_channels); 2975 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA && ret < 0) 2976 dev_warn(xdev->dev, "missing dma-channels property\n"); 2977 2978 for (i = 0; i < nr_channels; i++) { 2979 ret = xilinx_dma_chan_probe(xdev, node); 2980 if (ret) 2981 return ret; 2982 } 2983 2984 return 0; 2985 } 2986 2987 /** 2988 * of_dma_xilinx_xlate - Translation function 2989 * @dma_spec: Pointer to DMA specifier as found in the device tree 2990 * @ofdma: Pointer to DMA controller data 2991 * 2992 * Return: DMA channel pointer on success and NULL on error 2993 */ 2994 static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec, 2995 struct of_dma *ofdma) 2996 { 2997 struct xilinx_dma_device *xdev = ofdma->of_dma_data; 2998 int chan_id = dma_spec->args[0]; 2999 3000 if (chan_id >= xdev->dma_config->max_channels || !xdev->chan[chan_id]) 3001 return NULL; 3002 3003 return dma_get_slave_channel(&xdev->chan[chan_id]->common); 3004 } 3005 3006 static const struct xilinx_dma_config axidma_config = { 3007 .dmatype = XDMA_TYPE_AXIDMA, 3008 .clk_init = axidma_clk_init, 3009 .irq_handler = xilinx_dma_irq_handler, 3010 .max_channels = XILINX_DMA_MAX_CHANS_PER_DEVICE, 3011 }; 3012 3013 static const struct xilinx_dma_config aximcdma_config = { 3014 .dmatype = XDMA_TYPE_AXIMCDMA, 3015 .clk_init = axidma_clk_init, 3016 .irq_handler = xilinx_mcdma_irq_handler, 3017 .max_channels = XILINX_MCDMA_MAX_CHANS_PER_DEVICE, 3018 }; 3019 static const struct xilinx_dma_config axicdma_config = { 3020 .dmatype = XDMA_TYPE_CDMA, 3021 .clk_init = axicdma_clk_init, 3022 .irq_handler = xilinx_dma_irq_handler, 3023 .max_channels = XILINX_CDMA_MAX_CHANS_PER_DEVICE, 3024 }; 3025 3026 static const struct xilinx_dma_config axivdma_config = { 3027 .dmatype = XDMA_TYPE_VDMA, 3028 .clk_init = axivdma_clk_init, 3029 .irq_handler = xilinx_dma_irq_handler, 3030 .max_channels = XILINX_DMA_MAX_CHANS_PER_DEVICE, 3031 }; 3032 3033 static const struct of_device_id xilinx_dma_of_ids[] = { 3034 { .compatible = "xlnx,axi-dma-1.00.a", .data = &axidma_config }, 3035 { .compatible = "xlnx,axi-cdma-1.00.a", .data = &axicdma_config }, 3036 { .compatible = "xlnx,axi-vdma-1.00.a", .data = &axivdma_config }, 3037 { .compatible = "xlnx,axi-mcdma-1.00.a", .data = &aximcdma_config }, 3038 {} 3039 }; 3040 MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids); 3041 3042 /** 3043 * xilinx_dma_probe - Driver probe function 3044 * @pdev: Pointer to the platform_device structure 3045 * 3046 * Return: '0' on success and failure value on error 3047 */ 3048 static int xilinx_dma_probe(struct platform_device *pdev) 3049 { 3050 int (*clk_init)(struct platform_device *, struct clk **, struct clk **, 3051 struct clk **, struct clk **, struct clk **) 3052 = axivdma_clk_init; 3053 struct device_node *node = pdev->dev.of_node; 3054 struct xilinx_dma_device *xdev; 3055 struct device_node *child, *np = pdev->dev.of_node; 3056 u32 num_frames, addr_width, len_width; 3057 int i, err; 3058 3059 /* Allocate and initialize the DMA engine structure */ 3060 xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL); 3061 if (!xdev) 3062 return -ENOMEM; 3063 3064 xdev->dev = &pdev->dev; 3065 if (np) { 3066 const struct of_device_id *match; 3067 3068 match = of_match_node(xilinx_dma_of_ids, np); 3069 if (match && match->data) { 3070 xdev->dma_config = match->data; 3071 clk_init = xdev->dma_config->clk_init; 3072 } 3073 } 3074 3075 err = clk_init(pdev, &xdev->axi_clk, &xdev->tx_clk, &xdev->txs_clk, 3076 &xdev->rx_clk, &xdev->rxs_clk); 3077 if (err) 3078 return err; 3079 3080 /* Request and map I/O memory */ 3081 xdev->regs = devm_platform_ioremap_resource(pdev, 0); 3082 if (IS_ERR(xdev->regs)) { 3083 err = PTR_ERR(xdev->regs); 3084 goto disable_clks; 3085 } 3086 /* Retrieve the DMA engine properties from the device tree */ 3087 xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0); 3088 xdev->s2mm_chan_id = xdev->dma_config->max_channels / 2; 3089 3090 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA || 3091 xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 3092 if (!of_property_read_u32(node, "xlnx,sg-length-width", 3093 &len_width)) { 3094 if (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN || 3095 len_width > XILINX_DMA_V2_MAX_TRANS_LEN_MAX) { 3096 dev_warn(xdev->dev, 3097 "invalid xlnx,sg-length-width property value. Using default width\n"); 3098 } else { 3099 if (len_width > XILINX_DMA_MAX_TRANS_LEN_MAX) 3100 dev_warn(xdev->dev, "Please ensure that IP supports buffer length > 23 bits\n"); 3101 xdev->max_buffer_len = 3102 GENMASK(len_width - 1, 0); 3103 } 3104 } 3105 } 3106 3107 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 3108 xdev->has_axistream_connected = 3109 of_property_read_bool(node, "xlnx,axistream-connected"); 3110 } 3111 3112 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 3113 err = of_property_read_u32(node, "xlnx,num-fstores", 3114 &num_frames); 3115 if (err < 0) { 3116 dev_err(xdev->dev, 3117 "missing xlnx,num-fstores property\n"); 3118 goto disable_clks; 3119 } 3120 3121 err = of_property_read_u32(node, "xlnx,flush-fsync", 3122 &xdev->flush_on_fsync); 3123 if (err < 0) 3124 dev_warn(xdev->dev, 3125 "missing xlnx,flush-fsync property\n"); 3126 } 3127 3128 err = of_property_read_u32(node, "xlnx,addrwidth", &addr_width); 3129 if (err < 0) 3130 dev_warn(xdev->dev, "missing xlnx,addrwidth property\n"); 3131 3132 if (addr_width > 32) 3133 xdev->ext_addr = true; 3134 else 3135 xdev->ext_addr = false; 3136 3137 /* Set metadata mode */ 3138 if (xdev->has_axistream_connected) 3139 xdev->common.desc_metadata_modes = DESC_METADATA_ENGINE; 3140 3141 /* Set the dma mask bits */ 3142 err = dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width)); 3143 if (err < 0) { 3144 dev_err(xdev->dev, "DMA mask error %d\n", err); 3145 goto disable_clks; 3146 } 3147 3148 /* Initialize the DMA engine */ 3149 xdev->common.dev = &pdev->dev; 3150 3151 INIT_LIST_HEAD(&xdev->common.channels); 3152 if (!(xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) { 3153 dma_cap_set(DMA_SLAVE, xdev->common.cap_mask); 3154 dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask); 3155 } 3156 3157 xdev->common.device_alloc_chan_resources = 3158 xilinx_dma_alloc_chan_resources; 3159 xdev->common.device_free_chan_resources = 3160 xilinx_dma_free_chan_resources; 3161 xdev->common.device_terminate_all = xilinx_dma_terminate_all; 3162 xdev->common.device_synchronize = xilinx_dma_synchronize; 3163 xdev->common.device_tx_status = xilinx_dma_tx_status; 3164 xdev->common.device_issue_pending = xilinx_dma_issue_pending; 3165 xdev->common.device_config = xilinx_dma_device_config; 3166 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 3167 dma_cap_set(DMA_CYCLIC, xdev->common.cap_mask); 3168 xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg; 3169 xdev->common.device_prep_dma_cyclic = 3170 xilinx_dma_prep_dma_cyclic; 3171 /* Residue calculation is supported by only AXI DMA and CDMA */ 3172 xdev->common.residue_granularity = 3173 DMA_RESIDUE_GRANULARITY_SEGMENT; 3174 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 3175 dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask); 3176 xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy; 3177 /* Residue calculation is supported by only AXI DMA and CDMA */ 3178 xdev->common.residue_granularity = 3179 DMA_RESIDUE_GRANULARITY_SEGMENT; 3180 } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 3181 xdev->common.device_prep_slave_sg = xilinx_mcdma_prep_slave_sg; 3182 } else { 3183 xdev->common.device_prep_interleaved_dma = 3184 xilinx_vdma_dma_prep_interleaved; 3185 } 3186 3187 platform_set_drvdata(pdev, xdev); 3188 3189 /* Initialize the channels */ 3190 for_each_child_of_node(node, child) { 3191 err = xilinx_dma_child_probe(xdev, child); 3192 if (err < 0) { 3193 of_node_put(child); 3194 goto error; 3195 } 3196 } 3197 3198 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 3199 for (i = 0; i < xdev->dma_config->max_channels; i++) 3200 if (xdev->chan[i]) 3201 xdev->chan[i]->num_frms = num_frames; 3202 } 3203 3204 /* Register the DMA engine with the core */ 3205 err = dma_async_device_register(&xdev->common); 3206 if (err) { 3207 dev_err(xdev->dev, "failed to register the dma device\n"); 3208 goto error; 3209 } 3210 3211 err = of_dma_controller_register(node, of_dma_xilinx_xlate, 3212 xdev); 3213 if (err < 0) { 3214 dev_err(&pdev->dev, "Unable to register DMA to DT\n"); 3215 dma_async_device_unregister(&xdev->common); 3216 goto error; 3217 } 3218 3219 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) 3220 dev_info(&pdev->dev, "Xilinx AXI DMA Engine Driver Probed!!\n"); 3221 else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) 3222 dev_info(&pdev->dev, "Xilinx AXI CDMA Engine Driver Probed!!\n"); 3223 else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) 3224 dev_info(&pdev->dev, "Xilinx AXI MCDMA Engine Driver Probed!!\n"); 3225 else 3226 dev_info(&pdev->dev, "Xilinx AXI VDMA Engine Driver Probed!!\n"); 3227 3228 return 0; 3229 3230 error: 3231 for (i = 0; i < xdev->dma_config->max_channels; i++) 3232 if (xdev->chan[i]) 3233 xilinx_dma_chan_remove(xdev->chan[i]); 3234 disable_clks: 3235 xdma_disable_allclks(xdev); 3236 3237 return err; 3238 } 3239 3240 /** 3241 * xilinx_dma_remove - Driver remove function 3242 * @pdev: Pointer to the platform_device structure 3243 * 3244 * Return: Always '0' 3245 */ 3246 static int xilinx_dma_remove(struct platform_device *pdev) 3247 { 3248 struct xilinx_dma_device *xdev = platform_get_drvdata(pdev); 3249 int i; 3250 3251 of_dma_controller_free(pdev->dev.of_node); 3252 3253 dma_async_device_unregister(&xdev->common); 3254 3255 for (i = 0; i < xdev->dma_config->max_channels; i++) 3256 if (xdev->chan[i]) 3257 xilinx_dma_chan_remove(xdev->chan[i]); 3258 3259 xdma_disable_allclks(xdev); 3260 3261 return 0; 3262 } 3263 3264 static struct platform_driver xilinx_vdma_driver = { 3265 .driver = { 3266 .name = "xilinx-vdma", 3267 .of_match_table = xilinx_dma_of_ids, 3268 }, 3269 .probe = xilinx_dma_probe, 3270 .remove = xilinx_dma_remove, 3271 }; 3272 3273 module_platform_driver(xilinx_vdma_driver); 3274 3275 MODULE_AUTHOR("Xilinx, Inc."); 3276 MODULE_DESCRIPTION("Xilinx VDMA driver"); 3277 MODULE_LICENSE("GPL v2"); 3278