1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DMA driver for Xilinx Video DMA Engine 4 * 5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved. 6 * 7 * Based on the Freescale DMA driver. 8 * 9 * Description: 10 * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP 11 * core that provides high-bandwidth direct memory access between memory 12 * and AXI4-Stream type video target peripherals. The core provides efficient 13 * two dimensional DMA operations with independent asynchronous read (S2MM) 14 * and write (MM2S) channel operation. It can be configured to have either 15 * one channel or two channels. If configured as two channels, one is to 16 * transmit to the video device (MM2S) and another is to receive from the 17 * video device (S2MM). Initialization, status, interrupt and management 18 * registers are accessed through an AXI4-Lite slave interface. 19 * 20 * The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core that 21 * provides high-bandwidth one dimensional direct memory access between memory 22 * and AXI4-Stream target peripherals. It supports one receive and one 23 * transmit channel, both of them optional at synthesis time. 24 * 25 * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory 26 * Access (DMA) between a memory-mapped source address and a memory-mapped 27 * destination address. 28 * 29 * The AXI Multichannel Direct Memory Access (AXI MCDMA) core is a soft 30 * Xilinx IP that provides high-bandwidth direct memory access between 31 * memory and AXI4-Stream target peripherals. It provides scatter gather 32 * (SG) interface with multiple channels independent configuration support. 33 * 34 */ 35 36 #include <linux/bitops.h> 37 #include <linux/dmapool.h> 38 #include <linux/dma/xilinx_dma.h> 39 #include <linux/init.h> 40 #include <linux/interrupt.h> 41 #include <linux/io.h> 42 #include <linux/iopoll.h> 43 #include <linux/module.h> 44 #include <linux/of.h> 45 #include <linux/of_dma.h> 46 #include <linux/of_irq.h> 47 #include <linux/platform_device.h> 48 #include <linux/slab.h> 49 #include <linux/clk.h> 50 #include <linux/io-64-nonatomic-lo-hi.h> 51 52 #include "../dmaengine.h" 53 54 /* Register/Descriptor Offsets */ 55 #define XILINX_DMA_MM2S_CTRL_OFFSET 0x0000 56 #define XILINX_DMA_S2MM_CTRL_OFFSET 0x0030 57 #define XILINX_VDMA_MM2S_DESC_OFFSET 0x0050 58 #define XILINX_VDMA_S2MM_DESC_OFFSET 0x00a0 59 60 /* Control Registers */ 61 #define XILINX_DMA_REG_DMACR 0x0000 62 #define XILINX_DMA_DMACR_DELAY_MAX 0xff 63 #define XILINX_DMA_DMACR_DELAY_SHIFT 24 64 #define XILINX_DMA_DMACR_FRAME_COUNT_MAX 0xff 65 #define XILINX_DMA_DMACR_FRAME_COUNT_SHIFT 16 66 #define XILINX_DMA_DMACR_ERR_IRQ BIT(14) 67 #define XILINX_DMA_DMACR_DLY_CNT_IRQ BIT(13) 68 #define XILINX_DMA_DMACR_FRM_CNT_IRQ BIT(12) 69 #define XILINX_DMA_DMACR_MASTER_SHIFT 8 70 #define XILINX_DMA_DMACR_FSYNCSRC_SHIFT 5 71 #define XILINX_DMA_DMACR_FRAMECNT_EN BIT(4) 72 #define XILINX_DMA_DMACR_GENLOCK_EN BIT(3) 73 #define XILINX_DMA_DMACR_RESET BIT(2) 74 #define XILINX_DMA_DMACR_CIRC_EN BIT(1) 75 #define XILINX_DMA_DMACR_RUNSTOP BIT(0) 76 #define XILINX_DMA_DMACR_FSYNCSRC_MASK GENMASK(6, 5) 77 #define XILINX_DMA_DMACR_DELAY_MASK GENMASK(31, 24) 78 #define XILINX_DMA_DMACR_FRAME_COUNT_MASK GENMASK(23, 16) 79 #define XILINX_DMA_DMACR_MASTER_MASK GENMASK(11, 8) 80 81 #define XILINX_DMA_REG_DMASR 0x0004 82 #define XILINX_DMA_DMASR_EOL_LATE_ERR BIT(15) 83 #define XILINX_DMA_DMASR_ERR_IRQ BIT(14) 84 #define XILINX_DMA_DMASR_DLY_CNT_IRQ BIT(13) 85 #define XILINX_DMA_DMASR_FRM_CNT_IRQ BIT(12) 86 #define XILINX_DMA_DMASR_SOF_LATE_ERR BIT(11) 87 #define XILINX_DMA_DMASR_SG_DEC_ERR BIT(10) 88 #define XILINX_DMA_DMASR_SG_SLV_ERR BIT(9) 89 #define XILINX_DMA_DMASR_EOF_EARLY_ERR BIT(8) 90 #define XILINX_DMA_DMASR_SOF_EARLY_ERR BIT(7) 91 #define XILINX_DMA_DMASR_DMA_DEC_ERR BIT(6) 92 #define XILINX_DMA_DMASR_DMA_SLAVE_ERR BIT(5) 93 #define XILINX_DMA_DMASR_DMA_INT_ERR BIT(4) 94 #define XILINX_DMA_DMASR_SG_MASK BIT(3) 95 #define XILINX_DMA_DMASR_IDLE BIT(1) 96 #define XILINX_DMA_DMASR_HALTED BIT(0) 97 #define XILINX_DMA_DMASR_DELAY_MASK GENMASK(31, 24) 98 #define XILINX_DMA_DMASR_FRAME_COUNT_MASK GENMASK(23, 16) 99 100 #define XILINX_DMA_REG_CURDESC 0x0008 101 #define XILINX_DMA_REG_TAILDESC 0x0010 102 #define XILINX_DMA_REG_REG_INDEX 0x0014 103 #define XILINX_DMA_REG_FRMSTORE 0x0018 104 #define XILINX_DMA_REG_THRESHOLD 0x001c 105 #define XILINX_DMA_REG_FRMPTR_STS 0x0024 106 #define XILINX_DMA_REG_PARK_PTR 0x0028 107 #define XILINX_DMA_PARK_PTR_WR_REF_SHIFT 8 108 #define XILINX_DMA_PARK_PTR_WR_REF_MASK GENMASK(12, 8) 109 #define XILINX_DMA_PARK_PTR_RD_REF_SHIFT 0 110 #define XILINX_DMA_PARK_PTR_RD_REF_MASK GENMASK(4, 0) 111 #define XILINX_DMA_REG_VDMA_VERSION 0x002c 112 113 /* Register Direct Mode Registers */ 114 #define XILINX_DMA_REG_VSIZE 0x0000 115 #define XILINX_DMA_REG_HSIZE 0x0004 116 117 #define XILINX_DMA_REG_FRMDLY_STRIDE 0x0008 118 #define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT 24 119 #define XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT 0 120 121 #define XILINX_VDMA_REG_START_ADDRESS(n) (0x000c + 4 * (n)) 122 #define XILINX_VDMA_REG_START_ADDRESS_64(n) (0x000c + 8 * (n)) 123 124 #define XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP 0x00ec 125 #define XILINX_VDMA_ENABLE_VERTICAL_FLIP BIT(0) 126 127 /* HW specific definitions */ 128 #define XILINX_MCDMA_MAX_CHANS_PER_DEVICE 0x20 129 #define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x2 130 #define XILINX_CDMA_MAX_CHANS_PER_DEVICE 0x1 131 132 #define XILINX_DMA_DMAXR_ALL_IRQ_MASK \ 133 (XILINX_DMA_DMASR_FRM_CNT_IRQ | \ 134 XILINX_DMA_DMASR_DLY_CNT_IRQ | \ 135 XILINX_DMA_DMASR_ERR_IRQ) 136 137 #define XILINX_DMA_DMASR_ALL_ERR_MASK \ 138 (XILINX_DMA_DMASR_EOL_LATE_ERR | \ 139 XILINX_DMA_DMASR_SOF_LATE_ERR | \ 140 XILINX_DMA_DMASR_SG_DEC_ERR | \ 141 XILINX_DMA_DMASR_SG_SLV_ERR | \ 142 XILINX_DMA_DMASR_EOF_EARLY_ERR | \ 143 XILINX_DMA_DMASR_SOF_EARLY_ERR | \ 144 XILINX_DMA_DMASR_DMA_DEC_ERR | \ 145 XILINX_DMA_DMASR_DMA_SLAVE_ERR | \ 146 XILINX_DMA_DMASR_DMA_INT_ERR) 147 148 /* 149 * Recoverable errors are DMA Internal error, SOF Early, EOF Early 150 * and SOF Late. They are only recoverable when C_FLUSH_ON_FSYNC 151 * is enabled in the h/w system. 152 */ 153 #define XILINX_DMA_DMASR_ERR_RECOVER_MASK \ 154 (XILINX_DMA_DMASR_SOF_LATE_ERR | \ 155 XILINX_DMA_DMASR_EOF_EARLY_ERR | \ 156 XILINX_DMA_DMASR_SOF_EARLY_ERR | \ 157 XILINX_DMA_DMASR_DMA_INT_ERR) 158 159 /* Axi VDMA Flush on Fsync bits */ 160 #define XILINX_DMA_FLUSH_S2MM 3 161 #define XILINX_DMA_FLUSH_MM2S 2 162 #define XILINX_DMA_FLUSH_BOTH 1 163 164 /* Delay loop counter to prevent hardware failure */ 165 #define XILINX_DMA_LOOP_COUNT 1000000 166 167 /* AXI DMA Specific Registers/Offsets */ 168 #define XILINX_DMA_REG_SRCDSTADDR 0x18 169 #define XILINX_DMA_REG_BTT 0x28 170 171 /* AXI DMA Specific Masks/Bit fields */ 172 #define XILINX_DMA_MAX_TRANS_LEN_MIN 8 173 #define XILINX_DMA_MAX_TRANS_LEN_MAX 23 174 #define XILINX_DMA_V2_MAX_TRANS_LEN_MAX 26 175 #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16) 176 #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4) 177 #define XILINX_DMA_CR_COALESCE_SHIFT 16 178 #define XILINX_DMA_BD_SOP BIT(27) 179 #define XILINX_DMA_BD_EOP BIT(26) 180 #define XILINX_DMA_COALESCE_MAX 255 181 #define XILINX_DMA_NUM_DESCS 512 182 #define XILINX_DMA_NUM_APP_WORDS 5 183 184 /* AXI CDMA Specific Registers/Offsets */ 185 #define XILINX_CDMA_REG_SRCADDR 0x18 186 #define XILINX_CDMA_REG_DSTADDR 0x20 187 188 /* AXI CDMA Specific Masks */ 189 #define XILINX_CDMA_CR_SGMODE BIT(3) 190 191 #define xilinx_prep_dma_addr_t(addr) \ 192 ((dma_addr_t)((u64)addr##_##msb << 32 | (addr))) 193 194 /* AXI MCDMA Specific Registers/Offsets */ 195 #define XILINX_MCDMA_MM2S_CTRL_OFFSET 0x0000 196 #define XILINX_MCDMA_S2MM_CTRL_OFFSET 0x0500 197 #define XILINX_MCDMA_CHEN_OFFSET 0x0008 198 #define XILINX_MCDMA_CH_ERR_OFFSET 0x0010 199 #define XILINX_MCDMA_RXINT_SER_OFFSET 0x0020 200 #define XILINX_MCDMA_TXINT_SER_OFFSET 0x0028 201 #define XILINX_MCDMA_CHAN_CR_OFFSET(x) (0x40 + (x) * 0x40) 202 #define XILINX_MCDMA_CHAN_SR_OFFSET(x) (0x44 + (x) * 0x40) 203 #define XILINX_MCDMA_CHAN_CDESC_OFFSET(x) (0x48 + (x) * 0x40) 204 #define XILINX_MCDMA_CHAN_TDESC_OFFSET(x) (0x50 + (x) * 0x40) 205 206 /* AXI MCDMA Specific Masks/Shifts */ 207 #define XILINX_MCDMA_COALESCE_SHIFT 16 208 #define XILINX_MCDMA_COALESCE_MAX 24 209 #define XILINX_MCDMA_IRQ_ALL_MASK GENMASK(7, 5) 210 #define XILINX_MCDMA_COALESCE_MASK GENMASK(23, 16) 211 #define XILINX_MCDMA_CR_RUNSTOP_MASK BIT(0) 212 #define XILINX_MCDMA_IRQ_IOC_MASK BIT(5) 213 #define XILINX_MCDMA_IRQ_DELAY_MASK BIT(6) 214 #define XILINX_MCDMA_IRQ_ERR_MASK BIT(7) 215 #define XILINX_MCDMA_BD_EOP BIT(30) 216 #define XILINX_MCDMA_BD_SOP BIT(31) 217 218 /** 219 * struct xilinx_vdma_desc_hw - Hardware Descriptor 220 * @next_desc: Next Descriptor Pointer @0x00 221 * @pad1: Reserved @0x04 222 * @buf_addr: Buffer address @0x08 223 * @buf_addr_msb: MSB of Buffer address @0x0C 224 * @vsize: Vertical Size @0x10 225 * @hsize: Horizontal Size @0x14 226 * @stride: Number of bytes between the first 227 * pixels of each horizontal line @0x18 228 */ 229 struct xilinx_vdma_desc_hw { 230 u32 next_desc; 231 u32 pad1; 232 u32 buf_addr; 233 u32 buf_addr_msb; 234 u32 vsize; 235 u32 hsize; 236 u32 stride; 237 } __aligned(64); 238 239 /** 240 * struct xilinx_axidma_desc_hw - Hardware Descriptor for AXI DMA 241 * @next_desc: Next Descriptor Pointer @0x00 242 * @next_desc_msb: MSB of Next Descriptor Pointer @0x04 243 * @buf_addr: Buffer address @0x08 244 * @buf_addr_msb: MSB of Buffer address @0x0C 245 * @reserved1: Reserved @0x10 246 * @reserved2: Reserved @0x14 247 * @control: Control field @0x18 248 * @status: Status field @0x1C 249 * @app: APP Fields @0x20 - 0x30 250 */ 251 struct xilinx_axidma_desc_hw { 252 u32 next_desc; 253 u32 next_desc_msb; 254 u32 buf_addr; 255 u32 buf_addr_msb; 256 u32 reserved1; 257 u32 reserved2; 258 u32 control; 259 u32 status; 260 u32 app[XILINX_DMA_NUM_APP_WORDS]; 261 } __aligned(64); 262 263 /** 264 * struct xilinx_aximcdma_desc_hw - Hardware Descriptor for AXI MCDMA 265 * @next_desc: Next Descriptor Pointer @0x00 266 * @next_desc_msb: MSB of Next Descriptor Pointer @0x04 267 * @buf_addr: Buffer address @0x08 268 * @buf_addr_msb: MSB of Buffer address @0x0C 269 * @rsvd: Reserved field @0x10 270 * @control: Control Information field @0x14 271 * @status: Status field @0x18 272 * @sideband_status: Status of sideband signals @0x1C 273 * @app: APP Fields @0x20 - 0x30 274 */ 275 struct xilinx_aximcdma_desc_hw { 276 u32 next_desc; 277 u32 next_desc_msb; 278 u32 buf_addr; 279 u32 buf_addr_msb; 280 u32 rsvd; 281 u32 control; 282 u32 status; 283 u32 sideband_status; 284 u32 app[XILINX_DMA_NUM_APP_WORDS]; 285 } __aligned(64); 286 287 /** 288 * struct xilinx_cdma_desc_hw - Hardware Descriptor 289 * @next_desc: Next Descriptor Pointer @0x00 290 * @next_desc_msb: Next Descriptor Pointer MSB @0x04 291 * @src_addr: Source address @0x08 292 * @src_addr_msb: Source address MSB @0x0C 293 * @dest_addr: Destination address @0x10 294 * @dest_addr_msb: Destination address MSB @0x14 295 * @control: Control field @0x18 296 * @status: Status field @0x1C 297 */ 298 struct xilinx_cdma_desc_hw { 299 u32 next_desc; 300 u32 next_desc_msb; 301 u32 src_addr; 302 u32 src_addr_msb; 303 u32 dest_addr; 304 u32 dest_addr_msb; 305 u32 control; 306 u32 status; 307 } __aligned(64); 308 309 /** 310 * struct xilinx_vdma_tx_segment - Descriptor segment 311 * @hw: Hardware descriptor 312 * @node: Node in the descriptor segments list 313 * @phys: Physical address of segment 314 */ 315 struct xilinx_vdma_tx_segment { 316 struct xilinx_vdma_desc_hw hw; 317 struct list_head node; 318 dma_addr_t phys; 319 } __aligned(64); 320 321 /** 322 * struct xilinx_axidma_tx_segment - Descriptor segment 323 * @hw: Hardware descriptor 324 * @node: Node in the descriptor segments list 325 * @phys: Physical address of segment 326 */ 327 struct xilinx_axidma_tx_segment { 328 struct xilinx_axidma_desc_hw hw; 329 struct list_head node; 330 dma_addr_t phys; 331 } __aligned(64); 332 333 /** 334 * struct xilinx_aximcdma_tx_segment - Descriptor segment 335 * @hw: Hardware descriptor 336 * @node: Node in the descriptor segments list 337 * @phys: Physical address of segment 338 */ 339 struct xilinx_aximcdma_tx_segment { 340 struct xilinx_aximcdma_desc_hw hw; 341 struct list_head node; 342 dma_addr_t phys; 343 } __aligned(64); 344 345 /** 346 * struct xilinx_cdma_tx_segment - Descriptor segment 347 * @hw: Hardware descriptor 348 * @node: Node in the descriptor segments list 349 * @phys: Physical address of segment 350 */ 351 struct xilinx_cdma_tx_segment { 352 struct xilinx_cdma_desc_hw hw; 353 struct list_head node; 354 dma_addr_t phys; 355 } __aligned(64); 356 357 /** 358 * struct xilinx_dma_tx_descriptor - Per Transaction structure 359 * @async_tx: Async transaction descriptor 360 * @segments: TX segments list 361 * @node: Node in the channel descriptors list 362 * @cyclic: Check for cyclic transfers. 363 * @err: Whether the descriptor has an error. 364 * @residue: Residue of the completed descriptor 365 */ 366 struct xilinx_dma_tx_descriptor { 367 struct dma_async_tx_descriptor async_tx; 368 struct list_head segments; 369 struct list_head node; 370 bool cyclic; 371 bool err; 372 u32 residue; 373 }; 374 375 /** 376 * struct xilinx_dma_chan - Driver specific DMA channel structure 377 * @xdev: Driver specific device structure 378 * @ctrl_offset: Control registers offset 379 * @desc_offset: TX descriptor registers offset 380 * @lock: Descriptor operation lock 381 * @pending_list: Descriptors waiting 382 * @active_list: Descriptors ready to submit 383 * @done_list: Complete descriptors 384 * @free_seg_list: Free descriptors 385 * @common: DMA common channel 386 * @desc_pool: Descriptors pool 387 * @dev: The dma device 388 * @irq: Channel IRQ 389 * @id: Channel ID 390 * @direction: Transfer direction 391 * @num_frms: Number of frames 392 * @has_sg: Support scatter transfers 393 * @cyclic: Check for cyclic transfers. 394 * @genlock: Support genlock mode 395 * @err: Channel has errors 396 * @idle: Check for channel idle 397 * @terminating: Check for channel being synchronized by user 398 * @tasklet: Cleanup work after irq 399 * @config: Device configuration info 400 * @flush_on_fsync: Flush on Frame sync 401 * @desc_pendingcount: Descriptor pending count 402 * @ext_addr: Indicates 64 bit addressing is supported by dma channel 403 * @desc_submitcount: Descriptor h/w submitted count 404 * @seg_v: Statically allocated segments base 405 * @seg_mv: Statically allocated segments base for MCDMA 406 * @seg_p: Physical allocated segments base 407 * @cyclic_seg_v: Statically allocated segment base for cyclic transfers 408 * @cyclic_seg_p: Physical allocated segments base for cyclic dma 409 * @start_transfer: Differentiate b/w DMA IP's transfer 410 * @stop_transfer: Differentiate b/w DMA IP's quiesce 411 * @tdest: TDEST value for mcdma 412 * @has_vflip: S2MM vertical flip 413 */ 414 struct xilinx_dma_chan { 415 struct xilinx_dma_device *xdev; 416 u32 ctrl_offset; 417 u32 desc_offset; 418 spinlock_t lock; 419 struct list_head pending_list; 420 struct list_head active_list; 421 struct list_head done_list; 422 struct list_head free_seg_list; 423 struct dma_chan common; 424 struct dma_pool *desc_pool; 425 struct device *dev; 426 int irq; 427 int id; 428 enum dma_transfer_direction direction; 429 int num_frms; 430 bool has_sg; 431 bool cyclic; 432 bool genlock; 433 bool err; 434 bool idle; 435 bool terminating; 436 struct tasklet_struct tasklet; 437 struct xilinx_vdma_config config; 438 bool flush_on_fsync; 439 u32 desc_pendingcount; 440 bool ext_addr; 441 u32 desc_submitcount; 442 struct xilinx_axidma_tx_segment *seg_v; 443 struct xilinx_aximcdma_tx_segment *seg_mv; 444 dma_addr_t seg_p; 445 struct xilinx_axidma_tx_segment *cyclic_seg_v; 446 dma_addr_t cyclic_seg_p; 447 void (*start_transfer)(struct xilinx_dma_chan *chan); 448 int (*stop_transfer)(struct xilinx_dma_chan *chan); 449 u16 tdest; 450 bool has_vflip; 451 }; 452 453 /** 454 * enum xdma_ip_type - DMA IP type. 455 * 456 * @XDMA_TYPE_AXIDMA: Axi dma ip. 457 * @XDMA_TYPE_CDMA: Axi cdma ip. 458 * @XDMA_TYPE_VDMA: Axi vdma ip. 459 * @XDMA_TYPE_AXIMCDMA: Axi MCDMA ip. 460 * 461 */ 462 enum xdma_ip_type { 463 XDMA_TYPE_AXIDMA = 0, 464 XDMA_TYPE_CDMA, 465 XDMA_TYPE_VDMA, 466 XDMA_TYPE_AXIMCDMA 467 }; 468 469 struct xilinx_dma_config { 470 enum xdma_ip_type dmatype; 471 int (*clk_init)(struct platform_device *pdev, struct clk **axi_clk, 472 struct clk **tx_clk, struct clk **txs_clk, 473 struct clk **rx_clk, struct clk **rxs_clk); 474 irqreturn_t (*irq_handler)(int irq, void *data); 475 const int max_channels; 476 }; 477 478 /** 479 * struct xilinx_dma_device - DMA device structure 480 * @regs: I/O mapped base address 481 * @dev: Device Structure 482 * @common: DMA device structure 483 * @chan: Driver specific DMA channel 484 * @flush_on_fsync: Flush on frame sync 485 * @ext_addr: Indicates 64 bit addressing is supported by dma device 486 * @pdev: Platform device structure pointer 487 * @dma_config: DMA config structure 488 * @axi_clk: DMA Axi4-lite interace clock 489 * @tx_clk: DMA mm2s clock 490 * @txs_clk: DMA mm2s stream clock 491 * @rx_clk: DMA s2mm clock 492 * @rxs_clk: DMA s2mm stream clock 493 * @s2mm_chan_id: DMA s2mm channel identifier 494 * @mm2s_chan_id: DMA mm2s channel identifier 495 * @max_buffer_len: Max buffer length 496 * @has_axistream_connected: AXI DMA connected to AXI Stream IP 497 */ 498 struct xilinx_dma_device { 499 void __iomem *regs; 500 struct device *dev; 501 struct dma_device common; 502 struct xilinx_dma_chan *chan[XILINX_MCDMA_MAX_CHANS_PER_DEVICE]; 503 u32 flush_on_fsync; 504 bool ext_addr; 505 struct platform_device *pdev; 506 const struct xilinx_dma_config *dma_config; 507 struct clk *axi_clk; 508 struct clk *tx_clk; 509 struct clk *txs_clk; 510 struct clk *rx_clk; 511 struct clk *rxs_clk; 512 u32 s2mm_chan_id; 513 u32 mm2s_chan_id; 514 u32 max_buffer_len; 515 bool has_axistream_connected; 516 }; 517 518 /* Macros */ 519 #define to_xilinx_chan(chan) \ 520 container_of(chan, struct xilinx_dma_chan, common) 521 #define to_dma_tx_descriptor(tx) \ 522 container_of(tx, struct xilinx_dma_tx_descriptor, async_tx) 523 #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \ 524 readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \ 525 val, cond, delay_us, timeout_us) 526 527 /* IO accessors */ 528 static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg) 529 { 530 return ioread32(chan->xdev->regs + reg); 531 } 532 533 static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value) 534 { 535 iowrite32(value, chan->xdev->regs + reg); 536 } 537 538 static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg, 539 u32 value) 540 { 541 dma_write(chan, chan->desc_offset + reg, value); 542 } 543 544 static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg) 545 { 546 return dma_read(chan, chan->ctrl_offset + reg); 547 } 548 549 static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg, 550 u32 value) 551 { 552 dma_write(chan, chan->ctrl_offset + reg, value); 553 } 554 555 static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg, 556 u32 clr) 557 { 558 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr); 559 } 560 561 static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg, 562 u32 set) 563 { 564 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set); 565 } 566 567 /** 568 * vdma_desc_write_64 - 64-bit descriptor write 569 * @chan: Driver specific VDMA channel 570 * @reg: Register to write 571 * @value_lsb: lower address of the descriptor. 572 * @value_msb: upper address of the descriptor. 573 * 574 * Since vdma driver is trying to write to a register offset which is not a 575 * multiple of 64 bits(ex : 0x5c), we are writing as two separate 32 bits 576 * instead of a single 64 bit register write. 577 */ 578 static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg, 579 u32 value_lsb, u32 value_msb) 580 { 581 /* Write the lsb 32 bits*/ 582 writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg); 583 584 /* Write the msb 32 bits */ 585 writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4); 586 } 587 588 static inline void dma_writeq(struct xilinx_dma_chan *chan, u32 reg, u64 value) 589 { 590 lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg); 591 } 592 593 static inline void xilinx_write(struct xilinx_dma_chan *chan, u32 reg, 594 dma_addr_t addr) 595 { 596 if (chan->ext_addr) 597 dma_writeq(chan, reg, addr); 598 else 599 dma_ctrl_write(chan, reg, addr); 600 } 601 602 static inline void xilinx_axidma_buf(struct xilinx_dma_chan *chan, 603 struct xilinx_axidma_desc_hw *hw, 604 dma_addr_t buf_addr, size_t sg_used, 605 size_t period_len) 606 { 607 if (chan->ext_addr) { 608 hw->buf_addr = lower_32_bits(buf_addr + sg_used + period_len); 609 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used + 610 period_len); 611 } else { 612 hw->buf_addr = buf_addr + sg_used + period_len; 613 } 614 } 615 616 static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan, 617 struct xilinx_aximcdma_desc_hw *hw, 618 dma_addr_t buf_addr, size_t sg_used) 619 { 620 if (chan->ext_addr) { 621 hw->buf_addr = lower_32_bits(buf_addr + sg_used); 622 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used); 623 } else { 624 hw->buf_addr = buf_addr + sg_used; 625 } 626 } 627 628 /** 629 * xilinx_dma_get_metadata_ptr- Populate metadata pointer and payload length 630 * @tx: async transaction descriptor 631 * @payload_len: metadata payload length 632 * @max_len: metadata max length 633 * Return: The app field pointer. 634 */ 635 static void *xilinx_dma_get_metadata_ptr(struct dma_async_tx_descriptor *tx, 636 size_t *payload_len, size_t *max_len) 637 { 638 struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx); 639 struct xilinx_axidma_tx_segment *seg; 640 641 *max_len = *payload_len = sizeof(u32) * XILINX_DMA_NUM_APP_WORDS; 642 seg = list_first_entry(&desc->segments, 643 struct xilinx_axidma_tx_segment, node); 644 return seg->hw.app; 645 } 646 647 static struct dma_descriptor_metadata_ops xilinx_dma_metadata_ops = { 648 .get_ptr = xilinx_dma_get_metadata_ptr, 649 }; 650 651 /* ----------------------------------------------------------------------------- 652 * Descriptors and segments alloc and free 653 */ 654 655 /** 656 * xilinx_vdma_alloc_tx_segment - Allocate transaction segment 657 * @chan: Driver specific DMA channel 658 * 659 * Return: The allocated segment on success and NULL on failure. 660 */ 661 static struct xilinx_vdma_tx_segment * 662 xilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan) 663 { 664 struct xilinx_vdma_tx_segment *segment; 665 dma_addr_t phys; 666 667 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys); 668 if (!segment) 669 return NULL; 670 671 segment->phys = phys; 672 673 return segment; 674 } 675 676 /** 677 * xilinx_cdma_alloc_tx_segment - Allocate transaction segment 678 * @chan: Driver specific DMA channel 679 * 680 * Return: The allocated segment on success and NULL on failure. 681 */ 682 static struct xilinx_cdma_tx_segment * 683 xilinx_cdma_alloc_tx_segment(struct xilinx_dma_chan *chan) 684 { 685 struct xilinx_cdma_tx_segment *segment; 686 dma_addr_t phys; 687 688 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys); 689 if (!segment) 690 return NULL; 691 692 segment->phys = phys; 693 694 return segment; 695 } 696 697 /** 698 * xilinx_axidma_alloc_tx_segment - Allocate transaction segment 699 * @chan: Driver specific DMA channel 700 * 701 * Return: The allocated segment on success and NULL on failure. 702 */ 703 static struct xilinx_axidma_tx_segment * 704 xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan) 705 { 706 struct xilinx_axidma_tx_segment *segment = NULL; 707 unsigned long flags; 708 709 spin_lock_irqsave(&chan->lock, flags); 710 if (!list_empty(&chan->free_seg_list)) { 711 segment = list_first_entry(&chan->free_seg_list, 712 struct xilinx_axidma_tx_segment, 713 node); 714 list_del(&segment->node); 715 } 716 spin_unlock_irqrestore(&chan->lock, flags); 717 718 if (!segment) 719 dev_dbg(chan->dev, "Could not find free tx segment\n"); 720 721 return segment; 722 } 723 724 /** 725 * xilinx_aximcdma_alloc_tx_segment - Allocate transaction segment 726 * @chan: Driver specific DMA channel 727 * 728 * Return: The allocated segment on success and NULL on failure. 729 */ 730 static struct xilinx_aximcdma_tx_segment * 731 xilinx_aximcdma_alloc_tx_segment(struct xilinx_dma_chan *chan) 732 { 733 struct xilinx_aximcdma_tx_segment *segment = NULL; 734 unsigned long flags; 735 736 spin_lock_irqsave(&chan->lock, flags); 737 if (!list_empty(&chan->free_seg_list)) { 738 segment = list_first_entry(&chan->free_seg_list, 739 struct xilinx_aximcdma_tx_segment, 740 node); 741 list_del(&segment->node); 742 } 743 spin_unlock_irqrestore(&chan->lock, flags); 744 745 return segment; 746 } 747 748 static void xilinx_dma_clean_hw_desc(struct xilinx_axidma_desc_hw *hw) 749 { 750 u32 next_desc = hw->next_desc; 751 u32 next_desc_msb = hw->next_desc_msb; 752 753 memset(hw, 0, sizeof(struct xilinx_axidma_desc_hw)); 754 755 hw->next_desc = next_desc; 756 hw->next_desc_msb = next_desc_msb; 757 } 758 759 static void xilinx_mcdma_clean_hw_desc(struct xilinx_aximcdma_desc_hw *hw) 760 { 761 u32 next_desc = hw->next_desc; 762 u32 next_desc_msb = hw->next_desc_msb; 763 764 memset(hw, 0, sizeof(struct xilinx_aximcdma_desc_hw)); 765 766 hw->next_desc = next_desc; 767 hw->next_desc_msb = next_desc_msb; 768 } 769 770 /** 771 * xilinx_dma_free_tx_segment - Free transaction segment 772 * @chan: Driver specific DMA channel 773 * @segment: DMA transaction segment 774 */ 775 static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan, 776 struct xilinx_axidma_tx_segment *segment) 777 { 778 xilinx_dma_clean_hw_desc(&segment->hw); 779 780 list_add_tail(&segment->node, &chan->free_seg_list); 781 } 782 783 /** 784 * xilinx_mcdma_free_tx_segment - Free transaction segment 785 * @chan: Driver specific DMA channel 786 * @segment: DMA transaction segment 787 */ 788 static void xilinx_mcdma_free_tx_segment(struct xilinx_dma_chan *chan, 789 struct xilinx_aximcdma_tx_segment * 790 segment) 791 { 792 xilinx_mcdma_clean_hw_desc(&segment->hw); 793 794 list_add_tail(&segment->node, &chan->free_seg_list); 795 } 796 797 /** 798 * xilinx_cdma_free_tx_segment - Free transaction segment 799 * @chan: Driver specific DMA channel 800 * @segment: DMA transaction segment 801 */ 802 static void xilinx_cdma_free_tx_segment(struct xilinx_dma_chan *chan, 803 struct xilinx_cdma_tx_segment *segment) 804 { 805 dma_pool_free(chan->desc_pool, segment, segment->phys); 806 } 807 808 /** 809 * xilinx_vdma_free_tx_segment - Free transaction segment 810 * @chan: Driver specific DMA channel 811 * @segment: DMA transaction segment 812 */ 813 static void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan, 814 struct xilinx_vdma_tx_segment *segment) 815 { 816 dma_pool_free(chan->desc_pool, segment, segment->phys); 817 } 818 819 /** 820 * xilinx_dma_alloc_tx_descriptor - Allocate transaction descriptor 821 * @chan: Driver specific DMA channel 822 * 823 * Return: The allocated descriptor on success and NULL on failure. 824 */ 825 static struct xilinx_dma_tx_descriptor * 826 xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan) 827 { 828 struct xilinx_dma_tx_descriptor *desc; 829 830 desc = kzalloc(sizeof(*desc), GFP_NOWAIT); 831 if (!desc) 832 return NULL; 833 834 INIT_LIST_HEAD(&desc->segments); 835 836 return desc; 837 } 838 839 /** 840 * xilinx_dma_free_tx_descriptor - Free transaction descriptor 841 * @chan: Driver specific DMA channel 842 * @desc: DMA transaction descriptor 843 */ 844 static void 845 xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan, 846 struct xilinx_dma_tx_descriptor *desc) 847 { 848 struct xilinx_vdma_tx_segment *segment, *next; 849 struct xilinx_cdma_tx_segment *cdma_segment, *cdma_next; 850 struct xilinx_axidma_tx_segment *axidma_segment, *axidma_next; 851 struct xilinx_aximcdma_tx_segment *aximcdma_segment, *aximcdma_next; 852 853 if (!desc) 854 return; 855 856 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 857 list_for_each_entry_safe(segment, next, &desc->segments, node) { 858 list_del(&segment->node); 859 xilinx_vdma_free_tx_segment(chan, segment); 860 } 861 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 862 list_for_each_entry_safe(cdma_segment, cdma_next, 863 &desc->segments, node) { 864 list_del(&cdma_segment->node); 865 xilinx_cdma_free_tx_segment(chan, cdma_segment); 866 } 867 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 868 list_for_each_entry_safe(axidma_segment, axidma_next, 869 &desc->segments, node) { 870 list_del(&axidma_segment->node); 871 xilinx_dma_free_tx_segment(chan, axidma_segment); 872 } 873 } else { 874 list_for_each_entry_safe(aximcdma_segment, aximcdma_next, 875 &desc->segments, node) { 876 list_del(&aximcdma_segment->node); 877 xilinx_mcdma_free_tx_segment(chan, aximcdma_segment); 878 } 879 } 880 881 kfree(desc); 882 } 883 884 /* Required functions */ 885 886 /** 887 * xilinx_dma_free_desc_list - Free descriptors list 888 * @chan: Driver specific DMA channel 889 * @list: List to parse and delete the descriptor 890 */ 891 static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan, 892 struct list_head *list) 893 { 894 struct xilinx_dma_tx_descriptor *desc, *next; 895 896 list_for_each_entry_safe(desc, next, list, node) { 897 list_del(&desc->node); 898 xilinx_dma_free_tx_descriptor(chan, desc); 899 } 900 } 901 902 /** 903 * xilinx_dma_free_descriptors - Free channel descriptors 904 * @chan: Driver specific DMA channel 905 */ 906 static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan) 907 { 908 unsigned long flags; 909 910 spin_lock_irqsave(&chan->lock, flags); 911 912 xilinx_dma_free_desc_list(chan, &chan->pending_list); 913 xilinx_dma_free_desc_list(chan, &chan->done_list); 914 xilinx_dma_free_desc_list(chan, &chan->active_list); 915 916 spin_unlock_irqrestore(&chan->lock, flags); 917 } 918 919 /** 920 * xilinx_dma_free_chan_resources - Free channel resources 921 * @dchan: DMA channel 922 */ 923 static void xilinx_dma_free_chan_resources(struct dma_chan *dchan) 924 { 925 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 926 unsigned long flags; 927 928 dev_dbg(chan->dev, "Free all channel resources.\n"); 929 930 xilinx_dma_free_descriptors(chan); 931 932 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 933 spin_lock_irqsave(&chan->lock, flags); 934 INIT_LIST_HEAD(&chan->free_seg_list); 935 spin_unlock_irqrestore(&chan->lock, flags); 936 937 /* Free memory that is allocated for BD */ 938 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) * 939 XILINX_DMA_NUM_DESCS, chan->seg_v, 940 chan->seg_p); 941 942 /* Free Memory that is allocated for cyclic DMA Mode */ 943 dma_free_coherent(chan->dev, sizeof(*chan->cyclic_seg_v), 944 chan->cyclic_seg_v, chan->cyclic_seg_p); 945 } 946 947 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 948 spin_lock_irqsave(&chan->lock, flags); 949 INIT_LIST_HEAD(&chan->free_seg_list); 950 spin_unlock_irqrestore(&chan->lock, flags); 951 952 /* Free memory that is allocated for BD */ 953 dma_free_coherent(chan->dev, sizeof(*chan->seg_mv) * 954 XILINX_DMA_NUM_DESCS, chan->seg_mv, 955 chan->seg_p); 956 } 957 958 if (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA && 959 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA) { 960 dma_pool_destroy(chan->desc_pool); 961 chan->desc_pool = NULL; 962 } 963 964 } 965 966 /** 967 * xilinx_dma_get_residue - Compute residue for a given descriptor 968 * @chan: Driver specific dma channel 969 * @desc: dma transaction descriptor 970 * 971 * Return: The number of residue bytes for the descriptor. 972 */ 973 static u32 xilinx_dma_get_residue(struct xilinx_dma_chan *chan, 974 struct xilinx_dma_tx_descriptor *desc) 975 { 976 struct xilinx_cdma_tx_segment *cdma_seg; 977 struct xilinx_axidma_tx_segment *axidma_seg; 978 struct xilinx_aximcdma_tx_segment *aximcdma_seg; 979 struct xilinx_cdma_desc_hw *cdma_hw; 980 struct xilinx_axidma_desc_hw *axidma_hw; 981 struct xilinx_aximcdma_desc_hw *aximcdma_hw; 982 struct list_head *entry; 983 u32 residue = 0; 984 985 list_for_each(entry, &desc->segments) { 986 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 987 cdma_seg = list_entry(entry, 988 struct xilinx_cdma_tx_segment, 989 node); 990 cdma_hw = &cdma_seg->hw; 991 residue += (cdma_hw->control - cdma_hw->status) & 992 chan->xdev->max_buffer_len; 993 } else if (chan->xdev->dma_config->dmatype == 994 XDMA_TYPE_AXIDMA) { 995 axidma_seg = list_entry(entry, 996 struct xilinx_axidma_tx_segment, 997 node); 998 axidma_hw = &axidma_seg->hw; 999 residue += (axidma_hw->control - axidma_hw->status) & 1000 chan->xdev->max_buffer_len; 1001 } else { 1002 aximcdma_seg = 1003 list_entry(entry, 1004 struct xilinx_aximcdma_tx_segment, 1005 node); 1006 aximcdma_hw = &aximcdma_seg->hw; 1007 residue += 1008 (aximcdma_hw->control - aximcdma_hw->status) & 1009 chan->xdev->max_buffer_len; 1010 } 1011 } 1012 1013 return residue; 1014 } 1015 1016 /** 1017 * xilinx_dma_chan_handle_cyclic - Cyclic dma callback 1018 * @chan: Driver specific dma channel 1019 * @desc: dma transaction descriptor 1020 * @flags: flags for spin lock 1021 */ 1022 static void xilinx_dma_chan_handle_cyclic(struct xilinx_dma_chan *chan, 1023 struct xilinx_dma_tx_descriptor *desc, 1024 unsigned long *flags) 1025 { 1026 struct dmaengine_desc_callback cb; 1027 1028 dmaengine_desc_get_callback(&desc->async_tx, &cb); 1029 if (dmaengine_desc_callback_valid(&cb)) { 1030 spin_unlock_irqrestore(&chan->lock, *flags); 1031 dmaengine_desc_callback_invoke(&cb, NULL); 1032 spin_lock_irqsave(&chan->lock, *flags); 1033 } 1034 } 1035 1036 /** 1037 * xilinx_dma_chan_desc_cleanup - Clean channel descriptors 1038 * @chan: Driver specific DMA channel 1039 */ 1040 static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan) 1041 { 1042 struct xilinx_dma_tx_descriptor *desc, *next; 1043 unsigned long flags; 1044 1045 spin_lock_irqsave(&chan->lock, flags); 1046 1047 list_for_each_entry_safe(desc, next, &chan->done_list, node) { 1048 struct dmaengine_result result; 1049 1050 if (desc->cyclic) { 1051 xilinx_dma_chan_handle_cyclic(chan, desc, &flags); 1052 break; 1053 } 1054 1055 /* Remove from the list of running transactions */ 1056 list_del(&desc->node); 1057 1058 if (unlikely(desc->err)) { 1059 if (chan->direction == DMA_DEV_TO_MEM) 1060 result.result = DMA_TRANS_READ_FAILED; 1061 else 1062 result.result = DMA_TRANS_WRITE_FAILED; 1063 } else { 1064 result.result = DMA_TRANS_NOERROR; 1065 } 1066 1067 result.residue = desc->residue; 1068 1069 /* Run the link descriptor callback function */ 1070 spin_unlock_irqrestore(&chan->lock, flags); 1071 dmaengine_desc_get_callback_invoke(&desc->async_tx, &result); 1072 spin_lock_irqsave(&chan->lock, flags); 1073 1074 /* Run any dependencies, then free the descriptor */ 1075 dma_run_dependencies(&desc->async_tx); 1076 xilinx_dma_free_tx_descriptor(chan, desc); 1077 1078 /* 1079 * While we ran a callback the user called a terminate function, 1080 * which takes care of cleaning up any remaining descriptors 1081 */ 1082 if (chan->terminating) 1083 break; 1084 } 1085 1086 spin_unlock_irqrestore(&chan->lock, flags); 1087 } 1088 1089 /** 1090 * xilinx_dma_do_tasklet - Schedule completion tasklet 1091 * @t: Pointer to the Xilinx DMA channel structure 1092 */ 1093 static void xilinx_dma_do_tasklet(struct tasklet_struct *t) 1094 { 1095 struct xilinx_dma_chan *chan = from_tasklet(chan, t, tasklet); 1096 1097 xilinx_dma_chan_desc_cleanup(chan); 1098 } 1099 1100 /** 1101 * xilinx_dma_alloc_chan_resources - Allocate channel resources 1102 * @dchan: DMA channel 1103 * 1104 * Return: '0' on success and failure value on error 1105 */ 1106 static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan) 1107 { 1108 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 1109 int i; 1110 1111 /* Has this channel already been allocated? */ 1112 if (chan->desc_pool) 1113 return 0; 1114 1115 /* 1116 * We need the descriptor to be aligned to 64bytes 1117 * for meeting Xilinx VDMA specification requirement. 1118 */ 1119 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 1120 /* Allocate the buffer descriptors. */ 1121 chan->seg_v = dma_alloc_coherent(chan->dev, 1122 sizeof(*chan->seg_v) * XILINX_DMA_NUM_DESCS, 1123 &chan->seg_p, GFP_KERNEL); 1124 if (!chan->seg_v) { 1125 dev_err(chan->dev, 1126 "unable to allocate channel %d descriptors\n", 1127 chan->id); 1128 return -ENOMEM; 1129 } 1130 /* 1131 * For cyclic DMA mode we need to program the tail Descriptor 1132 * register with a value which is not a part of the BD chain 1133 * so allocating a desc segment during channel allocation for 1134 * programming tail descriptor. 1135 */ 1136 chan->cyclic_seg_v = dma_alloc_coherent(chan->dev, 1137 sizeof(*chan->cyclic_seg_v), 1138 &chan->cyclic_seg_p, 1139 GFP_KERNEL); 1140 if (!chan->cyclic_seg_v) { 1141 dev_err(chan->dev, 1142 "unable to allocate desc segment for cyclic DMA\n"); 1143 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) * 1144 XILINX_DMA_NUM_DESCS, chan->seg_v, 1145 chan->seg_p); 1146 return -ENOMEM; 1147 } 1148 chan->cyclic_seg_v->phys = chan->cyclic_seg_p; 1149 1150 for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) { 1151 chan->seg_v[i].hw.next_desc = 1152 lower_32_bits(chan->seg_p + sizeof(*chan->seg_v) * 1153 ((i + 1) % XILINX_DMA_NUM_DESCS)); 1154 chan->seg_v[i].hw.next_desc_msb = 1155 upper_32_bits(chan->seg_p + sizeof(*chan->seg_v) * 1156 ((i + 1) % XILINX_DMA_NUM_DESCS)); 1157 chan->seg_v[i].phys = chan->seg_p + 1158 sizeof(*chan->seg_v) * i; 1159 list_add_tail(&chan->seg_v[i].node, 1160 &chan->free_seg_list); 1161 } 1162 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 1163 /* Allocate the buffer descriptors. */ 1164 chan->seg_mv = dma_alloc_coherent(chan->dev, 1165 sizeof(*chan->seg_mv) * 1166 XILINX_DMA_NUM_DESCS, 1167 &chan->seg_p, GFP_KERNEL); 1168 if (!chan->seg_mv) { 1169 dev_err(chan->dev, 1170 "unable to allocate channel %d descriptors\n", 1171 chan->id); 1172 return -ENOMEM; 1173 } 1174 for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) { 1175 chan->seg_mv[i].hw.next_desc = 1176 lower_32_bits(chan->seg_p + sizeof(*chan->seg_mv) * 1177 ((i + 1) % XILINX_DMA_NUM_DESCS)); 1178 chan->seg_mv[i].hw.next_desc_msb = 1179 upper_32_bits(chan->seg_p + sizeof(*chan->seg_mv) * 1180 ((i + 1) % XILINX_DMA_NUM_DESCS)); 1181 chan->seg_mv[i].phys = chan->seg_p + 1182 sizeof(*chan->seg_mv) * i; 1183 list_add_tail(&chan->seg_mv[i].node, 1184 &chan->free_seg_list); 1185 } 1186 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 1187 chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool", 1188 chan->dev, 1189 sizeof(struct xilinx_cdma_tx_segment), 1190 __alignof__(struct xilinx_cdma_tx_segment), 1191 0); 1192 } else { 1193 chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool", 1194 chan->dev, 1195 sizeof(struct xilinx_vdma_tx_segment), 1196 __alignof__(struct xilinx_vdma_tx_segment), 1197 0); 1198 } 1199 1200 if (!chan->desc_pool && 1201 ((chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) && 1202 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA)) { 1203 dev_err(chan->dev, 1204 "unable to allocate channel %d descriptor pool\n", 1205 chan->id); 1206 return -ENOMEM; 1207 } 1208 1209 dma_cookie_init(dchan); 1210 1211 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 1212 /* For AXI DMA resetting once channel will reset the 1213 * other channel as well so enable the interrupts here. 1214 */ 1215 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, 1216 XILINX_DMA_DMAXR_ALL_IRQ_MASK); 1217 } 1218 1219 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) 1220 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, 1221 XILINX_CDMA_CR_SGMODE); 1222 1223 return 0; 1224 } 1225 1226 /** 1227 * xilinx_dma_calc_copysize - Calculate the amount of data to copy 1228 * @chan: Driver specific DMA channel 1229 * @size: Total data that needs to be copied 1230 * @done: Amount of data that has been already copied 1231 * 1232 * Return: Amount of data that has to be copied 1233 */ 1234 static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan, 1235 int size, int done) 1236 { 1237 size_t copy; 1238 1239 copy = min_t(size_t, size - done, 1240 chan->xdev->max_buffer_len); 1241 1242 if ((copy + done < size) && 1243 chan->xdev->common.copy_align) { 1244 /* 1245 * If this is not the last descriptor, make sure 1246 * the next one will be properly aligned 1247 */ 1248 copy = rounddown(copy, 1249 (1 << chan->xdev->common.copy_align)); 1250 } 1251 return copy; 1252 } 1253 1254 /** 1255 * xilinx_dma_tx_status - Get DMA transaction status 1256 * @dchan: DMA channel 1257 * @cookie: Transaction identifier 1258 * @txstate: Transaction state 1259 * 1260 * Return: DMA transaction status 1261 */ 1262 static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan, 1263 dma_cookie_t cookie, 1264 struct dma_tx_state *txstate) 1265 { 1266 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 1267 struct xilinx_dma_tx_descriptor *desc; 1268 enum dma_status ret; 1269 unsigned long flags; 1270 u32 residue = 0; 1271 1272 ret = dma_cookie_status(dchan, cookie, txstate); 1273 if (ret == DMA_COMPLETE || !txstate) 1274 return ret; 1275 1276 spin_lock_irqsave(&chan->lock, flags); 1277 if (!list_empty(&chan->active_list)) { 1278 desc = list_last_entry(&chan->active_list, 1279 struct xilinx_dma_tx_descriptor, node); 1280 /* 1281 * VDMA and simple mode do not support residue reporting, so the 1282 * residue field will always be 0. 1283 */ 1284 if (chan->has_sg && chan->xdev->dma_config->dmatype != XDMA_TYPE_VDMA) 1285 residue = xilinx_dma_get_residue(chan, desc); 1286 } 1287 spin_unlock_irqrestore(&chan->lock, flags); 1288 1289 dma_set_residue(txstate, residue); 1290 1291 return ret; 1292 } 1293 1294 /** 1295 * xilinx_dma_stop_transfer - Halt DMA channel 1296 * @chan: Driver specific DMA channel 1297 * 1298 * Return: '0' on success and failure value on error 1299 */ 1300 static int xilinx_dma_stop_transfer(struct xilinx_dma_chan *chan) 1301 { 1302 u32 val; 1303 1304 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP); 1305 1306 /* Wait for the hardware to halt */ 1307 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, 1308 val & XILINX_DMA_DMASR_HALTED, 0, 1309 XILINX_DMA_LOOP_COUNT); 1310 } 1311 1312 /** 1313 * xilinx_cdma_stop_transfer - Wait for the current transfer to complete 1314 * @chan: Driver specific DMA channel 1315 * 1316 * Return: '0' on success and failure value on error 1317 */ 1318 static int xilinx_cdma_stop_transfer(struct xilinx_dma_chan *chan) 1319 { 1320 u32 val; 1321 1322 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, 1323 val & XILINX_DMA_DMASR_IDLE, 0, 1324 XILINX_DMA_LOOP_COUNT); 1325 } 1326 1327 /** 1328 * xilinx_dma_start - Start DMA channel 1329 * @chan: Driver specific DMA channel 1330 */ 1331 static void xilinx_dma_start(struct xilinx_dma_chan *chan) 1332 { 1333 int err; 1334 u32 val; 1335 1336 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP); 1337 1338 /* Wait for the hardware to start */ 1339 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, 1340 !(val & XILINX_DMA_DMASR_HALTED), 0, 1341 XILINX_DMA_LOOP_COUNT); 1342 1343 if (err) { 1344 dev_err(chan->dev, "Cannot start channel %p: %x\n", 1345 chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); 1346 1347 chan->err = true; 1348 } 1349 } 1350 1351 /** 1352 * xilinx_vdma_start_transfer - Starts VDMA transfer 1353 * @chan: Driver specific channel struct pointer 1354 */ 1355 static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) 1356 { 1357 struct xilinx_vdma_config *config = &chan->config; 1358 struct xilinx_dma_tx_descriptor *desc; 1359 u32 reg, j; 1360 struct xilinx_vdma_tx_segment *segment, *last = NULL; 1361 int i = 0; 1362 1363 /* This function was invoked with lock held */ 1364 if (chan->err) 1365 return; 1366 1367 if (!chan->idle) 1368 return; 1369 1370 if (list_empty(&chan->pending_list)) 1371 return; 1372 1373 desc = list_first_entry(&chan->pending_list, 1374 struct xilinx_dma_tx_descriptor, node); 1375 1376 /* Configure the hardware using info in the config structure */ 1377 if (chan->has_vflip) { 1378 reg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP); 1379 reg &= ~XILINX_VDMA_ENABLE_VERTICAL_FLIP; 1380 reg |= config->vflip_en; 1381 dma_write(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP, 1382 reg); 1383 } 1384 1385 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 1386 1387 if (config->frm_cnt_en) 1388 reg |= XILINX_DMA_DMACR_FRAMECNT_EN; 1389 else 1390 reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN; 1391 1392 /* If not parking, enable circular mode */ 1393 if (config->park) 1394 reg &= ~XILINX_DMA_DMACR_CIRC_EN; 1395 else 1396 reg |= XILINX_DMA_DMACR_CIRC_EN; 1397 1398 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); 1399 1400 j = chan->desc_submitcount; 1401 reg = dma_read(chan, XILINX_DMA_REG_PARK_PTR); 1402 if (chan->direction == DMA_MEM_TO_DEV) { 1403 reg &= ~XILINX_DMA_PARK_PTR_RD_REF_MASK; 1404 reg |= j << XILINX_DMA_PARK_PTR_RD_REF_SHIFT; 1405 } else { 1406 reg &= ~XILINX_DMA_PARK_PTR_WR_REF_MASK; 1407 reg |= j << XILINX_DMA_PARK_PTR_WR_REF_SHIFT; 1408 } 1409 dma_write(chan, XILINX_DMA_REG_PARK_PTR, reg); 1410 1411 /* Start the hardware */ 1412 xilinx_dma_start(chan); 1413 1414 if (chan->err) 1415 return; 1416 1417 /* Start the transfer */ 1418 if (chan->desc_submitcount < chan->num_frms) 1419 i = chan->desc_submitcount; 1420 1421 list_for_each_entry(segment, &desc->segments, node) { 1422 if (chan->ext_addr) 1423 vdma_desc_write_64(chan, 1424 XILINX_VDMA_REG_START_ADDRESS_64(i++), 1425 segment->hw.buf_addr, 1426 segment->hw.buf_addr_msb); 1427 else 1428 vdma_desc_write(chan, 1429 XILINX_VDMA_REG_START_ADDRESS(i++), 1430 segment->hw.buf_addr); 1431 1432 last = segment; 1433 } 1434 1435 if (!last) 1436 return; 1437 1438 /* HW expects these parameters to be same for one transaction */ 1439 vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); 1440 vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE, 1441 last->hw.stride); 1442 vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); 1443 1444 chan->desc_submitcount++; 1445 chan->desc_pendingcount--; 1446 list_move_tail(&desc->node, &chan->active_list); 1447 if (chan->desc_submitcount == chan->num_frms) 1448 chan->desc_submitcount = 0; 1449 1450 chan->idle = false; 1451 } 1452 1453 /** 1454 * xilinx_cdma_start_transfer - Starts cdma transfer 1455 * @chan: Driver specific channel struct pointer 1456 */ 1457 static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan) 1458 { 1459 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; 1460 struct xilinx_cdma_tx_segment *tail_segment; 1461 u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR); 1462 1463 if (chan->err) 1464 return; 1465 1466 if (!chan->idle) 1467 return; 1468 1469 if (list_empty(&chan->pending_list)) 1470 return; 1471 1472 head_desc = list_first_entry(&chan->pending_list, 1473 struct xilinx_dma_tx_descriptor, node); 1474 tail_desc = list_last_entry(&chan->pending_list, 1475 struct xilinx_dma_tx_descriptor, node); 1476 tail_segment = list_last_entry(&tail_desc->segments, 1477 struct xilinx_cdma_tx_segment, node); 1478 1479 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { 1480 ctrl_reg &= ~XILINX_DMA_CR_COALESCE_MAX; 1481 ctrl_reg |= chan->desc_pendingcount << 1482 XILINX_DMA_CR_COALESCE_SHIFT; 1483 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg); 1484 } 1485 1486 if (chan->has_sg) { 1487 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, 1488 XILINX_CDMA_CR_SGMODE); 1489 1490 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, 1491 XILINX_CDMA_CR_SGMODE); 1492 1493 xilinx_write(chan, XILINX_DMA_REG_CURDESC, 1494 head_desc->async_tx.phys); 1495 1496 /* Update tail ptr register which will start the transfer */ 1497 xilinx_write(chan, XILINX_DMA_REG_TAILDESC, 1498 tail_segment->phys); 1499 } else { 1500 /* In simple mode */ 1501 struct xilinx_cdma_tx_segment *segment; 1502 struct xilinx_cdma_desc_hw *hw; 1503 1504 segment = list_first_entry(&head_desc->segments, 1505 struct xilinx_cdma_tx_segment, 1506 node); 1507 1508 hw = &segment->hw; 1509 1510 xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, 1511 xilinx_prep_dma_addr_t(hw->src_addr)); 1512 xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, 1513 xilinx_prep_dma_addr_t(hw->dest_addr)); 1514 1515 /* Start the transfer */ 1516 dma_ctrl_write(chan, XILINX_DMA_REG_BTT, 1517 hw->control & chan->xdev->max_buffer_len); 1518 } 1519 1520 list_splice_tail_init(&chan->pending_list, &chan->active_list); 1521 chan->desc_pendingcount = 0; 1522 chan->idle = false; 1523 } 1524 1525 /** 1526 * xilinx_dma_start_transfer - Starts DMA transfer 1527 * @chan: Driver specific channel struct pointer 1528 */ 1529 static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan) 1530 { 1531 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; 1532 struct xilinx_axidma_tx_segment *tail_segment; 1533 u32 reg; 1534 1535 if (chan->err) 1536 return; 1537 1538 if (list_empty(&chan->pending_list)) 1539 return; 1540 1541 if (!chan->idle) 1542 return; 1543 1544 head_desc = list_first_entry(&chan->pending_list, 1545 struct xilinx_dma_tx_descriptor, node); 1546 tail_desc = list_last_entry(&chan->pending_list, 1547 struct xilinx_dma_tx_descriptor, node); 1548 tail_segment = list_last_entry(&tail_desc->segments, 1549 struct xilinx_axidma_tx_segment, node); 1550 1551 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 1552 1553 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { 1554 reg &= ~XILINX_DMA_CR_COALESCE_MAX; 1555 reg |= chan->desc_pendingcount << 1556 XILINX_DMA_CR_COALESCE_SHIFT; 1557 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); 1558 } 1559 1560 if (chan->has_sg) 1561 xilinx_write(chan, XILINX_DMA_REG_CURDESC, 1562 head_desc->async_tx.phys); 1563 1564 xilinx_dma_start(chan); 1565 1566 if (chan->err) 1567 return; 1568 1569 /* Start the transfer */ 1570 if (chan->has_sg) { 1571 if (chan->cyclic) 1572 xilinx_write(chan, XILINX_DMA_REG_TAILDESC, 1573 chan->cyclic_seg_v->phys); 1574 else 1575 xilinx_write(chan, XILINX_DMA_REG_TAILDESC, 1576 tail_segment->phys); 1577 } else { 1578 struct xilinx_axidma_tx_segment *segment; 1579 struct xilinx_axidma_desc_hw *hw; 1580 1581 segment = list_first_entry(&head_desc->segments, 1582 struct xilinx_axidma_tx_segment, 1583 node); 1584 hw = &segment->hw; 1585 1586 xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR, 1587 xilinx_prep_dma_addr_t(hw->buf_addr)); 1588 1589 /* Start the transfer */ 1590 dma_ctrl_write(chan, XILINX_DMA_REG_BTT, 1591 hw->control & chan->xdev->max_buffer_len); 1592 } 1593 1594 list_splice_tail_init(&chan->pending_list, &chan->active_list); 1595 chan->desc_pendingcount = 0; 1596 chan->idle = false; 1597 } 1598 1599 /** 1600 * xilinx_mcdma_start_transfer - Starts MCDMA transfer 1601 * @chan: Driver specific channel struct pointer 1602 */ 1603 static void xilinx_mcdma_start_transfer(struct xilinx_dma_chan *chan) 1604 { 1605 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; 1606 struct xilinx_aximcdma_tx_segment *tail_segment; 1607 u32 reg; 1608 1609 /* 1610 * lock has been held by calling functions, so we don't need it 1611 * to take it here again. 1612 */ 1613 1614 if (chan->err) 1615 return; 1616 1617 if (!chan->idle) 1618 return; 1619 1620 if (list_empty(&chan->pending_list)) 1621 return; 1622 1623 head_desc = list_first_entry(&chan->pending_list, 1624 struct xilinx_dma_tx_descriptor, node); 1625 tail_desc = list_last_entry(&chan->pending_list, 1626 struct xilinx_dma_tx_descriptor, node); 1627 tail_segment = list_last_entry(&tail_desc->segments, 1628 struct xilinx_aximcdma_tx_segment, node); 1629 1630 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest)); 1631 1632 if (chan->desc_pendingcount <= XILINX_MCDMA_COALESCE_MAX) { 1633 reg &= ~XILINX_MCDMA_COALESCE_MASK; 1634 reg |= chan->desc_pendingcount << 1635 XILINX_MCDMA_COALESCE_SHIFT; 1636 } 1637 1638 reg |= XILINX_MCDMA_IRQ_ALL_MASK; 1639 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); 1640 1641 /* Program current descriptor */ 1642 xilinx_write(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET(chan->tdest), 1643 head_desc->async_tx.phys); 1644 1645 /* Program channel enable register */ 1646 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHEN_OFFSET); 1647 reg |= BIT(chan->tdest); 1648 dma_ctrl_write(chan, XILINX_MCDMA_CHEN_OFFSET, reg); 1649 1650 /* Start the fetch of BDs for the channel */ 1651 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest)); 1652 reg |= XILINX_MCDMA_CR_RUNSTOP_MASK; 1653 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); 1654 1655 xilinx_dma_start(chan); 1656 1657 if (chan->err) 1658 return; 1659 1660 /* Start the transfer */ 1661 xilinx_write(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET(chan->tdest), 1662 tail_segment->phys); 1663 1664 list_splice_tail_init(&chan->pending_list, &chan->active_list); 1665 chan->desc_pendingcount = 0; 1666 chan->idle = false; 1667 } 1668 1669 /** 1670 * xilinx_dma_issue_pending - Issue pending transactions 1671 * @dchan: DMA channel 1672 */ 1673 static void xilinx_dma_issue_pending(struct dma_chan *dchan) 1674 { 1675 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 1676 unsigned long flags; 1677 1678 spin_lock_irqsave(&chan->lock, flags); 1679 chan->start_transfer(chan); 1680 spin_unlock_irqrestore(&chan->lock, flags); 1681 } 1682 1683 /** 1684 * xilinx_dma_device_config - Configure the DMA channel 1685 * @dchan: DMA channel 1686 * @config: channel configuration 1687 * 1688 * Return: 0 always. 1689 */ 1690 static int xilinx_dma_device_config(struct dma_chan *dchan, 1691 struct dma_slave_config *config) 1692 { 1693 return 0; 1694 } 1695 1696 /** 1697 * xilinx_dma_complete_descriptor - Mark the active descriptor as complete 1698 * @chan : xilinx DMA channel 1699 * 1700 * CONTEXT: hardirq 1701 */ 1702 static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan) 1703 { 1704 struct xilinx_dma_tx_descriptor *desc, *next; 1705 1706 /* This function was invoked with lock held */ 1707 if (list_empty(&chan->active_list)) 1708 return; 1709 1710 list_for_each_entry_safe(desc, next, &chan->active_list, node) { 1711 if (chan->has_sg && chan->xdev->dma_config->dmatype != 1712 XDMA_TYPE_VDMA) 1713 desc->residue = xilinx_dma_get_residue(chan, desc); 1714 else 1715 desc->residue = 0; 1716 desc->err = chan->err; 1717 1718 list_del(&desc->node); 1719 if (!desc->cyclic) 1720 dma_cookie_complete(&desc->async_tx); 1721 list_add_tail(&desc->node, &chan->done_list); 1722 } 1723 } 1724 1725 /** 1726 * xilinx_dma_reset - Reset DMA channel 1727 * @chan: Driver specific DMA channel 1728 * 1729 * Return: '0' on success and failure value on error 1730 */ 1731 static int xilinx_dma_reset(struct xilinx_dma_chan *chan) 1732 { 1733 int err; 1734 u32 tmp; 1735 1736 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET); 1737 1738 /* Wait for the hardware to finish reset */ 1739 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp, 1740 !(tmp & XILINX_DMA_DMACR_RESET), 0, 1741 XILINX_DMA_LOOP_COUNT); 1742 1743 if (err) { 1744 dev_err(chan->dev, "reset timeout, cr %x, sr %x\n", 1745 dma_ctrl_read(chan, XILINX_DMA_REG_DMACR), 1746 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); 1747 return -ETIMEDOUT; 1748 } 1749 1750 chan->err = false; 1751 chan->idle = true; 1752 chan->desc_pendingcount = 0; 1753 chan->desc_submitcount = 0; 1754 1755 return err; 1756 } 1757 1758 /** 1759 * xilinx_dma_chan_reset - Reset DMA channel and enable interrupts 1760 * @chan: Driver specific DMA channel 1761 * 1762 * Return: '0' on success and failure value on error 1763 */ 1764 static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan) 1765 { 1766 int err; 1767 1768 /* Reset VDMA */ 1769 err = xilinx_dma_reset(chan); 1770 if (err) 1771 return err; 1772 1773 /* Enable interrupts */ 1774 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, 1775 XILINX_DMA_DMAXR_ALL_IRQ_MASK); 1776 1777 return 0; 1778 } 1779 1780 /** 1781 * xilinx_mcdma_irq_handler - MCDMA Interrupt handler 1782 * @irq: IRQ number 1783 * @data: Pointer to the Xilinx MCDMA channel structure 1784 * 1785 * Return: IRQ_HANDLED/IRQ_NONE 1786 */ 1787 static irqreturn_t xilinx_mcdma_irq_handler(int irq, void *data) 1788 { 1789 struct xilinx_dma_chan *chan = data; 1790 u32 status, ser_offset, chan_sermask, chan_offset = 0, chan_id; 1791 1792 if (chan->direction == DMA_DEV_TO_MEM) 1793 ser_offset = XILINX_MCDMA_RXINT_SER_OFFSET; 1794 else 1795 ser_offset = XILINX_MCDMA_TXINT_SER_OFFSET; 1796 1797 /* Read the channel id raising the interrupt*/ 1798 chan_sermask = dma_ctrl_read(chan, ser_offset); 1799 chan_id = ffs(chan_sermask); 1800 1801 if (!chan_id) 1802 return IRQ_NONE; 1803 1804 if (chan->direction == DMA_DEV_TO_MEM) 1805 chan_offset = chan->xdev->dma_config->max_channels / 2; 1806 1807 chan_offset = chan_offset + (chan_id - 1); 1808 chan = chan->xdev->chan[chan_offset]; 1809 /* Read the status and ack the interrupts. */ 1810 status = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest)); 1811 if (!(status & XILINX_MCDMA_IRQ_ALL_MASK)) 1812 return IRQ_NONE; 1813 1814 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest), 1815 status & XILINX_MCDMA_IRQ_ALL_MASK); 1816 1817 if (status & XILINX_MCDMA_IRQ_ERR_MASK) { 1818 dev_err(chan->dev, "Channel %p has errors %x cdr %x tdr %x\n", 1819 chan, 1820 dma_ctrl_read(chan, XILINX_MCDMA_CH_ERR_OFFSET), 1821 dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET 1822 (chan->tdest)), 1823 dma_ctrl_read(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET 1824 (chan->tdest))); 1825 chan->err = true; 1826 } 1827 1828 if (status & XILINX_MCDMA_IRQ_DELAY_MASK) { 1829 /* 1830 * Device takes too long to do the transfer when user requires 1831 * responsiveness. 1832 */ 1833 dev_dbg(chan->dev, "Inter-packet latency too long\n"); 1834 } 1835 1836 if (status & XILINX_MCDMA_IRQ_IOC_MASK) { 1837 spin_lock(&chan->lock); 1838 xilinx_dma_complete_descriptor(chan); 1839 chan->idle = true; 1840 chan->start_transfer(chan); 1841 spin_unlock(&chan->lock); 1842 } 1843 1844 tasklet_schedule(&chan->tasklet); 1845 return IRQ_HANDLED; 1846 } 1847 1848 /** 1849 * xilinx_dma_irq_handler - DMA Interrupt handler 1850 * @irq: IRQ number 1851 * @data: Pointer to the Xilinx DMA channel structure 1852 * 1853 * Return: IRQ_HANDLED/IRQ_NONE 1854 */ 1855 static irqreturn_t xilinx_dma_irq_handler(int irq, void *data) 1856 { 1857 struct xilinx_dma_chan *chan = data; 1858 u32 status; 1859 1860 /* Read the status and ack the interrupts. */ 1861 status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR); 1862 if (!(status & XILINX_DMA_DMAXR_ALL_IRQ_MASK)) 1863 return IRQ_NONE; 1864 1865 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR, 1866 status & XILINX_DMA_DMAXR_ALL_IRQ_MASK); 1867 1868 if (status & XILINX_DMA_DMASR_ERR_IRQ) { 1869 /* 1870 * An error occurred. If C_FLUSH_ON_FSYNC is enabled and the 1871 * error is recoverable, ignore it. Otherwise flag the error. 1872 * 1873 * Only recoverable errors can be cleared in the DMASR register, 1874 * make sure not to write to other error bits to 1. 1875 */ 1876 u32 errors = status & XILINX_DMA_DMASR_ALL_ERR_MASK; 1877 1878 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR, 1879 errors & XILINX_DMA_DMASR_ERR_RECOVER_MASK); 1880 1881 if (!chan->flush_on_fsync || 1882 (errors & ~XILINX_DMA_DMASR_ERR_RECOVER_MASK)) { 1883 dev_err(chan->dev, 1884 "Channel %p has errors %x, cdr %x tdr %x\n", 1885 chan, errors, 1886 dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC), 1887 dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC)); 1888 chan->err = true; 1889 } 1890 } 1891 1892 if (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) { 1893 /* 1894 * Device takes too long to do the transfer when user requires 1895 * responsiveness. 1896 */ 1897 dev_dbg(chan->dev, "Inter-packet latency too long\n"); 1898 } 1899 1900 if (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) { 1901 spin_lock(&chan->lock); 1902 xilinx_dma_complete_descriptor(chan); 1903 chan->idle = true; 1904 chan->start_transfer(chan); 1905 spin_unlock(&chan->lock); 1906 } 1907 1908 tasklet_schedule(&chan->tasklet); 1909 return IRQ_HANDLED; 1910 } 1911 1912 /** 1913 * append_desc_queue - Queuing descriptor 1914 * @chan: Driver specific dma channel 1915 * @desc: dma transaction descriptor 1916 */ 1917 static void append_desc_queue(struct xilinx_dma_chan *chan, 1918 struct xilinx_dma_tx_descriptor *desc) 1919 { 1920 struct xilinx_vdma_tx_segment *tail_segment; 1921 struct xilinx_dma_tx_descriptor *tail_desc; 1922 struct xilinx_axidma_tx_segment *axidma_tail_segment; 1923 struct xilinx_aximcdma_tx_segment *aximcdma_tail_segment; 1924 struct xilinx_cdma_tx_segment *cdma_tail_segment; 1925 1926 if (list_empty(&chan->pending_list)) 1927 goto append; 1928 1929 /* 1930 * Add the hardware descriptor to the chain of hardware descriptors 1931 * that already exists in memory. 1932 */ 1933 tail_desc = list_last_entry(&chan->pending_list, 1934 struct xilinx_dma_tx_descriptor, node); 1935 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 1936 tail_segment = list_last_entry(&tail_desc->segments, 1937 struct xilinx_vdma_tx_segment, 1938 node); 1939 tail_segment->hw.next_desc = (u32)desc->async_tx.phys; 1940 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 1941 cdma_tail_segment = list_last_entry(&tail_desc->segments, 1942 struct xilinx_cdma_tx_segment, 1943 node); 1944 cdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; 1945 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 1946 axidma_tail_segment = list_last_entry(&tail_desc->segments, 1947 struct xilinx_axidma_tx_segment, 1948 node); 1949 axidma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; 1950 } else { 1951 aximcdma_tail_segment = 1952 list_last_entry(&tail_desc->segments, 1953 struct xilinx_aximcdma_tx_segment, 1954 node); 1955 aximcdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; 1956 } 1957 1958 /* 1959 * Add the software descriptor and all children to the list 1960 * of pending transactions 1961 */ 1962 append: 1963 list_add_tail(&desc->node, &chan->pending_list); 1964 chan->desc_pendingcount++; 1965 1966 if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) 1967 && unlikely(chan->desc_pendingcount > chan->num_frms)) { 1968 dev_dbg(chan->dev, "desc pendingcount is too high\n"); 1969 chan->desc_pendingcount = chan->num_frms; 1970 } 1971 } 1972 1973 /** 1974 * xilinx_dma_tx_submit - Submit DMA transaction 1975 * @tx: Async transaction descriptor 1976 * 1977 * Return: cookie value on success and failure value on error 1978 */ 1979 static dma_cookie_t xilinx_dma_tx_submit(struct dma_async_tx_descriptor *tx) 1980 { 1981 struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx); 1982 struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan); 1983 dma_cookie_t cookie; 1984 unsigned long flags; 1985 int err; 1986 1987 if (chan->cyclic) { 1988 xilinx_dma_free_tx_descriptor(chan, desc); 1989 return -EBUSY; 1990 } 1991 1992 if (chan->err) { 1993 /* 1994 * If reset fails, need to hard reset the system. 1995 * Channel is no longer functional 1996 */ 1997 err = xilinx_dma_chan_reset(chan); 1998 if (err < 0) 1999 return err; 2000 } 2001 2002 spin_lock_irqsave(&chan->lock, flags); 2003 2004 cookie = dma_cookie_assign(tx); 2005 2006 /* Put this transaction onto the tail of the pending queue */ 2007 append_desc_queue(chan, desc); 2008 2009 if (desc->cyclic) 2010 chan->cyclic = true; 2011 2012 chan->terminating = false; 2013 2014 spin_unlock_irqrestore(&chan->lock, flags); 2015 2016 return cookie; 2017 } 2018 2019 /** 2020 * xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a 2021 * DMA_SLAVE transaction 2022 * @dchan: DMA channel 2023 * @xt: Interleaved template pointer 2024 * @flags: transfer ack flags 2025 * 2026 * Return: Async transaction descriptor on success and NULL on failure 2027 */ 2028 static struct dma_async_tx_descriptor * 2029 xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan, 2030 struct dma_interleaved_template *xt, 2031 unsigned long flags) 2032 { 2033 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2034 struct xilinx_dma_tx_descriptor *desc; 2035 struct xilinx_vdma_tx_segment *segment; 2036 struct xilinx_vdma_desc_hw *hw; 2037 2038 if (!is_slave_direction(xt->dir)) 2039 return NULL; 2040 2041 if (!xt->numf || !xt->sgl[0].size) 2042 return NULL; 2043 2044 if (xt->frame_size != 1) 2045 return NULL; 2046 2047 /* Allocate a transaction descriptor. */ 2048 desc = xilinx_dma_alloc_tx_descriptor(chan); 2049 if (!desc) 2050 return NULL; 2051 2052 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2053 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2054 async_tx_ack(&desc->async_tx); 2055 2056 /* Allocate the link descriptor from DMA pool */ 2057 segment = xilinx_vdma_alloc_tx_segment(chan); 2058 if (!segment) 2059 goto error; 2060 2061 /* Fill in the hardware descriptor */ 2062 hw = &segment->hw; 2063 hw->vsize = xt->numf; 2064 hw->hsize = xt->sgl[0].size; 2065 hw->stride = (xt->sgl[0].icg + xt->sgl[0].size) << 2066 XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT; 2067 hw->stride |= chan->config.frm_dly << 2068 XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT; 2069 2070 if (xt->dir != DMA_MEM_TO_DEV) { 2071 if (chan->ext_addr) { 2072 hw->buf_addr = lower_32_bits(xt->dst_start); 2073 hw->buf_addr_msb = upper_32_bits(xt->dst_start); 2074 } else { 2075 hw->buf_addr = xt->dst_start; 2076 } 2077 } else { 2078 if (chan->ext_addr) { 2079 hw->buf_addr = lower_32_bits(xt->src_start); 2080 hw->buf_addr_msb = upper_32_bits(xt->src_start); 2081 } else { 2082 hw->buf_addr = xt->src_start; 2083 } 2084 } 2085 2086 /* Insert the segment into the descriptor segments list. */ 2087 list_add_tail(&segment->node, &desc->segments); 2088 2089 /* Link the last hardware descriptor with the first. */ 2090 segment = list_first_entry(&desc->segments, 2091 struct xilinx_vdma_tx_segment, node); 2092 desc->async_tx.phys = segment->phys; 2093 2094 return &desc->async_tx; 2095 2096 error: 2097 xilinx_dma_free_tx_descriptor(chan, desc); 2098 return NULL; 2099 } 2100 2101 /** 2102 * xilinx_cdma_prep_memcpy - prepare descriptors for a memcpy transaction 2103 * @dchan: DMA channel 2104 * @dma_dst: destination address 2105 * @dma_src: source address 2106 * @len: transfer length 2107 * @flags: transfer ack flags 2108 * 2109 * Return: Async transaction descriptor on success and NULL on failure 2110 */ 2111 static struct dma_async_tx_descriptor * 2112 xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst, 2113 dma_addr_t dma_src, size_t len, unsigned long flags) 2114 { 2115 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2116 struct xilinx_dma_tx_descriptor *desc; 2117 struct xilinx_cdma_tx_segment *segment; 2118 struct xilinx_cdma_desc_hw *hw; 2119 2120 if (!len || len > chan->xdev->max_buffer_len) 2121 return NULL; 2122 2123 desc = xilinx_dma_alloc_tx_descriptor(chan); 2124 if (!desc) 2125 return NULL; 2126 2127 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2128 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2129 2130 /* Allocate the link descriptor from DMA pool */ 2131 segment = xilinx_cdma_alloc_tx_segment(chan); 2132 if (!segment) 2133 goto error; 2134 2135 hw = &segment->hw; 2136 hw->control = len; 2137 hw->src_addr = dma_src; 2138 hw->dest_addr = dma_dst; 2139 if (chan->ext_addr) { 2140 hw->src_addr_msb = upper_32_bits(dma_src); 2141 hw->dest_addr_msb = upper_32_bits(dma_dst); 2142 } 2143 2144 /* Insert the segment into the descriptor segments list. */ 2145 list_add_tail(&segment->node, &desc->segments); 2146 2147 desc->async_tx.phys = segment->phys; 2148 hw->next_desc = segment->phys; 2149 2150 return &desc->async_tx; 2151 2152 error: 2153 xilinx_dma_free_tx_descriptor(chan, desc); 2154 return NULL; 2155 } 2156 2157 /** 2158 * xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction 2159 * @dchan: DMA channel 2160 * @sgl: scatterlist to transfer to/from 2161 * @sg_len: number of entries in @scatterlist 2162 * @direction: DMA direction 2163 * @flags: transfer ack flags 2164 * @context: APP words of the descriptor 2165 * 2166 * Return: Async transaction descriptor on success and NULL on failure 2167 */ 2168 static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( 2169 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, 2170 enum dma_transfer_direction direction, unsigned long flags, 2171 void *context) 2172 { 2173 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2174 struct xilinx_dma_tx_descriptor *desc; 2175 struct xilinx_axidma_tx_segment *segment = NULL; 2176 u32 *app_w = (u32 *)context; 2177 struct scatterlist *sg; 2178 size_t copy; 2179 size_t sg_used; 2180 unsigned int i; 2181 2182 if (!is_slave_direction(direction)) 2183 return NULL; 2184 2185 /* Allocate a transaction descriptor. */ 2186 desc = xilinx_dma_alloc_tx_descriptor(chan); 2187 if (!desc) 2188 return NULL; 2189 2190 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2191 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2192 2193 /* Build transactions using information in the scatter gather list */ 2194 for_each_sg(sgl, sg, sg_len, i) { 2195 sg_used = 0; 2196 2197 /* Loop until the entire scatterlist entry is used */ 2198 while (sg_used < sg_dma_len(sg)) { 2199 struct xilinx_axidma_desc_hw *hw; 2200 2201 /* Get a free segment */ 2202 segment = xilinx_axidma_alloc_tx_segment(chan); 2203 if (!segment) 2204 goto error; 2205 2206 /* 2207 * Calculate the maximum number of bytes to transfer, 2208 * making sure it is less than the hw limit 2209 */ 2210 copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg), 2211 sg_used); 2212 hw = &segment->hw; 2213 2214 /* Fill in the descriptor */ 2215 xilinx_axidma_buf(chan, hw, sg_dma_address(sg), 2216 sg_used, 0); 2217 2218 hw->control = copy; 2219 2220 if (chan->direction == DMA_MEM_TO_DEV) { 2221 if (app_w) 2222 memcpy(hw->app, app_w, sizeof(u32) * 2223 XILINX_DMA_NUM_APP_WORDS); 2224 } 2225 2226 sg_used += copy; 2227 2228 /* 2229 * Insert the segment into the descriptor segments 2230 * list. 2231 */ 2232 list_add_tail(&segment->node, &desc->segments); 2233 } 2234 } 2235 2236 segment = list_first_entry(&desc->segments, 2237 struct xilinx_axidma_tx_segment, node); 2238 desc->async_tx.phys = segment->phys; 2239 2240 /* For the last DMA_MEM_TO_DEV transfer, set EOP */ 2241 if (chan->direction == DMA_MEM_TO_DEV) { 2242 segment->hw.control |= XILINX_DMA_BD_SOP; 2243 segment = list_last_entry(&desc->segments, 2244 struct xilinx_axidma_tx_segment, 2245 node); 2246 segment->hw.control |= XILINX_DMA_BD_EOP; 2247 } 2248 2249 if (chan->xdev->has_axistream_connected) 2250 desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops; 2251 2252 return &desc->async_tx; 2253 2254 error: 2255 xilinx_dma_free_tx_descriptor(chan, desc); 2256 return NULL; 2257 } 2258 2259 /** 2260 * xilinx_dma_prep_dma_cyclic - prepare descriptors for a DMA_SLAVE transaction 2261 * @dchan: DMA channel 2262 * @buf_addr: Physical address of the buffer 2263 * @buf_len: Total length of the cyclic buffers 2264 * @period_len: length of individual cyclic buffer 2265 * @direction: DMA direction 2266 * @flags: transfer ack flags 2267 * 2268 * Return: Async transaction descriptor on success and NULL on failure 2269 */ 2270 static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic( 2271 struct dma_chan *dchan, dma_addr_t buf_addr, size_t buf_len, 2272 size_t period_len, enum dma_transfer_direction direction, 2273 unsigned long flags) 2274 { 2275 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2276 struct xilinx_dma_tx_descriptor *desc; 2277 struct xilinx_axidma_tx_segment *segment, *head_segment, *prev = NULL; 2278 size_t copy, sg_used; 2279 unsigned int num_periods; 2280 int i; 2281 u32 reg; 2282 2283 if (!period_len) 2284 return NULL; 2285 2286 num_periods = buf_len / period_len; 2287 2288 if (!num_periods) 2289 return NULL; 2290 2291 if (!is_slave_direction(direction)) 2292 return NULL; 2293 2294 /* Allocate a transaction descriptor. */ 2295 desc = xilinx_dma_alloc_tx_descriptor(chan); 2296 if (!desc) 2297 return NULL; 2298 2299 chan->direction = direction; 2300 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2301 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2302 2303 for (i = 0; i < num_periods; ++i) { 2304 sg_used = 0; 2305 2306 while (sg_used < period_len) { 2307 struct xilinx_axidma_desc_hw *hw; 2308 2309 /* Get a free segment */ 2310 segment = xilinx_axidma_alloc_tx_segment(chan); 2311 if (!segment) 2312 goto error; 2313 2314 /* 2315 * Calculate the maximum number of bytes to transfer, 2316 * making sure it is less than the hw limit 2317 */ 2318 copy = xilinx_dma_calc_copysize(chan, period_len, 2319 sg_used); 2320 hw = &segment->hw; 2321 xilinx_axidma_buf(chan, hw, buf_addr, sg_used, 2322 period_len * i); 2323 hw->control = copy; 2324 2325 if (prev) 2326 prev->hw.next_desc = segment->phys; 2327 2328 prev = segment; 2329 sg_used += copy; 2330 2331 /* 2332 * Insert the segment into the descriptor segments 2333 * list. 2334 */ 2335 list_add_tail(&segment->node, &desc->segments); 2336 } 2337 } 2338 2339 head_segment = list_first_entry(&desc->segments, 2340 struct xilinx_axidma_tx_segment, node); 2341 desc->async_tx.phys = head_segment->phys; 2342 2343 desc->cyclic = true; 2344 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 2345 reg |= XILINX_DMA_CR_CYCLIC_BD_EN_MASK; 2346 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); 2347 2348 segment = list_last_entry(&desc->segments, 2349 struct xilinx_axidma_tx_segment, 2350 node); 2351 segment->hw.next_desc = (u32) head_segment->phys; 2352 2353 /* For the last DMA_MEM_TO_DEV transfer, set EOP */ 2354 if (direction == DMA_MEM_TO_DEV) { 2355 head_segment->hw.control |= XILINX_DMA_BD_SOP; 2356 segment->hw.control |= XILINX_DMA_BD_EOP; 2357 } 2358 2359 return &desc->async_tx; 2360 2361 error: 2362 xilinx_dma_free_tx_descriptor(chan, desc); 2363 return NULL; 2364 } 2365 2366 /** 2367 * xilinx_mcdma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction 2368 * @dchan: DMA channel 2369 * @sgl: scatterlist to transfer to/from 2370 * @sg_len: number of entries in @scatterlist 2371 * @direction: DMA direction 2372 * @flags: transfer ack flags 2373 * @context: APP words of the descriptor 2374 * 2375 * Return: Async transaction descriptor on success and NULL on failure 2376 */ 2377 static struct dma_async_tx_descriptor * 2378 xilinx_mcdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, 2379 unsigned int sg_len, 2380 enum dma_transfer_direction direction, 2381 unsigned long flags, void *context) 2382 { 2383 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2384 struct xilinx_dma_tx_descriptor *desc; 2385 struct xilinx_aximcdma_tx_segment *segment = NULL; 2386 u32 *app_w = (u32 *)context; 2387 struct scatterlist *sg; 2388 size_t copy; 2389 size_t sg_used; 2390 unsigned int i; 2391 2392 if (!is_slave_direction(direction)) 2393 return NULL; 2394 2395 /* Allocate a transaction descriptor. */ 2396 desc = xilinx_dma_alloc_tx_descriptor(chan); 2397 if (!desc) 2398 return NULL; 2399 2400 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2401 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2402 2403 /* Build transactions using information in the scatter gather list */ 2404 for_each_sg(sgl, sg, sg_len, i) { 2405 sg_used = 0; 2406 2407 /* Loop until the entire scatterlist entry is used */ 2408 while (sg_used < sg_dma_len(sg)) { 2409 struct xilinx_aximcdma_desc_hw *hw; 2410 2411 /* Get a free segment */ 2412 segment = xilinx_aximcdma_alloc_tx_segment(chan); 2413 if (!segment) 2414 goto error; 2415 2416 /* 2417 * Calculate the maximum number of bytes to transfer, 2418 * making sure it is less than the hw limit 2419 */ 2420 copy = min_t(size_t, sg_dma_len(sg) - sg_used, 2421 chan->xdev->max_buffer_len); 2422 hw = &segment->hw; 2423 2424 /* Fill in the descriptor */ 2425 xilinx_aximcdma_buf(chan, hw, sg_dma_address(sg), 2426 sg_used); 2427 hw->control = copy; 2428 2429 if (chan->direction == DMA_MEM_TO_DEV && app_w) { 2430 memcpy(hw->app, app_w, sizeof(u32) * 2431 XILINX_DMA_NUM_APP_WORDS); 2432 } 2433 2434 sg_used += copy; 2435 /* 2436 * Insert the segment into the descriptor segments 2437 * list. 2438 */ 2439 list_add_tail(&segment->node, &desc->segments); 2440 } 2441 } 2442 2443 segment = list_first_entry(&desc->segments, 2444 struct xilinx_aximcdma_tx_segment, node); 2445 desc->async_tx.phys = segment->phys; 2446 2447 /* For the last DMA_MEM_TO_DEV transfer, set EOP */ 2448 if (chan->direction == DMA_MEM_TO_DEV) { 2449 segment->hw.control |= XILINX_MCDMA_BD_SOP; 2450 segment = list_last_entry(&desc->segments, 2451 struct xilinx_aximcdma_tx_segment, 2452 node); 2453 segment->hw.control |= XILINX_MCDMA_BD_EOP; 2454 } 2455 2456 return &desc->async_tx; 2457 2458 error: 2459 xilinx_dma_free_tx_descriptor(chan, desc); 2460 2461 return NULL; 2462 } 2463 2464 /** 2465 * xilinx_dma_terminate_all - Halt the channel and free descriptors 2466 * @dchan: Driver specific DMA Channel pointer 2467 * 2468 * Return: '0' always. 2469 */ 2470 static int xilinx_dma_terminate_all(struct dma_chan *dchan) 2471 { 2472 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2473 u32 reg; 2474 int err; 2475 2476 if (!chan->cyclic) { 2477 err = chan->stop_transfer(chan); 2478 if (err) { 2479 dev_err(chan->dev, "Cannot stop channel %p: %x\n", 2480 chan, dma_ctrl_read(chan, 2481 XILINX_DMA_REG_DMASR)); 2482 chan->err = true; 2483 } 2484 } 2485 2486 xilinx_dma_chan_reset(chan); 2487 /* Remove and free all of the descriptors in the lists */ 2488 chan->terminating = true; 2489 xilinx_dma_free_descriptors(chan); 2490 chan->idle = true; 2491 2492 if (chan->cyclic) { 2493 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 2494 reg &= ~XILINX_DMA_CR_CYCLIC_BD_EN_MASK; 2495 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); 2496 chan->cyclic = false; 2497 } 2498 2499 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) 2500 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, 2501 XILINX_CDMA_CR_SGMODE); 2502 2503 return 0; 2504 } 2505 2506 static void xilinx_dma_synchronize(struct dma_chan *dchan) 2507 { 2508 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2509 2510 tasklet_kill(&chan->tasklet); 2511 } 2512 2513 /** 2514 * xilinx_vdma_channel_set_config - Configure VDMA channel 2515 * Run-time configuration for Axi VDMA, supports: 2516 * . halt the channel 2517 * . configure interrupt coalescing and inter-packet delay threshold 2518 * . start/stop parking 2519 * . enable genlock 2520 * 2521 * @dchan: DMA channel 2522 * @cfg: VDMA device configuration pointer 2523 * 2524 * Return: '0' on success and failure value on error 2525 */ 2526 int xilinx_vdma_channel_set_config(struct dma_chan *dchan, 2527 struct xilinx_vdma_config *cfg) 2528 { 2529 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2530 u32 dmacr; 2531 2532 if (cfg->reset) 2533 return xilinx_dma_chan_reset(chan); 2534 2535 dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 2536 2537 chan->config.frm_dly = cfg->frm_dly; 2538 chan->config.park = cfg->park; 2539 2540 /* genlock settings */ 2541 chan->config.gen_lock = cfg->gen_lock; 2542 chan->config.master = cfg->master; 2543 2544 dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN; 2545 if (cfg->gen_lock && chan->genlock) { 2546 dmacr |= XILINX_DMA_DMACR_GENLOCK_EN; 2547 dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK; 2548 dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT; 2549 } 2550 2551 chan->config.frm_cnt_en = cfg->frm_cnt_en; 2552 chan->config.vflip_en = cfg->vflip_en; 2553 2554 if (cfg->park) 2555 chan->config.park_frm = cfg->park_frm; 2556 else 2557 chan->config.park_frm = -1; 2558 2559 chan->config.coalesc = cfg->coalesc; 2560 chan->config.delay = cfg->delay; 2561 2562 if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) { 2563 dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK; 2564 dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT; 2565 chan->config.coalesc = cfg->coalesc; 2566 } 2567 2568 if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) { 2569 dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK; 2570 dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT; 2571 chan->config.delay = cfg->delay; 2572 } 2573 2574 /* FSync Source selection */ 2575 dmacr &= ~XILINX_DMA_DMACR_FSYNCSRC_MASK; 2576 dmacr |= cfg->ext_fsync << XILINX_DMA_DMACR_FSYNCSRC_SHIFT; 2577 2578 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr); 2579 2580 return 0; 2581 } 2582 EXPORT_SYMBOL(xilinx_vdma_channel_set_config); 2583 2584 /* ----------------------------------------------------------------------------- 2585 * Probe and remove 2586 */ 2587 2588 /** 2589 * xilinx_dma_chan_remove - Per Channel remove function 2590 * @chan: Driver specific DMA channel 2591 */ 2592 static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan) 2593 { 2594 /* Disable all interrupts */ 2595 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, 2596 XILINX_DMA_DMAXR_ALL_IRQ_MASK); 2597 2598 if (chan->irq > 0) 2599 free_irq(chan->irq, chan); 2600 2601 tasklet_kill(&chan->tasklet); 2602 2603 list_del(&chan->common.device_node); 2604 } 2605 2606 static int axidma_clk_init(struct platform_device *pdev, struct clk **axi_clk, 2607 struct clk **tx_clk, struct clk **rx_clk, 2608 struct clk **sg_clk, struct clk **tmp_clk) 2609 { 2610 int err; 2611 2612 *tmp_clk = NULL; 2613 2614 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); 2615 if (IS_ERR(*axi_clk)) 2616 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n"); 2617 2618 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk"); 2619 if (IS_ERR(*tx_clk)) 2620 *tx_clk = NULL; 2621 2622 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk"); 2623 if (IS_ERR(*rx_clk)) 2624 *rx_clk = NULL; 2625 2626 *sg_clk = devm_clk_get(&pdev->dev, "m_axi_sg_aclk"); 2627 if (IS_ERR(*sg_clk)) 2628 *sg_clk = NULL; 2629 2630 err = clk_prepare_enable(*axi_clk); 2631 if (err) { 2632 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err); 2633 return err; 2634 } 2635 2636 err = clk_prepare_enable(*tx_clk); 2637 if (err) { 2638 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); 2639 goto err_disable_axiclk; 2640 } 2641 2642 err = clk_prepare_enable(*rx_clk); 2643 if (err) { 2644 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); 2645 goto err_disable_txclk; 2646 } 2647 2648 err = clk_prepare_enable(*sg_clk); 2649 if (err) { 2650 dev_err(&pdev->dev, "failed to enable sg_clk (%d)\n", err); 2651 goto err_disable_rxclk; 2652 } 2653 2654 return 0; 2655 2656 err_disable_rxclk: 2657 clk_disable_unprepare(*rx_clk); 2658 err_disable_txclk: 2659 clk_disable_unprepare(*tx_clk); 2660 err_disable_axiclk: 2661 clk_disable_unprepare(*axi_clk); 2662 2663 return err; 2664 } 2665 2666 static int axicdma_clk_init(struct platform_device *pdev, struct clk **axi_clk, 2667 struct clk **dev_clk, struct clk **tmp_clk, 2668 struct clk **tmp1_clk, struct clk **tmp2_clk) 2669 { 2670 int err; 2671 2672 *tmp_clk = NULL; 2673 *tmp1_clk = NULL; 2674 *tmp2_clk = NULL; 2675 2676 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); 2677 if (IS_ERR(*axi_clk)) 2678 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n"); 2679 2680 *dev_clk = devm_clk_get(&pdev->dev, "m_axi_aclk"); 2681 if (IS_ERR(*dev_clk)) 2682 return dev_err_probe(&pdev->dev, PTR_ERR(*dev_clk), "failed to get dev_clk\n"); 2683 2684 err = clk_prepare_enable(*axi_clk); 2685 if (err) { 2686 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err); 2687 return err; 2688 } 2689 2690 err = clk_prepare_enable(*dev_clk); 2691 if (err) { 2692 dev_err(&pdev->dev, "failed to enable dev_clk (%d)\n", err); 2693 goto err_disable_axiclk; 2694 } 2695 2696 return 0; 2697 2698 err_disable_axiclk: 2699 clk_disable_unprepare(*axi_clk); 2700 2701 return err; 2702 } 2703 2704 static int axivdma_clk_init(struct platform_device *pdev, struct clk **axi_clk, 2705 struct clk **tx_clk, struct clk **txs_clk, 2706 struct clk **rx_clk, struct clk **rxs_clk) 2707 { 2708 int err; 2709 2710 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); 2711 if (IS_ERR(*axi_clk)) 2712 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n"); 2713 2714 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk"); 2715 if (IS_ERR(*tx_clk)) 2716 *tx_clk = NULL; 2717 2718 *txs_clk = devm_clk_get(&pdev->dev, "m_axis_mm2s_aclk"); 2719 if (IS_ERR(*txs_clk)) 2720 *txs_clk = NULL; 2721 2722 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk"); 2723 if (IS_ERR(*rx_clk)) 2724 *rx_clk = NULL; 2725 2726 *rxs_clk = devm_clk_get(&pdev->dev, "s_axis_s2mm_aclk"); 2727 if (IS_ERR(*rxs_clk)) 2728 *rxs_clk = NULL; 2729 2730 err = clk_prepare_enable(*axi_clk); 2731 if (err) { 2732 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", 2733 err); 2734 return err; 2735 } 2736 2737 err = clk_prepare_enable(*tx_clk); 2738 if (err) { 2739 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); 2740 goto err_disable_axiclk; 2741 } 2742 2743 err = clk_prepare_enable(*txs_clk); 2744 if (err) { 2745 dev_err(&pdev->dev, "failed to enable txs_clk (%d)\n", err); 2746 goto err_disable_txclk; 2747 } 2748 2749 err = clk_prepare_enable(*rx_clk); 2750 if (err) { 2751 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); 2752 goto err_disable_txsclk; 2753 } 2754 2755 err = clk_prepare_enable(*rxs_clk); 2756 if (err) { 2757 dev_err(&pdev->dev, "failed to enable rxs_clk (%d)\n", err); 2758 goto err_disable_rxclk; 2759 } 2760 2761 return 0; 2762 2763 err_disable_rxclk: 2764 clk_disable_unprepare(*rx_clk); 2765 err_disable_txsclk: 2766 clk_disable_unprepare(*txs_clk); 2767 err_disable_txclk: 2768 clk_disable_unprepare(*tx_clk); 2769 err_disable_axiclk: 2770 clk_disable_unprepare(*axi_clk); 2771 2772 return err; 2773 } 2774 2775 static void xdma_disable_allclks(struct xilinx_dma_device *xdev) 2776 { 2777 clk_disable_unprepare(xdev->rxs_clk); 2778 clk_disable_unprepare(xdev->rx_clk); 2779 clk_disable_unprepare(xdev->txs_clk); 2780 clk_disable_unprepare(xdev->tx_clk); 2781 clk_disable_unprepare(xdev->axi_clk); 2782 } 2783 2784 /** 2785 * xilinx_dma_chan_probe - Per Channel Probing 2786 * It get channel features from the device tree entry and 2787 * initialize special channel handling routines 2788 * 2789 * @xdev: Driver specific device structure 2790 * @node: Device node 2791 * 2792 * Return: '0' on success and failure value on error 2793 */ 2794 static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, 2795 struct device_node *node) 2796 { 2797 struct xilinx_dma_chan *chan; 2798 bool has_dre = false; 2799 u32 value, width; 2800 int err; 2801 2802 /* Allocate and initialize the channel structure */ 2803 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL); 2804 if (!chan) 2805 return -ENOMEM; 2806 2807 chan->dev = xdev->dev; 2808 chan->xdev = xdev; 2809 chan->desc_pendingcount = 0x0; 2810 chan->ext_addr = xdev->ext_addr; 2811 /* This variable ensures that descriptors are not 2812 * Submitted when dma engine is in progress. This variable is 2813 * Added to avoid polling for a bit in the status register to 2814 * Know dma state in the driver hot path. 2815 */ 2816 chan->idle = true; 2817 2818 spin_lock_init(&chan->lock); 2819 INIT_LIST_HEAD(&chan->pending_list); 2820 INIT_LIST_HEAD(&chan->done_list); 2821 INIT_LIST_HEAD(&chan->active_list); 2822 INIT_LIST_HEAD(&chan->free_seg_list); 2823 2824 /* Retrieve the channel properties from the device tree */ 2825 has_dre = of_property_read_bool(node, "xlnx,include-dre"); 2826 2827 chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode"); 2828 2829 err = of_property_read_u32(node, "xlnx,datawidth", &value); 2830 if (err) { 2831 dev_err(xdev->dev, "missing xlnx,datawidth property\n"); 2832 return err; 2833 } 2834 width = value >> 3; /* Convert bits to bytes */ 2835 2836 /* If data width is greater than 8 bytes, DRE is not in hw */ 2837 if (width > 8) 2838 has_dre = false; 2839 2840 if (!has_dre) 2841 xdev->common.copy_align = (enum dmaengine_alignment)fls(width - 1); 2842 2843 if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel") || 2844 of_device_is_compatible(node, "xlnx,axi-dma-mm2s-channel") || 2845 of_device_is_compatible(node, "xlnx,axi-cdma-channel")) { 2846 chan->direction = DMA_MEM_TO_DEV; 2847 chan->id = xdev->mm2s_chan_id++; 2848 chan->tdest = chan->id; 2849 2850 chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; 2851 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 2852 chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET; 2853 chan->config.park = 1; 2854 2855 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH || 2856 xdev->flush_on_fsync == XILINX_DMA_FLUSH_MM2S) 2857 chan->flush_on_fsync = true; 2858 } 2859 } else if (of_device_is_compatible(node, 2860 "xlnx,axi-vdma-s2mm-channel") || 2861 of_device_is_compatible(node, 2862 "xlnx,axi-dma-s2mm-channel")) { 2863 chan->direction = DMA_DEV_TO_MEM; 2864 chan->id = xdev->s2mm_chan_id++; 2865 chan->tdest = chan->id - xdev->dma_config->max_channels / 2; 2866 chan->has_vflip = of_property_read_bool(node, 2867 "xlnx,enable-vert-flip"); 2868 if (chan->has_vflip) { 2869 chan->config.vflip_en = dma_read(chan, 2870 XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP) & 2871 XILINX_VDMA_ENABLE_VERTICAL_FLIP; 2872 } 2873 2874 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) 2875 chan->ctrl_offset = XILINX_MCDMA_S2MM_CTRL_OFFSET; 2876 else 2877 chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; 2878 2879 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 2880 chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET; 2881 chan->config.park = 1; 2882 2883 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH || 2884 xdev->flush_on_fsync == XILINX_DMA_FLUSH_S2MM) 2885 chan->flush_on_fsync = true; 2886 } 2887 } else { 2888 dev_err(xdev->dev, "Invalid channel compatible node\n"); 2889 return -EINVAL; 2890 } 2891 2892 /* Request the interrupt */ 2893 chan->irq = of_irq_get(node, chan->tdest); 2894 if (chan->irq < 0) 2895 return dev_err_probe(xdev->dev, chan->irq, "failed to get irq\n"); 2896 err = request_irq(chan->irq, xdev->dma_config->irq_handler, 2897 IRQF_SHARED, "xilinx-dma-controller", chan); 2898 if (err) { 2899 dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq); 2900 return err; 2901 } 2902 2903 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 2904 chan->start_transfer = xilinx_dma_start_transfer; 2905 chan->stop_transfer = xilinx_dma_stop_transfer; 2906 } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 2907 chan->start_transfer = xilinx_mcdma_start_transfer; 2908 chan->stop_transfer = xilinx_dma_stop_transfer; 2909 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 2910 chan->start_transfer = xilinx_cdma_start_transfer; 2911 chan->stop_transfer = xilinx_cdma_stop_transfer; 2912 } else { 2913 chan->start_transfer = xilinx_vdma_start_transfer; 2914 chan->stop_transfer = xilinx_dma_stop_transfer; 2915 } 2916 2917 /* check if SG is enabled (only for AXIDMA, AXIMCDMA, and CDMA) */ 2918 if (xdev->dma_config->dmatype != XDMA_TYPE_VDMA) { 2919 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA || 2920 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) & 2921 XILINX_DMA_DMASR_SG_MASK) 2922 chan->has_sg = true; 2923 dev_dbg(chan->dev, "ch %d: SG %s\n", chan->id, 2924 chan->has_sg ? "enabled" : "disabled"); 2925 } 2926 2927 /* Initialize the tasklet */ 2928 tasklet_setup(&chan->tasklet, xilinx_dma_do_tasklet); 2929 2930 /* 2931 * Initialize the DMA channel and add it to the DMA engine channels 2932 * list. 2933 */ 2934 chan->common.device = &xdev->common; 2935 2936 list_add_tail(&chan->common.device_node, &xdev->common.channels); 2937 xdev->chan[chan->id] = chan; 2938 2939 /* Reset the channel */ 2940 err = xilinx_dma_chan_reset(chan); 2941 if (err < 0) { 2942 dev_err(xdev->dev, "Reset channel failed\n"); 2943 return err; 2944 } 2945 2946 return 0; 2947 } 2948 2949 /** 2950 * xilinx_dma_child_probe - Per child node probe 2951 * It get number of dma-channels per child node from 2952 * device-tree and initializes all the channels. 2953 * 2954 * @xdev: Driver specific device structure 2955 * @node: Device node 2956 * 2957 * Return: '0' on success and failure value on error. 2958 */ 2959 static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev, 2960 struct device_node *node) 2961 { 2962 int ret, i; 2963 u32 nr_channels = 1; 2964 2965 ret = of_property_read_u32(node, "dma-channels", &nr_channels); 2966 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA && ret < 0) 2967 dev_warn(xdev->dev, "missing dma-channels property\n"); 2968 2969 for (i = 0; i < nr_channels; i++) { 2970 ret = xilinx_dma_chan_probe(xdev, node); 2971 if (ret) 2972 return ret; 2973 } 2974 2975 return 0; 2976 } 2977 2978 /** 2979 * of_dma_xilinx_xlate - Translation function 2980 * @dma_spec: Pointer to DMA specifier as found in the device tree 2981 * @ofdma: Pointer to DMA controller data 2982 * 2983 * Return: DMA channel pointer on success and NULL on error 2984 */ 2985 static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec, 2986 struct of_dma *ofdma) 2987 { 2988 struct xilinx_dma_device *xdev = ofdma->of_dma_data; 2989 int chan_id = dma_spec->args[0]; 2990 2991 if (chan_id >= xdev->dma_config->max_channels || !xdev->chan[chan_id]) 2992 return NULL; 2993 2994 return dma_get_slave_channel(&xdev->chan[chan_id]->common); 2995 } 2996 2997 static const struct xilinx_dma_config axidma_config = { 2998 .dmatype = XDMA_TYPE_AXIDMA, 2999 .clk_init = axidma_clk_init, 3000 .irq_handler = xilinx_dma_irq_handler, 3001 .max_channels = XILINX_DMA_MAX_CHANS_PER_DEVICE, 3002 }; 3003 3004 static const struct xilinx_dma_config aximcdma_config = { 3005 .dmatype = XDMA_TYPE_AXIMCDMA, 3006 .clk_init = axidma_clk_init, 3007 .irq_handler = xilinx_mcdma_irq_handler, 3008 .max_channels = XILINX_MCDMA_MAX_CHANS_PER_DEVICE, 3009 }; 3010 static const struct xilinx_dma_config axicdma_config = { 3011 .dmatype = XDMA_TYPE_CDMA, 3012 .clk_init = axicdma_clk_init, 3013 .irq_handler = xilinx_dma_irq_handler, 3014 .max_channels = XILINX_CDMA_MAX_CHANS_PER_DEVICE, 3015 }; 3016 3017 static const struct xilinx_dma_config axivdma_config = { 3018 .dmatype = XDMA_TYPE_VDMA, 3019 .clk_init = axivdma_clk_init, 3020 .irq_handler = xilinx_dma_irq_handler, 3021 .max_channels = XILINX_DMA_MAX_CHANS_PER_DEVICE, 3022 }; 3023 3024 static const struct of_device_id xilinx_dma_of_ids[] = { 3025 { .compatible = "xlnx,axi-dma-1.00.a", .data = &axidma_config }, 3026 { .compatible = "xlnx,axi-cdma-1.00.a", .data = &axicdma_config }, 3027 { .compatible = "xlnx,axi-vdma-1.00.a", .data = &axivdma_config }, 3028 { .compatible = "xlnx,axi-mcdma-1.00.a", .data = &aximcdma_config }, 3029 {} 3030 }; 3031 MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids); 3032 3033 /** 3034 * xilinx_dma_probe - Driver probe function 3035 * @pdev: Pointer to the platform_device structure 3036 * 3037 * Return: '0' on success and failure value on error 3038 */ 3039 static int xilinx_dma_probe(struct platform_device *pdev) 3040 { 3041 int (*clk_init)(struct platform_device *, struct clk **, struct clk **, 3042 struct clk **, struct clk **, struct clk **) 3043 = axivdma_clk_init; 3044 struct device_node *node = pdev->dev.of_node; 3045 struct xilinx_dma_device *xdev; 3046 struct device_node *child, *np = pdev->dev.of_node; 3047 u32 num_frames, addr_width, len_width; 3048 int i, err; 3049 3050 /* Allocate and initialize the DMA engine structure */ 3051 xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL); 3052 if (!xdev) 3053 return -ENOMEM; 3054 3055 xdev->dev = &pdev->dev; 3056 if (np) { 3057 const struct of_device_id *match; 3058 3059 match = of_match_node(xilinx_dma_of_ids, np); 3060 if (match && match->data) { 3061 xdev->dma_config = match->data; 3062 clk_init = xdev->dma_config->clk_init; 3063 } 3064 } 3065 3066 err = clk_init(pdev, &xdev->axi_clk, &xdev->tx_clk, &xdev->txs_clk, 3067 &xdev->rx_clk, &xdev->rxs_clk); 3068 if (err) 3069 return err; 3070 3071 /* Request and map I/O memory */ 3072 xdev->regs = devm_platform_ioremap_resource(pdev, 0); 3073 if (IS_ERR(xdev->regs)) { 3074 err = PTR_ERR(xdev->regs); 3075 goto disable_clks; 3076 } 3077 /* Retrieve the DMA engine properties from the device tree */ 3078 xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0); 3079 xdev->s2mm_chan_id = xdev->dma_config->max_channels / 2; 3080 3081 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA || 3082 xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 3083 if (!of_property_read_u32(node, "xlnx,sg-length-width", 3084 &len_width)) { 3085 if (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN || 3086 len_width > XILINX_DMA_V2_MAX_TRANS_LEN_MAX) { 3087 dev_warn(xdev->dev, 3088 "invalid xlnx,sg-length-width property value. Using default width\n"); 3089 } else { 3090 if (len_width > XILINX_DMA_MAX_TRANS_LEN_MAX) 3091 dev_warn(xdev->dev, "Please ensure that IP supports buffer length > 23 bits\n"); 3092 xdev->max_buffer_len = 3093 GENMASK(len_width - 1, 0); 3094 } 3095 } 3096 } 3097 3098 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 3099 xdev->has_axistream_connected = 3100 of_property_read_bool(node, "xlnx,axistream-connected"); 3101 } 3102 3103 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 3104 err = of_property_read_u32(node, "xlnx,num-fstores", 3105 &num_frames); 3106 if (err < 0) { 3107 dev_err(xdev->dev, 3108 "missing xlnx,num-fstores property\n"); 3109 goto disable_clks; 3110 } 3111 3112 err = of_property_read_u32(node, "xlnx,flush-fsync", 3113 &xdev->flush_on_fsync); 3114 if (err < 0) 3115 dev_warn(xdev->dev, 3116 "missing xlnx,flush-fsync property\n"); 3117 } 3118 3119 err = of_property_read_u32(node, "xlnx,addrwidth", &addr_width); 3120 if (err < 0) 3121 dev_warn(xdev->dev, "missing xlnx,addrwidth property\n"); 3122 3123 if (addr_width > 32) 3124 xdev->ext_addr = true; 3125 else 3126 xdev->ext_addr = false; 3127 3128 /* Set metadata mode */ 3129 if (xdev->has_axistream_connected) 3130 xdev->common.desc_metadata_modes = DESC_METADATA_ENGINE; 3131 3132 /* Set the dma mask bits */ 3133 err = dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width)); 3134 if (err < 0) { 3135 dev_err(xdev->dev, "DMA mask error %d\n", err); 3136 goto disable_clks; 3137 } 3138 3139 /* Initialize the DMA engine */ 3140 xdev->common.dev = &pdev->dev; 3141 3142 INIT_LIST_HEAD(&xdev->common.channels); 3143 if (!(xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) { 3144 dma_cap_set(DMA_SLAVE, xdev->common.cap_mask); 3145 dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask); 3146 } 3147 3148 xdev->common.device_alloc_chan_resources = 3149 xilinx_dma_alloc_chan_resources; 3150 xdev->common.device_free_chan_resources = 3151 xilinx_dma_free_chan_resources; 3152 xdev->common.device_terminate_all = xilinx_dma_terminate_all; 3153 xdev->common.device_synchronize = xilinx_dma_synchronize; 3154 xdev->common.device_tx_status = xilinx_dma_tx_status; 3155 xdev->common.device_issue_pending = xilinx_dma_issue_pending; 3156 xdev->common.device_config = xilinx_dma_device_config; 3157 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 3158 dma_cap_set(DMA_CYCLIC, xdev->common.cap_mask); 3159 xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg; 3160 xdev->common.device_prep_dma_cyclic = 3161 xilinx_dma_prep_dma_cyclic; 3162 /* Residue calculation is supported by only AXI DMA and CDMA */ 3163 xdev->common.residue_granularity = 3164 DMA_RESIDUE_GRANULARITY_SEGMENT; 3165 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 3166 dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask); 3167 xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy; 3168 /* Residue calculation is supported by only AXI DMA and CDMA */ 3169 xdev->common.residue_granularity = 3170 DMA_RESIDUE_GRANULARITY_SEGMENT; 3171 } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 3172 xdev->common.device_prep_slave_sg = xilinx_mcdma_prep_slave_sg; 3173 } else { 3174 xdev->common.device_prep_interleaved_dma = 3175 xilinx_vdma_dma_prep_interleaved; 3176 } 3177 3178 platform_set_drvdata(pdev, xdev); 3179 3180 /* Initialize the channels */ 3181 for_each_child_of_node(node, child) { 3182 err = xilinx_dma_child_probe(xdev, child); 3183 if (err < 0) { 3184 of_node_put(child); 3185 goto error; 3186 } 3187 } 3188 3189 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 3190 for (i = 0; i < xdev->dma_config->max_channels; i++) 3191 if (xdev->chan[i]) 3192 xdev->chan[i]->num_frms = num_frames; 3193 } 3194 3195 /* Register the DMA engine with the core */ 3196 err = dma_async_device_register(&xdev->common); 3197 if (err) { 3198 dev_err(xdev->dev, "failed to register the dma device\n"); 3199 goto error; 3200 } 3201 3202 err = of_dma_controller_register(node, of_dma_xilinx_xlate, 3203 xdev); 3204 if (err < 0) { 3205 dev_err(&pdev->dev, "Unable to register DMA to DT\n"); 3206 dma_async_device_unregister(&xdev->common); 3207 goto error; 3208 } 3209 3210 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) 3211 dev_info(&pdev->dev, "Xilinx AXI DMA Engine Driver Probed!!\n"); 3212 else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) 3213 dev_info(&pdev->dev, "Xilinx AXI CDMA Engine Driver Probed!!\n"); 3214 else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) 3215 dev_info(&pdev->dev, "Xilinx AXI MCDMA Engine Driver Probed!!\n"); 3216 else 3217 dev_info(&pdev->dev, "Xilinx AXI VDMA Engine Driver Probed!!\n"); 3218 3219 return 0; 3220 3221 error: 3222 for (i = 0; i < xdev->dma_config->max_channels; i++) 3223 if (xdev->chan[i]) 3224 xilinx_dma_chan_remove(xdev->chan[i]); 3225 disable_clks: 3226 xdma_disable_allclks(xdev); 3227 3228 return err; 3229 } 3230 3231 /** 3232 * xilinx_dma_remove - Driver remove function 3233 * @pdev: Pointer to the platform_device structure 3234 * 3235 * Return: Always '0' 3236 */ 3237 static int xilinx_dma_remove(struct platform_device *pdev) 3238 { 3239 struct xilinx_dma_device *xdev = platform_get_drvdata(pdev); 3240 int i; 3241 3242 of_dma_controller_free(pdev->dev.of_node); 3243 3244 dma_async_device_unregister(&xdev->common); 3245 3246 for (i = 0; i < xdev->dma_config->max_channels; i++) 3247 if (xdev->chan[i]) 3248 xilinx_dma_chan_remove(xdev->chan[i]); 3249 3250 xdma_disable_allclks(xdev); 3251 3252 return 0; 3253 } 3254 3255 static struct platform_driver xilinx_vdma_driver = { 3256 .driver = { 3257 .name = "xilinx-vdma", 3258 .of_match_table = xilinx_dma_of_ids, 3259 }, 3260 .probe = xilinx_dma_probe, 3261 .remove = xilinx_dma_remove, 3262 }; 3263 3264 module_platform_driver(xilinx_vdma_driver); 3265 3266 MODULE_AUTHOR("Xilinx, Inc."); 3267 MODULE_DESCRIPTION("Xilinx VDMA driver"); 3268 MODULE_LICENSE("GPL v2"); 3269