xref: /openbmc/linux/drivers/dma/ti/k3-psil-am64.c (revision cdd38c5f1ce4398ec58fec95904b75824daab7b5)
1*2329725dSPeter Ujfalusi // SPDX-License-Identifier: GPL-2.0
2*2329725dSPeter Ujfalusi /*
3*2329725dSPeter Ujfalusi  *  Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
4*2329725dSPeter Ujfalusi  *  Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
5*2329725dSPeter Ujfalusi  */
6*2329725dSPeter Ujfalusi 
7*2329725dSPeter Ujfalusi #include <linux/kernel.h>
8*2329725dSPeter Ujfalusi 
9*2329725dSPeter Ujfalusi #include "k3-psil-priv.h"
10*2329725dSPeter Ujfalusi 
11*2329725dSPeter Ujfalusi #define PSIL_PDMA_XY_TR(x)					\
12*2329725dSPeter Ujfalusi 	{							\
13*2329725dSPeter Ujfalusi 		.thread_id = x,					\
14*2329725dSPeter Ujfalusi 		.ep_config = {					\
15*2329725dSPeter Ujfalusi 			.ep_type = PSIL_EP_PDMA_XY,		\
16*2329725dSPeter Ujfalusi 			.mapped_channel_id = -1,		\
17*2329725dSPeter Ujfalusi 			.default_flow_id = -1,			\
18*2329725dSPeter Ujfalusi 		},						\
19*2329725dSPeter Ujfalusi 	}
20*2329725dSPeter Ujfalusi 
21*2329725dSPeter Ujfalusi #define PSIL_PDMA_XY_PKT(x)					\
22*2329725dSPeter Ujfalusi 	{							\
23*2329725dSPeter Ujfalusi 		.thread_id = x,					\
24*2329725dSPeter Ujfalusi 		.ep_config = {					\
25*2329725dSPeter Ujfalusi 			.ep_type = PSIL_EP_PDMA_XY,		\
26*2329725dSPeter Ujfalusi 			.mapped_channel_id = -1,		\
27*2329725dSPeter Ujfalusi 			.default_flow_id = -1,			\
28*2329725dSPeter Ujfalusi 			.pkt_mode = 1,				\
29*2329725dSPeter Ujfalusi 		},						\
30*2329725dSPeter Ujfalusi 	}
31*2329725dSPeter Ujfalusi 
32*2329725dSPeter Ujfalusi #define PSIL_ETHERNET(x, ch, flow_base, flow_cnt)		\
33*2329725dSPeter Ujfalusi 	{							\
34*2329725dSPeter Ujfalusi 		.thread_id = x,					\
35*2329725dSPeter Ujfalusi 		.ep_config = {					\
36*2329725dSPeter Ujfalusi 			.ep_type = PSIL_EP_NATIVE,		\
37*2329725dSPeter Ujfalusi 			.pkt_mode = 1,				\
38*2329725dSPeter Ujfalusi 			.needs_epib = 1,			\
39*2329725dSPeter Ujfalusi 			.psd_size = 16,				\
40*2329725dSPeter Ujfalusi 			.mapped_channel_id = ch,		\
41*2329725dSPeter Ujfalusi 			.flow_start = flow_base,		\
42*2329725dSPeter Ujfalusi 			.flow_num = flow_cnt,			\
43*2329725dSPeter Ujfalusi 			.default_flow_id = flow_base,		\
44*2329725dSPeter Ujfalusi 		},						\
45*2329725dSPeter Ujfalusi 	}
46*2329725dSPeter Ujfalusi 
47*2329725dSPeter Ujfalusi #define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx)	\
48*2329725dSPeter Ujfalusi 	{							\
49*2329725dSPeter Ujfalusi 		.thread_id = x,					\
50*2329725dSPeter Ujfalusi 		.ep_config = {					\
51*2329725dSPeter Ujfalusi 			.ep_type = PSIL_EP_NATIVE,		\
52*2329725dSPeter Ujfalusi 			.pkt_mode = 1,				\
53*2329725dSPeter Ujfalusi 			.needs_epib = 1,			\
54*2329725dSPeter Ujfalusi 			.psd_size = 64,				\
55*2329725dSPeter Ujfalusi 			.mapped_channel_id = ch,		\
56*2329725dSPeter Ujfalusi 			.flow_start = flow_base,		\
57*2329725dSPeter Ujfalusi 			.flow_num = flow_cnt,			\
58*2329725dSPeter Ujfalusi 			.default_flow_id = default_flow,	\
59*2329725dSPeter Ujfalusi 			.notdpkt = tx,				\
60*2329725dSPeter Ujfalusi 		},						\
61*2329725dSPeter Ujfalusi 	}
62*2329725dSPeter Ujfalusi 
63*2329725dSPeter Ujfalusi /* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
64*2329725dSPeter Ujfalusi static struct psil_ep am64_src_ep_map[] = {
65*2329725dSPeter Ujfalusi 	/* SAUL */
66*2329725dSPeter Ujfalusi 	PSIL_SAUL(0x4000, 17, 32, 8, 32, 0),
67*2329725dSPeter Ujfalusi 	PSIL_SAUL(0x4001, 18, 32, 8, 33, 0),
68*2329725dSPeter Ujfalusi 	PSIL_SAUL(0x4002, 19, 40, 8, 40, 0),
69*2329725dSPeter Ujfalusi 	PSIL_SAUL(0x4003, 20, 40, 8, 41, 0),
70*2329725dSPeter Ujfalusi 	/* ICSS_G0 */
71*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0x4100, 21, 48, 16),
72*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0x4101, 22, 64, 16),
73*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0x4102, 23, 80, 16),
74*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0x4103, 24, 96, 16),
75*2329725dSPeter Ujfalusi 	/* ICSS_G1 */
76*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0x4200, 25, 112, 16),
77*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0x4201, 26, 128, 16),
78*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0x4202, 27, 144, 16),
79*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0x4203, 28, 160, 16),
80*2329725dSPeter Ujfalusi 	/* PDMA_MAIN0 - SPI0-3 */
81*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x4300),
82*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x4301),
83*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x4302),
84*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x4303),
85*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x4304),
86*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x4305),
87*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x4306),
88*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x4307),
89*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x4308),
90*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x4309),
91*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x430a),
92*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x430b),
93*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x430c),
94*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x430d),
95*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x430e),
96*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x430f),
97*2329725dSPeter Ujfalusi 	/* PDMA_MAIN0 - USART0-1 */
98*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x4310),
99*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x4311),
100*2329725dSPeter Ujfalusi 	/* PDMA_MAIN1 - SPI4 */
101*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x4400),
102*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x4401),
103*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x4402),
104*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x4403),
105*2329725dSPeter Ujfalusi 	/* PDMA_MAIN1 - USART2-6 */
106*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x4404),
107*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x4405),
108*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x4406),
109*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x4407),
110*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_PKT(0x4408),
111*2329725dSPeter Ujfalusi 	/* PDMA_MAIN1 - ADCs */
112*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_TR(0x440f),
113*2329725dSPeter Ujfalusi 	PSIL_PDMA_XY_TR(0x4410),
114*2329725dSPeter Ujfalusi 	/* CPSW2 */
115*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0x4500, 16, 16, 16),
116*2329725dSPeter Ujfalusi };
117*2329725dSPeter Ujfalusi 
118*2329725dSPeter Ujfalusi /* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
119*2329725dSPeter Ujfalusi static struct psil_ep am64_dst_ep_map[] = {
120*2329725dSPeter Ujfalusi 	/* SAUL */
121*2329725dSPeter Ujfalusi 	PSIL_SAUL(0xc000, 24, 80, 8, 80, 1),
122*2329725dSPeter Ujfalusi 	PSIL_SAUL(0xc001, 25, 88, 8, 88, 1),
123*2329725dSPeter Ujfalusi 	/* ICSS_G0 */
124*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc100, 26, 96, 1),
125*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc101, 27, 97, 1),
126*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc102, 28, 98, 1),
127*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc103, 29, 99, 1),
128*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc104, 30, 100, 1),
129*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc105, 31, 101, 1),
130*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc106, 32, 102, 1),
131*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc107, 33, 103, 1),
132*2329725dSPeter Ujfalusi 	/* ICSS_G1 */
133*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc200, 34, 104, 1),
134*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc201, 35, 105, 1),
135*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc202, 36, 106, 1),
136*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc203, 37, 107, 1),
137*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc204, 38, 108, 1),
138*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc205, 39, 109, 1),
139*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc206, 40, 110, 1),
140*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc207, 41, 111, 1),
141*2329725dSPeter Ujfalusi 	/* CPSW2 */
142*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc500, 16, 16, 8),
143*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc501, 17, 24, 8),
144*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc502, 18, 32, 8),
145*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc503, 19, 40, 8),
146*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc504, 20, 48, 8),
147*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc505, 21, 56, 8),
148*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc506, 22, 64, 8),
149*2329725dSPeter Ujfalusi 	PSIL_ETHERNET(0xc507, 23, 72, 8),
150*2329725dSPeter Ujfalusi };
151*2329725dSPeter Ujfalusi 
152*2329725dSPeter Ujfalusi struct psil_ep_map am64_ep_map = {
153*2329725dSPeter Ujfalusi 	.name = "am64",
154*2329725dSPeter Ujfalusi 	.src = am64_src_ep_map,
155*2329725dSPeter Ujfalusi 	.src_count = ARRAY_SIZE(am64_src_ep_map),
156*2329725dSPeter Ujfalusi 	.dst = am64_dst_ep_map,
157*2329725dSPeter Ujfalusi 	.dst_count = ARRAY_SIZE(am64_dst_ep_map),
158*2329725dSPeter Ujfalusi };
159