1 /* 2 * drivers/dma/imx-sdma.c 3 * 4 * This file contains a driver for the Freescale Smart DMA engine 5 * 6 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 7 * 8 * Based on code from Freescale: 9 * 10 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. 11 * 12 * The code contained herein is licensed under the GNU General Public 13 * License. You may obtain a copy of the GNU General Public License 14 * Version 2 or later at the following locations: 15 * 16 * http://www.opensource.org/licenses/gpl-license.html 17 * http://www.gnu.org/copyleft/gpl.html 18 */ 19 20 #include <linux/init.h> 21 #include <linux/module.h> 22 #include <linux/types.h> 23 #include <linux/bitops.h> 24 #include <linux/mm.h> 25 #include <linux/interrupt.h> 26 #include <linux/clk.h> 27 #include <linux/delay.h> 28 #include <linux/sched.h> 29 #include <linux/semaphore.h> 30 #include <linux/spinlock.h> 31 #include <linux/device.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/firmware.h> 34 #include <linux/slab.h> 35 #include <linux/platform_device.h> 36 #include <linux/dmaengine.h> 37 #include <linux/of.h> 38 #include <linux/of_device.h> 39 #include <linux/of_dma.h> 40 41 #include <asm/irq.h> 42 #include <linux/platform_data/dma-imx-sdma.h> 43 #include <linux/platform_data/dma-imx.h> 44 45 #include "dmaengine.h" 46 47 /* SDMA registers */ 48 #define SDMA_H_C0PTR 0x000 49 #define SDMA_H_INTR 0x004 50 #define SDMA_H_STATSTOP 0x008 51 #define SDMA_H_START 0x00c 52 #define SDMA_H_EVTOVR 0x010 53 #define SDMA_H_DSPOVR 0x014 54 #define SDMA_H_HOSTOVR 0x018 55 #define SDMA_H_EVTPEND 0x01c 56 #define SDMA_H_DSPENBL 0x020 57 #define SDMA_H_RESET 0x024 58 #define SDMA_H_EVTERR 0x028 59 #define SDMA_H_INTRMSK 0x02c 60 #define SDMA_H_PSW 0x030 61 #define SDMA_H_EVTERRDBG 0x034 62 #define SDMA_H_CONFIG 0x038 63 #define SDMA_ONCE_ENB 0x040 64 #define SDMA_ONCE_DATA 0x044 65 #define SDMA_ONCE_INSTR 0x048 66 #define SDMA_ONCE_STAT 0x04c 67 #define SDMA_ONCE_CMD 0x050 68 #define SDMA_EVT_MIRROR 0x054 69 #define SDMA_ILLINSTADDR 0x058 70 #define SDMA_CHN0ADDR 0x05c 71 #define SDMA_ONCE_RTB 0x060 72 #define SDMA_XTRIG_CONF1 0x070 73 #define SDMA_XTRIG_CONF2 0x074 74 #define SDMA_CHNENBL0_IMX35 0x200 75 #define SDMA_CHNENBL0_IMX31 0x080 76 #define SDMA_CHNPRI_0 0x100 77 78 /* 79 * Buffer descriptor status values. 80 */ 81 #define BD_DONE 0x01 82 #define BD_WRAP 0x02 83 #define BD_CONT 0x04 84 #define BD_INTR 0x08 85 #define BD_RROR 0x10 86 #define BD_LAST 0x20 87 #define BD_EXTD 0x80 88 89 /* 90 * Data Node descriptor status values. 91 */ 92 #define DND_END_OF_FRAME 0x80 93 #define DND_END_OF_XFER 0x40 94 #define DND_DONE 0x20 95 #define DND_UNUSED 0x01 96 97 /* 98 * IPCV2 descriptor status values. 99 */ 100 #define BD_IPCV2_END_OF_FRAME 0x40 101 102 #define IPCV2_MAX_NODES 50 103 /* 104 * Error bit set in the CCB status field by the SDMA, 105 * in setbd routine, in case of a transfer error 106 */ 107 #define DATA_ERROR 0x10000000 108 109 /* 110 * Buffer descriptor commands. 111 */ 112 #define C0_ADDR 0x01 113 #define C0_LOAD 0x02 114 #define C0_DUMP 0x03 115 #define C0_SETCTX 0x07 116 #define C0_GETCTX 0x03 117 #define C0_SETDM 0x01 118 #define C0_SETPM 0x04 119 #define C0_GETDM 0x02 120 #define C0_GETPM 0x08 121 /* 122 * Change endianness indicator in the BD command field 123 */ 124 #define CHANGE_ENDIANNESS 0x80 125 126 /* 127 * Mode/Count of data node descriptors - IPCv2 128 */ 129 struct sdma_mode_count { 130 u32 count : 16; /* size of the buffer pointed by this BD */ 131 u32 status : 8; /* E,R,I,C,W,D status bits stored here */ 132 u32 command : 8; /* command mostlky used for channel 0 */ 133 }; 134 135 /* 136 * Buffer descriptor 137 */ 138 struct sdma_buffer_descriptor { 139 struct sdma_mode_count mode; 140 u32 buffer_addr; /* address of the buffer described */ 141 u32 ext_buffer_addr; /* extended buffer address */ 142 } __attribute__ ((packed)); 143 144 /** 145 * struct sdma_channel_control - Channel control Block 146 * 147 * @current_bd_ptr current buffer descriptor processed 148 * @base_bd_ptr first element of buffer descriptor array 149 * @unused padding. The SDMA engine expects an array of 128 byte 150 * control blocks 151 */ 152 struct sdma_channel_control { 153 u32 current_bd_ptr; 154 u32 base_bd_ptr; 155 u32 unused[2]; 156 } __attribute__ ((packed)); 157 158 /** 159 * struct sdma_state_registers - SDMA context for a channel 160 * 161 * @pc: program counter 162 * @t: test bit: status of arithmetic & test instruction 163 * @rpc: return program counter 164 * @sf: source fault while loading data 165 * @spc: loop start program counter 166 * @df: destination fault while storing data 167 * @epc: loop end program counter 168 * @lm: loop mode 169 */ 170 struct sdma_state_registers { 171 u32 pc :14; 172 u32 unused1: 1; 173 u32 t : 1; 174 u32 rpc :14; 175 u32 unused0: 1; 176 u32 sf : 1; 177 u32 spc :14; 178 u32 unused2: 1; 179 u32 df : 1; 180 u32 epc :14; 181 u32 lm : 2; 182 } __attribute__ ((packed)); 183 184 /** 185 * struct sdma_context_data - sdma context specific to a channel 186 * 187 * @channel_state: channel state bits 188 * @gReg: general registers 189 * @mda: burst dma destination address register 190 * @msa: burst dma source address register 191 * @ms: burst dma status register 192 * @md: burst dma data register 193 * @pda: peripheral dma destination address register 194 * @psa: peripheral dma source address register 195 * @ps: peripheral dma status register 196 * @pd: peripheral dma data register 197 * @ca: CRC polynomial register 198 * @cs: CRC accumulator register 199 * @dda: dedicated core destination address register 200 * @dsa: dedicated core source address register 201 * @ds: dedicated core status register 202 * @dd: dedicated core data register 203 */ 204 struct sdma_context_data { 205 struct sdma_state_registers channel_state; 206 u32 gReg[8]; 207 u32 mda; 208 u32 msa; 209 u32 ms; 210 u32 md; 211 u32 pda; 212 u32 psa; 213 u32 ps; 214 u32 pd; 215 u32 ca; 216 u32 cs; 217 u32 dda; 218 u32 dsa; 219 u32 ds; 220 u32 dd; 221 u32 scratch0; 222 u32 scratch1; 223 u32 scratch2; 224 u32 scratch3; 225 u32 scratch4; 226 u32 scratch5; 227 u32 scratch6; 228 u32 scratch7; 229 } __attribute__ ((packed)); 230 231 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor)) 232 233 struct sdma_engine; 234 235 /** 236 * struct sdma_channel - housekeeping for a SDMA channel 237 * 238 * @sdma pointer to the SDMA engine for this channel 239 * @channel the channel number, matches dmaengine chan_id + 1 240 * @direction transfer type. Needed for setting SDMA script 241 * @peripheral_type Peripheral type. Needed for setting SDMA script 242 * @event_id0 aka dma request line 243 * @event_id1 for channels that use 2 events 244 * @word_size peripheral access size 245 * @buf_tail ID of the buffer that was processed 246 * @num_bd max NUM_BD. number of descriptors currently handling 247 */ 248 struct sdma_channel { 249 struct sdma_engine *sdma; 250 unsigned int channel; 251 enum dma_transfer_direction direction; 252 enum sdma_peripheral_type peripheral_type; 253 unsigned int event_id0; 254 unsigned int event_id1; 255 enum dma_slave_buswidth word_size; 256 unsigned int buf_tail; 257 unsigned int num_bd; 258 struct sdma_buffer_descriptor *bd; 259 dma_addr_t bd_phys; 260 unsigned int pc_from_device, pc_to_device; 261 unsigned long flags; 262 dma_addr_t per_address; 263 unsigned long event_mask[2]; 264 unsigned long watermark_level; 265 u32 shp_addr, per_addr; 266 struct dma_chan chan; 267 spinlock_t lock; 268 struct dma_async_tx_descriptor desc; 269 enum dma_status status; 270 unsigned int chn_count; 271 unsigned int chn_real_count; 272 struct tasklet_struct tasklet; 273 }; 274 275 #define IMX_DMA_SG_LOOP BIT(0) 276 277 #define MAX_DMA_CHANNELS 32 278 #define MXC_SDMA_DEFAULT_PRIORITY 1 279 #define MXC_SDMA_MIN_PRIORITY 1 280 #define MXC_SDMA_MAX_PRIORITY 7 281 282 #define SDMA_FIRMWARE_MAGIC 0x414d4453 283 284 /** 285 * struct sdma_firmware_header - Layout of the firmware image 286 * 287 * @magic "SDMA" 288 * @version_major increased whenever layout of struct sdma_script_start_addrs 289 * changes. 290 * @version_minor firmware minor version (for binary compatible changes) 291 * @script_addrs_start offset of struct sdma_script_start_addrs in this image 292 * @num_script_addrs Number of script addresses in this image 293 * @ram_code_start offset of SDMA ram image in this firmware image 294 * @ram_code_size size of SDMA ram image 295 * @script_addrs Stores the start address of the SDMA scripts 296 * (in SDMA memory space) 297 */ 298 struct sdma_firmware_header { 299 u32 magic; 300 u32 version_major; 301 u32 version_minor; 302 u32 script_addrs_start; 303 u32 num_script_addrs; 304 u32 ram_code_start; 305 u32 ram_code_size; 306 }; 307 308 struct sdma_driver_data { 309 int chnenbl0; 310 int num_events; 311 struct sdma_script_start_addrs *script_addrs; 312 }; 313 314 struct sdma_engine { 315 struct device *dev; 316 struct device_dma_parameters dma_parms; 317 struct sdma_channel channel[MAX_DMA_CHANNELS]; 318 struct sdma_channel_control *channel_control; 319 void __iomem *regs; 320 struct sdma_context_data *context; 321 dma_addr_t context_phys; 322 struct dma_device dma_device; 323 struct clk *clk_ipg; 324 struct clk *clk_ahb; 325 spinlock_t channel_0_lock; 326 u32 script_number; 327 struct sdma_script_start_addrs *script_addrs; 328 const struct sdma_driver_data *drvdata; 329 }; 330 331 static struct sdma_driver_data sdma_imx31 = { 332 .chnenbl0 = SDMA_CHNENBL0_IMX31, 333 .num_events = 32, 334 }; 335 336 static struct sdma_script_start_addrs sdma_script_imx25 = { 337 .ap_2_ap_addr = 729, 338 .uart_2_mcu_addr = 904, 339 .per_2_app_addr = 1255, 340 .mcu_2_app_addr = 834, 341 .uartsh_2_mcu_addr = 1120, 342 .per_2_shp_addr = 1329, 343 .mcu_2_shp_addr = 1048, 344 .ata_2_mcu_addr = 1560, 345 .mcu_2_ata_addr = 1479, 346 .app_2_per_addr = 1189, 347 .app_2_mcu_addr = 770, 348 .shp_2_per_addr = 1407, 349 .shp_2_mcu_addr = 979, 350 }; 351 352 static struct sdma_driver_data sdma_imx25 = { 353 .chnenbl0 = SDMA_CHNENBL0_IMX35, 354 .num_events = 48, 355 .script_addrs = &sdma_script_imx25, 356 }; 357 358 static struct sdma_driver_data sdma_imx35 = { 359 .chnenbl0 = SDMA_CHNENBL0_IMX35, 360 .num_events = 48, 361 }; 362 363 static struct sdma_script_start_addrs sdma_script_imx51 = { 364 .ap_2_ap_addr = 642, 365 .uart_2_mcu_addr = 817, 366 .mcu_2_app_addr = 747, 367 .mcu_2_shp_addr = 961, 368 .ata_2_mcu_addr = 1473, 369 .mcu_2_ata_addr = 1392, 370 .app_2_per_addr = 1033, 371 .app_2_mcu_addr = 683, 372 .shp_2_per_addr = 1251, 373 .shp_2_mcu_addr = 892, 374 }; 375 376 static struct sdma_driver_data sdma_imx51 = { 377 .chnenbl0 = SDMA_CHNENBL0_IMX35, 378 .num_events = 48, 379 .script_addrs = &sdma_script_imx51, 380 }; 381 382 static struct sdma_script_start_addrs sdma_script_imx53 = { 383 .ap_2_ap_addr = 642, 384 .app_2_mcu_addr = 683, 385 .mcu_2_app_addr = 747, 386 .uart_2_mcu_addr = 817, 387 .shp_2_mcu_addr = 891, 388 .mcu_2_shp_addr = 960, 389 .uartsh_2_mcu_addr = 1032, 390 .spdif_2_mcu_addr = 1100, 391 .mcu_2_spdif_addr = 1134, 392 .firi_2_mcu_addr = 1193, 393 .mcu_2_firi_addr = 1290, 394 }; 395 396 static struct sdma_driver_data sdma_imx53 = { 397 .chnenbl0 = SDMA_CHNENBL0_IMX35, 398 .num_events = 48, 399 .script_addrs = &sdma_script_imx53, 400 }; 401 402 static struct sdma_script_start_addrs sdma_script_imx6q = { 403 .ap_2_ap_addr = 642, 404 .uart_2_mcu_addr = 817, 405 .mcu_2_app_addr = 747, 406 .per_2_per_addr = 6331, 407 .uartsh_2_mcu_addr = 1032, 408 .mcu_2_shp_addr = 960, 409 .app_2_mcu_addr = 683, 410 .shp_2_mcu_addr = 891, 411 .spdif_2_mcu_addr = 1100, 412 .mcu_2_spdif_addr = 1134, 413 }; 414 415 static struct sdma_driver_data sdma_imx6q = { 416 .chnenbl0 = SDMA_CHNENBL0_IMX35, 417 .num_events = 48, 418 .script_addrs = &sdma_script_imx6q, 419 }; 420 421 static struct platform_device_id sdma_devtypes[] = { 422 { 423 .name = "imx25-sdma", 424 .driver_data = (unsigned long)&sdma_imx25, 425 }, { 426 .name = "imx31-sdma", 427 .driver_data = (unsigned long)&sdma_imx31, 428 }, { 429 .name = "imx35-sdma", 430 .driver_data = (unsigned long)&sdma_imx35, 431 }, { 432 .name = "imx51-sdma", 433 .driver_data = (unsigned long)&sdma_imx51, 434 }, { 435 .name = "imx53-sdma", 436 .driver_data = (unsigned long)&sdma_imx53, 437 }, { 438 .name = "imx6q-sdma", 439 .driver_data = (unsigned long)&sdma_imx6q, 440 }, { 441 /* sentinel */ 442 } 443 }; 444 MODULE_DEVICE_TABLE(platform, sdma_devtypes); 445 446 static const struct of_device_id sdma_dt_ids[] = { 447 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, }, 448 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, }, 449 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, }, 450 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, }, 451 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, }, 452 { /* sentinel */ } 453 }; 454 MODULE_DEVICE_TABLE(of, sdma_dt_ids); 455 456 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */ 457 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */ 458 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */ 459 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/ 460 461 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event) 462 { 463 u32 chnenbl0 = sdma->drvdata->chnenbl0; 464 return chnenbl0 + event * 4; 465 } 466 467 static int sdma_config_ownership(struct sdma_channel *sdmac, 468 bool event_override, bool mcu_override, bool dsp_override) 469 { 470 struct sdma_engine *sdma = sdmac->sdma; 471 int channel = sdmac->channel; 472 unsigned long evt, mcu, dsp; 473 474 if (event_override && mcu_override && dsp_override) 475 return -EINVAL; 476 477 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); 478 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); 479 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); 480 481 if (dsp_override) 482 __clear_bit(channel, &dsp); 483 else 484 __set_bit(channel, &dsp); 485 486 if (event_override) 487 __clear_bit(channel, &evt); 488 else 489 __set_bit(channel, &evt); 490 491 if (mcu_override) 492 __clear_bit(channel, &mcu); 493 else 494 __set_bit(channel, &mcu); 495 496 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); 497 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); 498 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); 499 500 return 0; 501 } 502 503 static void sdma_enable_channel(struct sdma_engine *sdma, int channel) 504 { 505 writel(BIT(channel), sdma->regs + SDMA_H_START); 506 } 507 508 /* 509 * sdma_run_channel0 - run a channel and wait till it's done 510 */ 511 static int sdma_run_channel0(struct sdma_engine *sdma) 512 { 513 int ret; 514 unsigned long timeout = 500; 515 516 sdma_enable_channel(sdma, 0); 517 518 while (!(ret = readl_relaxed(sdma->regs + SDMA_H_INTR) & 1)) { 519 if (timeout-- <= 0) 520 break; 521 udelay(1); 522 } 523 524 if (ret) { 525 /* Clear the interrupt status */ 526 writel_relaxed(ret, sdma->regs + SDMA_H_INTR); 527 } else { 528 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); 529 } 530 531 return ret ? 0 : -ETIMEDOUT; 532 } 533 534 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, 535 u32 address) 536 { 537 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; 538 void *buf_virt; 539 dma_addr_t buf_phys; 540 int ret; 541 unsigned long flags; 542 543 buf_virt = dma_alloc_coherent(NULL, 544 size, 545 &buf_phys, GFP_KERNEL); 546 if (!buf_virt) { 547 return -ENOMEM; 548 } 549 550 spin_lock_irqsave(&sdma->channel_0_lock, flags); 551 552 bd0->mode.command = C0_SETPM; 553 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; 554 bd0->mode.count = size / 2; 555 bd0->buffer_addr = buf_phys; 556 bd0->ext_buffer_addr = address; 557 558 memcpy(buf_virt, buf, size); 559 560 ret = sdma_run_channel0(sdma); 561 562 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); 563 564 dma_free_coherent(NULL, size, buf_virt, buf_phys); 565 566 return ret; 567 } 568 569 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event) 570 { 571 struct sdma_engine *sdma = sdmac->sdma; 572 int channel = sdmac->channel; 573 unsigned long val; 574 u32 chnenbl = chnenbl_ofs(sdma, event); 575 576 val = readl_relaxed(sdma->regs + chnenbl); 577 __set_bit(channel, &val); 578 writel_relaxed(val, sdma->regs + chnenbl); 579 } 580 581 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) 582 { 583 struct sdma_engine *sdma = sdmac->sdma; 584 int channel = sdmac->channel; 585 u32 chnenbl = chnenbl_ofs(sdma, event); 586 unsigned long val; 587 588 val = readl_relaxed(sdma->regs + chnenbl); 589 __clear_bit(channel, &val); 590 writel_relaxed(val, sdma->regs + chnenbl); 591 } 592 593 static void sdma_handle_channel_loop(struct sdma_channel *sdmac) 594 { 595 struct sdma_buffer_descriptor *bd; 596 597 /* 598 * loop mode. Iterate over descriptors, re-setup them and 599 * call callback function. 600 */ 601 while (1) { 602 bd = &sdmac->bd[sdmac->buf_tail]; 603 604 if (bd->mode.status & BD_DONE) 605 break; 606 607 if (bd->mode.status & BD_RROR) 608 sdmac->status = DMA_ERROR; 609 else 610 sdmac->status = DMA_IN_PROGRESS; 611 612 bd->mode.status |= BD_DONE; 613 sdmac->buf_tail++; 614 sdmac->buf_tail %= sdmac->num_bd; 615 616 if (sdmac->desc.callback) 617 sdmac->desc.callback(sdmac->desc.callback_param); 618 } 619 } 620 621 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac) 622 { 623 struct sdma_buffer_descriptor *bd; 624 int i, error = 0; 625 626 sdmac->chn_real_count = 0; 627 /* 628 * non loop mode. Iterate over all descriptors, collect 629 * errors and call callback function 630 */ 631 for (i = 0; i < sdmac->num_bd; i++) { 632 bd = &sdmac->bd[i]; 633 634 if (bd->mode.status & (BD_DONE | BD_RROR)) 635 error = -EIO; 636 sdmac->chn_real_count += bd->mode.count; 637 } 638 639 if (error) 640 sdmac->status = DMA_ERROR; 641 else 642 sdmac->status = DMA_COMPLETE; 643 644 dma_cookie_complete(&sdmac->desc); 645 if (sdmac->desc.callback) 646 sdmac->desc.callback(sdmac->desc.callback_param); 647 } 648 649 static void sdma_tasklet(unsigned long data) 650 { 651 struct sdma_channel *sdmac = (struct sdma_channel *) data; 652 653 if (sdmac->flags & IMX_DMA_SG_LOOP) 654 sdma_handle_channel_loop(sdmac); 655 else 656 mxc_sdma_handle_channel_normal(sdmac); 657 } 658 659 static irqreturn_t sdma_int_handler(int irq, void *dev_id) 660 { 661 struct sdma_engine *sdma = dev_id; 662 unsigned long stat; 663 664 stat = readl_relaxed(sdma->regs + SDMA_H_INTR); 665 /* not interested in channel 0 interrupts */ 666 stat &= ~1; 667 writel_relaxed(stat, sdma->regs + SDMA_H_INTR); 668 669 while (stat) { 670 int channel = fls(stat) - 1; 671 struct sdma_channel *sdmac = &sdma->channel[channel]; 672 673 tasklet_schedule(&sdmac->tasklet); 674 675 __clear_bit(channel, &stat); 676 } 677 678 return IRQ_HANDLED; 679 } 680 681 /* 682 * sets the pc of SDMA script according to the peripheral type 683 */ 684 static void sdma_get_pc(struct sdma_channel *sdmac, 685 enum sdma_peripheral_type peripheral_type) 686 { 687 struct sdma_engine *sdma = sdmac->sdma; 688 int per_2_emi = 0, emi_2_per = 0; 689 /* 690 * These are needed once we start to support transfers between 691 * two peripherals or memory-to-memory transfers 692 */ 693 int per_2_per = 0, emi_2_emi = 0; 694 695 sdmac->pc_from_device = 0; 696 sdmac->pc_to_device = 0; 697 698 switch (peripheral_type) { 699 case IMX_DMATYPE_MEMORY: 700 emi_2_emi = sdma->script_addrs->ap_2_ap_addr; 701 break; 702 case IMX_DMATYPE_DSP: 703 emi_2_per = sdma->script_addrs->bp_2_ap_addr; 704 per_2_emi = sdma->script_addrs->ap_2_bp_addr; 705 break; 706 case IMX_DMATYPE_FIRI: 707 per_2_emi = sdma->script_addrs->firi_2_mcu_addr; 708 emi_2_per = sdma->script_addrs->mcu_2_firi_addr; 709 break; 710 case IMX_DMATYPE_UART: 711 per_2_emi = sdma->script_addrs->uart_2_mcu_addr; 712 emi_2_per = sdma->script_addrs->mcu_2_app_addr; 713 break; 714 case IMX_DMATYPE_UART_SP: 715 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; 716 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; 717 break; 718 case IMX_DMATYPE_ATA: 719 per_2_emi = sdma->script_addrs->ata_2_mcu_addr; 720 emi_2_per = sdma->script_addrs->mcu_2_ata_addr; 721 break; 722 case IMX_DMATYPE_CSPI: 723 case IMX_DMATYPE_EXT: 724 case IMX_DMATYPE_SSI: 725 per_2_emi = sdma->script_addrs->app_2_mcu_addr; 726 emi_2_per = sdma->script_addrs->mcu_2_app_addr; 727 break; 728 case IMX_DMATYPE_SSI_SP: 729 case IMX_DMATYPE_MMC: 730 case IMX_DMATYPE_SDHC: 731 case IMX_DMATYPE_CSPI_SP: 732 case IMX_DMATYPE_ESAI: 733 case IMX_DMATYPE_MSHC_SP: 734 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; 735 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; 736 break; 737 case IMX_DMATYPE_ASRC: 738 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; 739 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; 740 per_2_per = sdma->script_addrs->per_2_per_addr; 741 break; 742 case IMX_DMATYPE_MSHC: 743 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; 744 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; 745 break; 746 case IMX_DMATYPE_CCM: 747 per_2_emi = sdma->script_addrs->dptc_dvfs_addr; 748 break; 749 case IMX_DMATYPE_SPDIF: 750 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; 751 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; 752 break; 753 case IMX_DMATYPE_IPU_MEMORY: 754 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; 755 break; 756 default: 757 break; 758 } 759 760 sdmac->pc_from_device = per_2_emi; 761 sdmac->pc_to_device = emi_2_per; 762 } 763 764 static int sdma_load_context(struct sdma_channel *sdmac) 765 { 766 struct sdma_engine *sdma = sdmac->sdma; 767 int channel = sdmac->channel; 768 int load_address; 769 struct sdma_context_data *context = sdma->context; 770 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; 771 int ret; 772 unsigned long flags; 773 774 if (sdmac->direction == DMA_DEV_TO_MEM) { 775 load_address = sdmac->pc_from_device; 776 } else { 777 load_address = sdmac->pc_to_device; 778 } 779 780 if (load_address < 0) 781 return load_address; 782 783 dev_dbg(sdma->dev, "load_address = %d\n", load_address); 784 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); 785 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); 786 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); 787 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); 788 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); 789 790 spin_lock_irqsave(&sdma->channel_0_lock, flags); 791 792 memset(context, 0, sizeof(*context)); 793 context->channel_state.pc = load_address; 794 795 /* Send by context the event mask,base address for peripheral 796 * and watermark level 797 */ 798 context->gReg[0] = sdmac->event_mask[1]; 799 context->gReg[1] = sdmac->event_mask[0]; 800 context->gReg[2] = sdmac->per_addr; 801 context->gReg[6] = sdmac->shp_addr; 802 context->gReg[7] = sdmac->watermark_level; 803 804 bd0->mode.command = C0_SETDM; 805 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; 806 bd0->mode.count = sizeof(*context) / 4; 807 bd0->buffer_addr = sdma->context_phys; 808 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; 809 ret = sdma_run_channel0(sdma); 810 811 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); 812 813 return ret; 814 } 815 816 static void sdma_disable_channel(struct sdma_channel *sdmac) 817 { 818 struct sdma_engine *sdma = sdmac->sdma; 819 int channel = sdmac->channel; 820 821 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); 822 sdmac->status = DMA_ERROR; 823 } 824 825 static int sdma_config_channel(struct sdma_channel *sdmac) 826 { 827 int ret; 828 829 sdma_disable_channel(sdmac); 830 831 sdmac->event_mask[0] = 0; 832 sdmac->event_mask[1] = 0; 833 sdmac->shp_addr = 0; 834 sdmac->per_addr = 0; 835 836 if (sdmac->event_id0) { 837 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) 838 return -EINVAL; 839 sdma_event_enable(sdmac, sdmac->event_id0); 840 } 841 842 switch (sdmac->peripheral_type) { 843 case IMX_DMATYPE_DSP: 844 sdma_config_ownership(sdmac, false, true, true); 845 break; 846 case IMX_DMATYPE_MEMORY: 847 sdma_config_ownership(sdmac, false, true, false); 848 break; 849 default: 850 sdma_config_ownership(sdmac, true, true, false); 851 break; 852 } 853 854 sdma_get_pc(sdmac, sdmac->peripheral_type); 855 856 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && 857 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { 858 /* Handle multiple event channels differently */ 859 if (sdmac->event_id1) { 860 sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32); 861 if (sdmac->event_id1 > 31) 862 __set_bit(31, &sdmac->watermark_level); 863 sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32); 864 if (sdmac->event_id0 > 31) 865 __set_bit(30, &sdmac->watermark_level); 866 } else { 867 __set_bit(sdmac->event_id0, sdmac->event_mask); 868 } 869 /* Watermark Level */ 870 sdmac->watermark_level |= sdmac->watermark_level; 871 /* Address */ 872 sdmac->shp_addr = sdmac->per_address; 873 } else { 874 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ 875 } 876 877 ret = sdma_load_context(sdmac); 878 879 return ret; 880 } 881 882 static int sdma_set_channel_priority(struct sdma_channel *sdmac, 883 unsigned int priority) 884 { 885 struct sdma_engine *sdma = sdmac->sdma; 886 int channel = sdmac->channel; 887 888 if (priority < MXC_SDMA_MIN_PRIORITY 889 || priority > MXC_SDMA_MAX_PRIORITY) { 890 return -EINVAL; 891 } 892 893 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); 894 895 return 0; 896 } 897 898 static int sdma_request_channel(struct sdma_channel *sdmac) 899 { 900 struct sdma_engine *sdma = sdmac->sdma; 901 int channel = sdmac->channel; 902 int ret = -EBUSY; 903 904 sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL); 905 if (!sdmac->bd) { 906 ret = -ENOMEM; 907 goto out; 908 } 909 910 memset(sdmac->bd, 0, PAGE_SIZE); 911 912 sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys; 913 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; 914 915 sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY); 916 return 0; 917 out: 918 919 return ret; 920 } 921 922 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan) 923 { 924 return container_of(chan, struct sdma_channel, chan); 925 } 926 927 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx) 928 { 929 unsigned long flags; 930 struct sdma_channel *sdmac = to_sdma_chan(tx->chan); 931 dma_cookie_t cookie; 932 933 spin_lock_irqsave(&sdmac->lock, flags); 934 935 cookie = dma_cookie_assign(tx); 936 937 spin_unlock_irqrestore(&sdmac->lock, flags); 938 939 return cookie; 940 } 941 942 static int sdma_alloc_chan_resources(struct dma_chan *chan) 943 { 944 struct sdma_channel *sdmac = to_sdma_chan(chan); 945 struct imx_dma_data *data = chan->private; 946 int prio, ret; 947 948 if (!data) 949 return -EINVAL; 950 951 switch (data->priority) { 952 case DMA_PRIO_HIGH: 953 prio = 3; 954 break; 955 case DMA_PRIO_MEDIUM: 956 prio = 2; 957 break; 958 case DMA_PRIO_LOW: 959 default: 960 prio = 1; 961 break; 962 } 963 964 sdmac->peripheral_type = data->peripheral_type; 965 sdmac->event_id0 = data->dma_request; 966 967 clk_enable(sdmac->sdma->clk_ipg); 968 clk_enable(sdmac->sdma->clk_ahb); 969 970 ret = sdma_request_channel(sdmac); 971 if (ret) 972 return ret; 973 974 ret = sdma_set_channel_priority(sdmac, prio); 975 if (ret) 976 return ret; 977 978 dma_async_tx_descriptor_init(&sdmac->desc, chan); 979 sdmac->desc.tx_submit = sdma_tx_submit; 980 /* txd.flags will be overwritten in prep funcs */ 981 sdmac->desc.flags = DMA_CTRL_ACK; 982 983 return 0; 984 } 985 986 static void sdma_free_chan_resources(struct dma_chan *chan) 987 { 988 struct sdma_channel *sdmac = to_sdma_chan(chan); 989 struct sdma_engine *sdma = sdmac->sdma; 990 991 sdma_disable_channel(sdmac); 992 993 if (sdmac->event_id0) 994 sdma_event_disable(sdmac, sdmac->event_id0); 995 if (sdmac->event_id1) 996 sdma_event_disable(sdmac, sdmac->event_id1); 997 998 sdmac->event_id0 = 0; 999 sdmac->event_id1 = 0; 1000 1001 sdma_set_channel_priority(sdmac, 0); 1002 1003 dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys); 1004 1005 clk_disable(sdma->clk_ipg); 1006 clk_disable(sdma->clk_ahb); 1007 } 1008 1009 static struct dma_async_tx_descriptor *sdma_prep_slave_sg( 1010 struct dma_chan *chan, struct scatterlist *sgl, 1011 unsigned int sg_len, enum dma_transfer_direction direction, 1012 unsigned long flags, void *context) 1013 { 1014 struct sdma_channel *sdmac = to_sdma_chan(chan); 1015 struct sdma_engine *sdma = sdmac->sdma; 1016 int ret, i, count; 1017 int channel = sdmac->channel; 1018 struct scatterlist *sg; 1019 1020 if (sdmac->status == DMA_IN_PROGRESS) 1021 return NULL; 1022 sdmac->status = DMA_IN_PROGRESS; 1023 1024 sdmac->flags = 0; 1025 1026 sdmac->buf_tail = 0; 1027 1028 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", 1029 sg_len, channel); 1030 1031 sdmac->direction = direction; 1032 ret = sdma_load_context(sdmac); 1033 if (ret) 1034 goto err_out; 1035 1036 if (sg_len > NUM_BD) { 1037 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", 1038 channel, sg_len, NUM_BD); 1039 ret = -EINVAL; 1040 goto err_out; 1041 } 1042 1043 sdmac->chn_count = 0; 1044 for_each_sg(sgl, sg, sg_len, i) { 1045 struct sdma_buffer_descriptor *bd = &sdmac->bd[i]; 1046 int param; 1047 1048 bd->buffer_addr = sg->dma_address; 1049 1050 count = sg_dma_len(sg); 1051 1052 if (count > 0xffff) { 1053 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", 1054 channel, count, 0xffff); 1055 ret = -EINVAL; 1056 goto err_out; 1057 } 1058 1059 bd->mode.count = count; 1060 sdmac->chn_count += count; 1061 1062 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) { 1063 ret = -EINVAL; 1064 goto err_out; 1065 } 1066 1067 switch (sdmac->word_size) { 1068 case DMA_SLAVE_BUSWIDTH_4_BYTES: 1069 bd->mode.command = 0; 1070 if (count & 3 || sg->dma_address & 3) 1071 return NULL; 1072 break; 1073 case DMA_SLAVE_BUSWIDTH_2_BYTES: 1074 bd->mode.command = 2; 1075 if (count & 1 || sg->dma_address & 1) 1076 return NULL; 1077 break; 1078 case DMA_SLAVE_BUSWIDTH_1_BYTE: 1079 bd->mode.command = 1; 1080 break; 1081 default: 1082 return NULL; 1083 } 1084 1085 param = BD_DONE | BD_EXTD | BD_CONT; 1086 1087 if (i + 1 == sg_len) { 1088 param |= BD_INTR; 1089 param |= BD_LAST; 1090 param &= ~BD_CONT; 1091 } 1092 1093 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", 1094 i, count, (u64)sg->dma_address, 1095 param & BD_WRAP ? "wrap" : "", 1096 param & BD_INTR ? " intr" : ""); 1097 1098 bd->mode.status = param; 1099 } 1100 1101 sdmac->num_bd = sg_len; 1102 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; 1103 1104 return &sdmac->desc; 1105 err_out: 1106 sdmac->status = DMA_ERROR; 1107 return NULL; 1108 } 1109 1110 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( 1111 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 1112 size_t period_len, enum dma_transfer_direction direction, 1113 unsigned long flags, void *context) 1114 { 1115 struct sdma_channel *sdmac = to_sdma_chan(chan); 1116 struct sdma_engine *sdma = sdmac->sdma; 1117 int num_periods = buf_len / period_len; 1118 int channel = sdmac->channel; 1119 int ret, i = 0, buf = 0; 1120 1121 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); 1122 1123 if (sdmac->status == DMA_IN_PROGRESS) 1124 return NULL; 1125 1126 sdmac->status = DMA_IN_PROGRESS; 1127 1128 sdmac->buf_tail = 0; 1129 1130 sdmac->flags |= IMX_DMA_SG_LOOP; 1131 sdmac->direction = direction; 1132 ret = sdma_load_context(sdmac); 1133 if (ret) 1134 goto err_out; 1135 1136 if (num_periods > NUM_BD) { 1137 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", 1138 channel, num_periods, NUM_BD); 1139 goto err_out; 1140 } 1141 1142 if (period_len > 0xffff) { 1143 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n", 1144 channel, period_len, 0xffff); 1145 goto err_out; 1146 } 1147 1148 while (buf < buf_len) { 1149 struct sdma_buffer_descriptor *bd = &sdmac->bd[i]; 1150 int param; 1151 1152 bd->buffer_addr = dma_addr; 1153 1154 bd->mode.count = period_len; 1155 1156 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) 1157 goto err_out; 1158 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) 1159 bd->mode.command = 0; 1160 else 1161 bd->mode.command = sdmac->word_size; 1162 1163 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR; 1164 if (i + 1 == num_periods) 1165 param |= BD_WRAP; 1166 1167 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", 1168 i, period_len, (u64)dma_addr, 1169 param & BD_WRAP ? "wrap" : "", 1170 param & BD_INTR ? " intr" : ""); 1171 1172 bd->mode.status = param; 1173 1174 dma_addr += period_len; 1175 buf += period_len; 1176 1177 i++; 1178 } 1179 1180 sdmac->num_bd = num_periods; 1181 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; 1182 1183 return &sdmac->desc; 1184 err_out: 1185 sdmac->status = DMA_ERROR; 1186 return NULL; 1187 } 1188 1189 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 1190 unsigned long arg) 1191 { 1192 struct sdma_channel *sdmac = to_sdma_chan(chan); 1193 struct dma_slave_config *dmaengine_cfg = (void *)arg; 1194 1195 switch (cmd) { 1196 case DMA_TERMINATE_ALL: 1197 sdma_disable_channel(sdmac); 1198 return 0; 1199 case DMA_SLAVE_CONFIG: 1200 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { 1201 sdmac->per_address = dmaengine_cfg->src_addr; 1202 sdmac->watermark_level = dmaengine_cfg->src_maxburst * 1203 dmaengine_cfg->src_addr_width; 1204 sdmac->word_size = dmaengine_cfg->src_addr_width; 1205 } else { 1206 sdmac->per_address = dmaengine_cfg->dst_addr; 1207 sdmac->watermark_level = dmaengine_cfg->dst_maxburst * 1208 dmaengine_cfg->dst_addr_width; 1209 sdmac->word_size = dmaengine_cfg->dst_addr_width; 1210 } 1211 sdmac->direction = dmaengine_cfg->direction; 1212 return sdma_config_channel(sdmac); 1213 default: 1214 return -ENOSYS; 1215 } 1216 1217 return -EINVAL; 1218 } 1219 1220 static enum dma_status sdma_tx_status(struct dma_chan *chan, 1221 dma_cookie_t cookie, 1222 struct dma_tx_state *txstate) 1223 { 1224 struct sdma_channel *sdmac = to_sdma_chan(chan); 1225 1226 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, 1227 sdmac->chn_count - sdmac->chn_real_count); 1228 1229 return sdmac->status; 1230 } 1231 1232 static void sdma_issue_pending(struct dma_chan *chan) 1233 { 1234 struct sdma_channel *sdmac = to_sdma_chan(chan); 1235 struct sdma_engine *sdma = sdmac->sdma; 1236 1237 if (sdmac->status == DMA_IN_PROGRESS) 1238 sdma_enable_channel(sdma, sdmac->channel); 1239 } 1240 1241 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 1242 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38 1243 1244 static void sdma_add_scripts(struct sdma_engine *sdma, 1245 const struct sdma_script_start_addrs *addr) 1246 { 1247 s32 *addr_arr = (u32 *)addr; 1248 s32 *saddr_arr = (u32 *)sdma->script_addrs; 1249 int i; 1250 1251 for (i = 0; i < sdma->script_number; i++) 1252 if (addr_arr[i] > 0) 1253 saddr_arr[i] = addr_arr[i]; 1254 } 1255 1256 static void sdma_load_firmware(const struct firmware *fw, void *context) 1257 { 1258 struct sdma_engine *sdma = context; 1259 const struct sdma_firmware_header *header; 1260 const struct sdma_script_start_addrs *addr; 1261 unsigned short *ram_code; 1262 1263 if (!fw) { 1264 dev_err(sdma->dev, "firmware not found\n"); 1265 return; 1266 } 1267 1268 if (fw->size < sizeof(*header)) 1269 goto err_firmware; 1270 1271 header = (struct sdma_firmware_header *)fw->data; 1272 1273 if (header->magic != SDMA_FIRMWARE_MAGIC) 1274 goto err_firmware; 1275 if (header->ram_code_start + header->ram_code_size > fw->size) 1276 goto err_firmware; 1277 switch (header->version_major) { 1278 case 1: 1279 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; 1280 break; 1281 case 2: 1282 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; 1283 break; 1284 default: 1285 dev_err(sdma->dev, "unknown firmware version\n"); 1286 goto err_firmware; 1287 } 1288 1289 addr = (void *)header + header->script_addrs_start; 1290 ram_code = (void *)header + header->ram_code_start; 1291 1292 clk_enable(sdma->clk_ipg); 1293 clk_enable(sdma->clk_ahb); 1294 /* download the RAM image for SDMA */ 1295 sdma_load_script(sdma, ram_code, 1296 header->ram_code_size, 1297 addr->ram_code_start_addr); 1298 clk_disable(sdma->clk_ipg); 1299 clk_disable(sdma->clk_ahb); 1300 1301 sdma_add_scripts(sdma, addr); 1302 1303 dev_info(sdma->dev, "loaded firmware %d.%d\n", 1304 header->version_major, 1305 header->version_minor); 1306 1307 err_firmware: 1308 release_firmware(fw); 1309 } 1310 1311 static int __init sdma_get_firmware(struct sdma_engine *sdma, 1312 const char *fw_name) 1313 { 1314 int ret; 1315 1316 ret = request_firmware_nowait(THIS_MODULE, 1317 FW_ACTION_HOTPLUG, fw_name, sdma->dev, 1318 GFP_KERNEL, sdma, sdma_load_firmware); 1319 1320 return ret; 1321 } 1322 1323 static int __init sdma_init(struct sdma_engine *sdma) 1324 { 1325 int i, ret; 1326 dma_addr_t ccb_phys; 1327 1328 clk_enable(sdma->clk_ipg); 1329 clk_enable(sdma->clk_ahb); 1330 1331 /* Be sure SDMA has not started yet */ 1332 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); 1333 1334 sdma->channel_control = dma_alloc_coherent(NULL, 1335 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) + 1336 sizeof(struct sdma_context_data), 1337 &ccb_phys, GFP_KERNEL); 1338 1339 if (!sdma->channel_control) { 1340 ret = -ENOMEM; 1341 goto err_dma_alloc; 1342 } 1343 1344 sdma->context = (void *)sdma->channel_control + 1345 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); 1346 sdma->context_phys = ccb_phys + 1347 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); 1348 1349 /* Zero-out the CCB structures array just allocated */ 1350 memset(sdma->channel_control, 0, 1351 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control)); 1352 1353 /* disable all channels */ 1354 for (i = 0; i < sdma->drvdata->num_events; i++) 1355 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); 1356 1357 /* All channels have priority 0 */ 1358 for (i = 0; i < MAX_DMA_CHANNELS; i++) 1359 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); 1360 1361 ret = sdma_request_channel(&sdma->channel[0]); 1362 if (ret) 1363 goto err_dma_alloc; 1364 1365 sdma_config_ownership(&sdma->channel[0], false, true, false); 1366 1367 /* Set Command Channel (Channel Zero) */ 1368 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); 1369 1370 /* Set bits of CONFIG register but with static context switching */ 1371 /* FIXME: Check whether to set ACR bit depending on clock ratios */ 1372 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); 1373 1374 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); 1375 1376 /* Set bits of CONFIG register with given context switching mode */ 1377 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG); 1378 1379 /* Initializes channel's priorities */ 1380 sdma_set_channel_priority(&sdma->channel[0], 7); 1381 1382 clk_disable(sdma->clk_ipg); 1383 clk_disable(sdma->clk_ahb); 1384 1385 return 0; 1386 1387 err_dma_alloc: 1388 clk_disable(sdma->clk_ipg); 1389 clk_disable(sdma->clk_ahb); 1390 dev_err(sdma->dev, "initialisation failed with %d\n", ret); 1391 return ret; 1392 } 1393 1394 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param) 1395 { 1396 struct imx_dma_data *data = fn_param; 1397 1398 if (!imx_dma_is_general_purpose(chan)) 1399 return false; 1400 1401 chan->private = data; 1402 1403 return true; 1404 } 1405 1406 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec, 1407 struct of_dma *ofdma) 1408 { 1409 struct sdma_engine *sdma = ofdma->of_dma_data; 1410 dma_cap_mask_t mask = sdma->dma_device.cap_mask; 1411 struct imx_dma_data data; 1412 1413 if (dma_spec->args_count != 3) 1414 return NULL; 1415 1416 data.dma_request = dma_spec->args[0]; 1417 data.peripheral_type = dma_spec->args[1]; 1418 data.priority = dma_spec->args[2]; 1419 1420 return dma_request_channel(mask, sdma_filter_fn, &data); 1421 } 1422 1423 static int __init sdma_probe(struct platform_device *pdev) 1424 { 1425 const struct of_device_id *of_id = 1426 of_match_device(sdma_dt_ids, &pdev->dev); 1427 struct device_node *np = pdev->dev.of_node; 1428 const char *fw_name; 1429 int ret; 1430 int irq; 1431 struct resource *iores; 1432 struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev); 1433 int i; 1434 struct sdma_engine *sdma; 1435 s32 *saddr_arr; 1436 const struct sdma_driver_data *drvdata = NULL; 1437 1438 if (of_id) 1439 drvdata = of_id->data; 1440 else if (pdev->id_entry) 1441 drvdata = (void *)pdev->id_entry->driver_data; 1442 1443 if (!drvdata) { 1444 dev_err(&pdev->dev, "unable to find driver data\n"); 1445 return -EINVAL; 1446 } 1447 1448 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 1449 if (ret) 1450 return ret; 1451 1452 sdma = kzalloc(sizeof(*sdma), GFP_KERNEL); 1453 if (!sdma) 1454 return -ENOMEM; 1455 1456 spin_lock_init(&sdma->channel_0_lock); 1457 1458 sdma->dev = &pdev->dev; 1459 sdma->drvdata = drvdata; 1460 1461 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1462 irq = platform_get_irq(pdev, 0); 1463 if (!iores || irq < 0) { 1464 ret = -EINVAL; 1465 goto err_irq; 1466 } 1467 1468 if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) { 1469 ret = -EBUSY; 1470 goto err_request_region; 1471 } 1472 1473 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1474 if (IS_ERR(sdma->clk_ipg)) { 1475 ret = PTR_ERR(sdma->clk_ipg); 1476 goto err_clk; 1477 } 1478 1479 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 1480 if (IS_ERR(sdma->clk_ahb)) { 1481 ret = PTR_ERR(sdma->clk_ahb); 1482 goto err_clk; 1483 } 1484 1485 clk_prepare(sdma->clk_ipg); 1486 clk_prepare(sdma->clk_ahb); 1487 1488 sdma->regs = ioremap(iores->start, resource_size(iores)); 1489 if (!sdma->regs) { 1490 ret = -ENOMEM; 1491 goto err_ioremap; 1492 } 1493 1494 ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma); 1495 if (ret) 1496 goto err_request_irq; 1497 1498 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); 1499 if (!sdma->script_addrs) { 1500 ret = -ENOMEM; 1501 goto err_alloc; 1502 } 1503 1504 /* initially no scripts available */ 1505 saddr_arr = (s32 *)sdma->script_addrs; 1506 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++) 1507 saddr_arr[i] = -EINVAL; 1508 1509 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); 1510 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); 1511 1512 INIT_LIST_HEAD(&sdma->dma_device.channels); 1513 /* Initialize channel parameters */ 1514 for (i = 0; i < MAX_DMA_CHANNELS; i++) { 1515 struct sdma_channel *sdmac = &sdma->channel[i]; 1516 1517 sdmac->sdma = sdma; 1518 spin_lock_init(&sdmac->lock); 1519 1520 sdmac->chan.device = &sdma->dma_device; 1521 dma_cookie_init(&sdmac->chan); 1522 sdmac->channel = i; 1523 1524 tasklet_init(&sdmac->tasklet, sdma_tasklet, 1525 (unsigned long) sdmac); 1526 /* 1527 * Add the channel to the DMAC list. Do not add channel 0 though 1528 * because we need it internally in the SDMA driver. This also means 1529 * that channel 0 in dmaengine counting matches sdma channel 1. 1530 */ 1531 if (i) 1532 list_add_tail(&sdmac->chan.device_node, 1533 &sdma->dma_device.channels); 1534 } 1535 1536 ret = sdma_init(sdma); 1537 if (ret) 1538 goto err_init; 1539 1540 if (sdma->drvdata->script_addrs) 1541 sdma_add_scripts(sdma, sdma->drvdata->script_addrs); 1542 if (pdata && pdata->script_addrs) 1543 sdma_add_scripts(sdma, pdata->script_addrs); 1544 1545 if (pdata) { 1546 ret = sdma_get_firmware(sdma, pdata->fw_name); 1547 if (ret) 1548 dev_warn(&pdev->dev, "failed to get firmware from platform data\n"); 1549 } else { 1550 /* 1551 * Because that device tree does not encode ROM script address, 1552 * the RAM script in firmware is mandatory for device tree 1553 * probe, otherwise it fails. 1554 */ 1555 ret = of_property_read_string(np, "fsl,sdma-ram-script-name", 1556 &fw_name); 1557 if (ret) 1558 dev_warn(&pdev->dev, "failed to get firmware name\n"); 1559 else { 1560 ret = sdma_get_firmware(sdma, fw_name); 1561 if (ret) 1562 dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); 1563 } 1564 } 1565 1566 sdma->dma_device.dev = &pdev->dev; 1567 1568 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; 1569 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; 1570 sdma->dma_device.device_tx_status = sdma_tx_status; 1571 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; 1572 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; 1573 sdma->dma_device.device_control = sdma_control; 1574 sdma->dma_device.device_issue_pending = sdma_issue_pending; 1575 sdma->dma_device.dev->dma_parms = &sdma->dma_parms; 1576 dma_set_max_seg_size(sdma->dma_device.dev, 65535); 1577 1578 ret = dma_async_device_register(&sdma->dma_device); 1579 if (ret) { 1580 dev_err(&pdev->dev, "unable to register\n"); 1581 goto err_init; 1582 } 1583 1584 if (np) { 1585 ret = of_dma_controller_register(np, sdma_xlate, sdma); 1586 if (ret) { 1587 dev_err(&pdev->dev, "failed to register controller\n"); 1588 goto err_register; 1589 } 1590 } 1591 1592 dev_info(sdma->dev, "initialized\n"); 1593 1594 return 0; 1595 1596 err_register: 1597 dma_async_device_unregister(&sdma->dma_device); 1598 err_init: 1599 kfree(sdma->script_addrs); 1600 err_alloc: 1601 free_irq(irq, sdma); 1602 err_request_irq: 1603 iounmap(sdma->regs); 1604 err_ioremap: 1605 err_clk: 1606 release_mem_region(iores->start, resource_size(iores)); 1607 err_request_region: 1608 err_irq: 1609 kfree(sdma); 1610 return ret; 1611 } 1612 1613 static int sdma_remove(struct platform_device *pdev) 1614 { 1615 return -EBUSY; 1616 } 1617 1618 static struct platform_driver sdma_driver = { 1619 .driver = { 1620 .name = "imx-sdma", 1621 .of_match_table = sdma_dt_ids, 1622 }, 1623 .id_table = sdma_devtypes, 1624 .remove = sdma_remove, 1625 }; 1626 1627 static int __init sdma_module_init(void) 1628 { 1629 return platform_driver_probe(&sdma_driver, sdma_probe); 1630 } 1631 module_init(sdma_module_init); 1632 1633 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); 1634 MODULE_DESCRIPTION("i.MX SDMA driver"); 1635 MODULE_LICENSE("GPL"); 1636