1d1dfe5b8SDave Jiang // SPDX-License-Identifier: GPL-2.0 2d1dfe5b8SDave Jiang /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3d1dfe5b8SDave Jiang #include <linux/init.h> 4d1dfe5b8SDave Jiang #include <linux/kernel.h> 5d1dfe5b8SDave Jiang #include <linux/module.h> 6d1dfe5b8SDave Jiang #include <linux/pci.h> 7d1dfe5b8SDave Jiang #include <uapi/linux/idxd.h> 8d1dfe5b8SDave Jiang #include "idxd.h" 9d1dfe5b8SDave Jiang #include "registers.h" 10d1dfe5b8SDave Jiang 110705107fSDave Jiang static struct idxd_desc *__get_desc(struct idxd_wq *wq, int idx, int cpu) 12d1dfe5b8SDave Jiang { 13d1dfe5b8SDave Jiang struct idxd_desc *desc; 148e50d392SDave Jiang struct idxd_device *idxd = wq->idxd; 15d1dfe5b8SDave Jiang 16d1dfe5b8SDave Jiang desc = wq->descs[idx]; 17d1dfe5b8SDave Jiang memset(desc->hw, 0, sizeof(struct dsa_hw_desc)); 18435b512dSDave Jiang memset(desc->completion, 0, idxd->data->compl_size); 190705107fSDave Jiang desc->cpu = cpu; 208e50d392SDave Jiang 218e50d392SDave Jiang if (device_pasid_enabled(idxd)) 228e50d392SDave Jiang desc->hw->pasid = idxd->pasid; 238e50d392SDave Jiang 248e50d392SDave Jiang /* 256cfd9e62SDave Jiang * On host, MSIX vecotr 0 is used for misc interrupt. Therefore when we match 266cfd9e62SDave Jiang * vector 1:1 to the WQ id, we need to add 1 278e50d392SDave Jiang */ 286cfd9e62SDave Jiang if (!idxd->int_handles) 296cfd9e62SDave Jiang desc->hw->int_handle = wq->id + 1; 306cfd9e62SDave Jiang else 316cfd9e62SDave Jiang desc->hw->int_handle = idxd->int_handles[wq->id]; 32eb15e715SDave Jiang 33d1dfe5b8SDave Jiang return desc; 34d1dfe5b8SDave Jiang } 35d1dfe5b8SDave Jiang 360705107fSDave Jiang struct idxd_desc *idxd_alloc_desc(struct idxd_wq *wq, enum idxd_op_type optype) 370705107fSDave Jiang { 380705107fSDave Jiang int cpu, idx; 390705107fSDave Jiang struct idxd_device *idxd = wq->idxd; 400705107fSDave Jiang DEFINE_SBQ_WAIT(wait); 410705107fSDave Jiang struct sbq_wait_state *ws; 420705107fSDave Jiang struct sbitmap_queue *sbq; 430705107fSDave Jiang 440705107fSDave Jiang if (idxd->state != IDXD_DEV_ENABLED) 450705107fSDave Jiang return ERR_PTR(-EIO); 460705107fSDave Jiang 470705107fSDave Jiang sbq = &wq->sbq; 480705107fSDave Jiang idx = sbitmap_queue_get(sbq, &cpu); 490705107fSDave Jiang if (idx < 0) { 500705107fSDave Jiang if (optype == IDXD_OP_NONBLOCK) 510705107fSDave Jiang return ERR_PTR(-EAGAIN); 520705107fSDave Jiang } else { 530705107fSDave Jiang return __get_desc(wq, idx, cpu); 540705107fSDave Jiang } 550705107fSDave Jiang 560705107fSDave Jiang ws = &sbq->ws[0]; 570705107fSDave Jiang for (;;) { 580705107fSDave Jiang sbitmap_prepare_to_wait(sbq, ws, &wait, TASK_INTERRUPTIBLE); 590705107fSDave Jiang if (signal_pending_state(TASK_INTERRUPTIBLE, current)) 600705107fSDave Jiang break; 610705107fSDave Jiang idx = sbitmap_queue_get(sbq, &cpu); 62673d812dSDave Jiang if (idx >= 0) 630705107fSDave Jiang break; 640705107fSDave Jiang schedule(); 650705107fSDave Jiang } 660705107fSDave Jiang 670705107fSDave Jiang sbitmap_finish_wait(sbq, ws, &wait); 680705107fSDave Jiang if (idx < 0) 690705107fSDave Jiang return ERR_PTR(-EAGAIN); 700705107fSDave Jiang 710705107fSDave Jiang return __get_desc(wq, idx, cpu); 720705107fSDave Jiang } 730705107fSDave Jiang 74d1dfe5b8SDave Jiang void idxd_free_desc(struct idxd_wq *wq, struct idxd_desc *desc) 75d1dfe5b8SDave Jiang { 760705107fSDave Jiang int cpu = desc->cpu; 77d1dfe5b8SDave Jiang 780705107fSDave Jiang desc->cpu = -1; 790705107fSDave Jiang sbitmap_queue_clear(&wq->sbq, desc->id, cpu); 80d1dfe5b8SDave Jiang } 81d1dfe5b8SDave Jiang 826b4b87f2SDave Jiang static struct idxd_desc *list_abort_desc(struct idxd_wq *wq, struct idxd_irq_entry *ie, 836b4b87f2SDave Jiang struct idxd_desc *desc) 846b4b87f2SDave Jiang { 856b4b87f2SDave Jiang struct idxd_desc *d, *n; 866b4b87f2SDave Jiang 876b4b87f2SDave Jiang lockdep_assert_held(&ie->list_lock); 886b4b87f2SDave Jiang list_for_each_entry_safe(d, n, &ie->work_list, list) { 896b4b87f2SDave Jiang if (d == desc) { 906b4b87f2SDave Jiang list_del(&d->list); 916b4b87f2SDave Jiang return d; 926b4b87f2SDave Jiang } 936b4b87f2SDave Jiang } 946b4b87f2SDave Jiang 956b4b87f2SDave Jiang /* 966b4b87f2SDave Jiang * At this point, the desc needs to be aborted is held by the completion 976b4b87f2SDave Jiang * handler where it has taken it off the pending list but has not added to the 986b4b87f2SDave Jiang * work list. It will be cleaned up by the interrupt handler when it sees the 996b4b87f2SDave Jiang * IDXD_COMP_DESC_ABORT for completion status. 1006b4b87f2SDave Jiang */ 1016b4b87f2SDave Jiang return NULL; 1026b4b87f2SDave Jiang } 1036b4b87f2SDave Jiang 1046b4b87f2SDave Jiang static void llist_abort_desc(struct idxd_wq *wq, struct idxd_irq_entry *ie, 1056b4b87f2SDave Jiang struct idxd_desc *desc) 1066b4b87f2SDave Jiang { 1076b4b87f2SDave Jiang struct idxd_desc *d, *t, *found = NULL; 1086b4b87f2SDave Jiang struct llist_node *head; 1096b4b87f2SDave Jiang 1106b4b87f2SDave Jiang desc->completion->status = IDXD_COMP_DESC_ABORT; 1116b4b87f2SDave Jiang /* 1126b4b87f2SDave Jiang * Grab the list lock so it will block the irq thread handler. This allows the 1136b4b87f2SDave Jiang * abort code to locate the descriptor need to be aborted. 1146b4b87f2SDave Jiang */ 115*9fce3b3aSDave Jiang spin_lock(&ie->list_lock); 1166b4b87f2SDave Jiang head = llist_del_all(&ie->pending_llist); 1176b4b87f2SDave Jiang if (head) { 1186b4b87f2SDave Jiang llist_for_each_entry_safe(d, t, head, llnode) { 1196b4b87f2SDave Jiang if (d == desc) { 1206b4b87f2SDave Jiang found = desc; 1216b4b87f2SDave Jiang continue; 1226b4b87f2SDave Jiang } 1236b4b87f2SDave Jiang list_add_tail(&desc->list, &ie->work_list); 1246b4b87f2SDave Jiang } 1256b4b87f2SDave Jiang } 1266b4b87f2SDave Jiang 1276b4b87f2SDave Jiang if (!found) 1286b4b87f2SDave Jiang found = list_abort_desc(wq, ie, desc); 129*9fce3b3aSDave Jiang spin_unlock(&ie->list_lock); 1306b4b87f2SDave Jiang 1316b4b87f2SDave Jiang if (found) 1326b4b87f2SDave Jiang complete_desc(found, IDXD_COMPLETE_ABORT); 1336b4b87f2SDave Jiang } 1346b4b87f2SDave Jiang 135d1dfe5b8SDave Jiang int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc) 136d1dfe5b8SDave Jiang { 137d1dfe5b8SDave Jiang struct idxd_device *idxd = wq->idxd; 1386b4b87f2SDave Jiang struct idxd_irq_entry *ie = NULL; 13942d279f9SDave Jiang void __iomem *portal; 1408e50d392SDave Jiang int rc; 141d1dfe5b8SDave Jiang 142d1dfe5b8SDave Jiang if (idxd->state != IDXD_DEV_ENABLED) 143d1dfe5b8SDave Jiang return -EIO; 144d1dfe5b8SDave Jiang 14593a40a6dSDave Jiang if (!percpu_ref_tryget_live(&wq->wq_active)) 14693a40a6dSDave Jiang return -ENXIO; 14793a40a6dSDave Jiang 148a9c17152SDave Jiang portal = idxd_wq_portal_addr(wq); 1498e50d392SDave Jiang 150d1dfe5b8SDave Jiang /* 1518e50d392SDave Jiang * The wmb() flushes writes to coherent DMA data before 1528e50d392SDave Jiang * possibly triggering a DMA read. The wmb() is necessary 1538e50d392SDave Jiang * even on UP because the recipient is a device. 154d1dfe5b8SDave Jiang */ 155d1dfe5b8SDave Jiang wmb(); 1566b4b87f2SDave Jiang 1576b4b87f2SDave Jiang /* 1586b4b87f2SDave Jiang * Pending the descriptor to the lockless list for the irq_entry 1596b4b87f2SDave Jiang * that we designated the descriptor to. 1606b4b87f2SDave Jiang */ 1616b4b87f2SDave Jiang if (desc->hw->flags & IDXD_OP_FLAG_RCI) { 16288c5d0a2SVinod Koul ie = &idxd->irq_entries[wq->id + 1]; 1636b4b87f2SDave Jiang llist_add(&desc->llnode, &ie->pending_llist); 1646b4b87f2SDave Jiang } 1656b4b87f2SDave Jiang 1668e50d392SDave Jiang if (wq_dedicated(wq)) { 16742d279f9SDave Jiang iosubmit_cmds512(portal, desc->hw, 1); 1688e50d392SDave Jiang } else { 1698e50d392SDave Jiang /* 1708e50d392SDave Jiang * It's not likely that we would receive queue full rejection 1718e50d392SDave Jiang * since the descriptor allocation gates at wq size. If we 1728e50d392SDave Jiang * receive a -EAGAIN, that means something went wrong such as the 1738e50d392SDave Jiang * device is not accepting descriptor at all. 1748e50d392SDave Jiang */ 1758e50d392SDave Jiang rc = enqcmds(portal, desc->hw); 176ac24a2dcSDave Jiang if (rc < 0) { 177ac24a2dcSDave Jiang percpu_ref_put(&wq->wq_active); 1786b4b87f2SDave Jiang if (ie) 1796b4b87f2SDave Jiang llist_abort_desc(wq, ie, desc); 1808e50d392SDave Jiang return rc; 1818e50d392SDave Jiang } 182ac24a2dcSDave Jiang } 183d1dfe5b8SDave Jiang 18493a40a6dSDave Jiang percpu_ref_put(&wq->wq_active); 185d1dfe5b8SDave Jiang return 0; 186d1dfe5b8SDave Jiang } 187