1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #include <linux/init.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/io-64-nonatomic-lo-hi.h> 8 #include <linux/dmaengine.h> 9 #include <uapi/linux/idxd.h> 10 #include "../dmaengine.h" 11 #include "idxd.h" 12 #include "registers.h" 13 14 void idxd_device_wqs_clear_state(struct idxd_device *idxd) 15 { 16 int i; 17 18 lockdep_assert_held(&idxd->dev_lock); 19 for (i = 0; i < idxd->max_wqs; i++) { 20 struct idxd_wq *wq = &idxd->wqs[i]; 21 22 wq->state = IDXD_WQ_DISABLED; 23 } 24 } 25 26 static void idxd_device_reinit(struct work_struct *work) 27 { 28 struct idxd_device *idxd = container_of(work, struct idxd_device, work); 29 struct device *dev = &idxd->pdev->dev; 30 int rc, i; 31 32 idxd_device_reset(idxd); 33 rc = idxd_device_config(idxd); 34 if (rc < 0) 35 goto out; 36 37 rc = idxd_device_enable(idxd); 38 if (rc < 0) 39 goto out; 40 41 for (i = 0; i < idxd->max_wqs; i++) { 42 struct idxd_wq *wq = &idxd->wqs[i]; 43 44 if (wq->state == IDXD_WQ_ENABLED) { 45 rc = idxd_wq_enable(wq); 46 if (rc < 0) { 47 dev_warn(dev, "Unable to re-enable wq %s\n", 48 dev_name(&wq->conf_dev)); 49 } 50 } 51 } 52 53 return; 54 55 out: 56 idxd_device_wqs_clear_state(idxd); 57 } 58 59 irqreturn_t idxd_irq_handler(int vec, void *data) 60 { 61 struct idxd_irq_entry *irq_entry = data; 62 struct idxd_device *idxd = irq_entry->idxd; 63 64 idxd_mask_msix_vector(idxd, irq_entry->id); 65 return IRQ_WAKE_THREAD; 66 } 67 68 irqreturn_t idxd_misc_thread(int vec, void *data) 69 { 70 struct idxd_irq_entry *irq_entry = data; 71 struct idxd_device *idxd = irq_entry->idxd; 72 struct device *dev = &idxd->pdev->dev; 73 union gensts_reg gensts; 74 u32 cause, val = 0; 75 int i; 76 bool err = false; 77 78 cause = ioread32(idxd->reg_base + IDXD_INTCAUSE_OFFSET); 79 80 if (cause & IDXD_INTC_ERR) { 81 spin_lock_bh(&idxd->dev_lock); 82 for (i = 0; i < 4; i++) 83 idxd->sw_err.bits[i] = ioread64(idxd->reg_base + 84 IDXD_SWERR_OFFSET + i * sizeof(u64)); 85 iowrite64(IDXD_SWERR_ACK, idxd->reg_base + IDXD_SWERR_OFFSET); 86 87 if (idxd->sw_err.valid && idxd->sw_err.wq_idx_valid) { 88 int id = idxd->sw_err.wq_idx; 89 struct idxd_wq *wq = &idxd->wqs[id]; 90 91 if (wq->type == IDXD_WQT_USER) 92 wake_up_interruptible(&wq->idxd_cdev.err_queue); 93 } else { 94 int i; 95 96 for (i = 0; i < idxd->max_wqs; i++) { 97 struct idxd_wq *wq = &idxd->wqs[i]; 98 99 if (wq->type == IDXD_WQT_USER) 100 wake_up_interruptible(&wq->idxd_cdev.err_queue); 101 } 102 } 103 104 spin_unlock_bh(&idxd->dev_lock); 105 val |= IDXD_INTC_ERR; 106 107 for (i = 0; i < 4; i++) 108 dev_warn(dev, "err[%d]: %#16.16llx\n", 109 i, idxd->sw_err.bits[i]); 110 err = true; 111 } 112 113 if (cause & IDXD_INTC_CMD) { 114 val |= IDXD_INTC_CMD; 115 complete(idxd->cmd_done); 116 } 117 118 if (cause & IDXD_INTC_OCCUPY) { 119 /* Driver does not utilize occupancy interrupt */ 120 val |= IDXD_INTC_OCCUPY; 121 } 122 123 if (cause & IDXD_INTC_PERFMON_OVFL) { 124 /* 125 * Driver does not utilize perfmon counter overflow interrupt 126 * yet. 127 */ 128 val |= IDXD_INTC_PERFMON_OVFL; 129 } 130 131 val ^= cause; 132 if (val) 133 dev_warn_once(dev, "Unexpected interrupt cause bits set: %#x\n", 134 val); 135 136 iowrite32(cause, idxd->reg_base + IDXD_INTCAUSE_OFFSET); 137 if (!err) 138 return IRQ_HANDLED; 139 140 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET); 141 if (gensts.state == IDXD_DEVICE_STATE_HALT) { 142 idxd->state = IDXD_DEV_HALTED; 143 if (gensts.reset_type == IDXD_DEVICE_RESET_SOFTWARE) { 144 /* 145 * If we need a software reset, we will throw the work 146 * on a system workqueue in order to allow interrupts 147 * for the device command completions. 148 */ 149 INIT_WORK(&idxd->work, idxd_device_reinit); 150 queue_work(idxd->wq, &idxd->work); 151 } else { 152 spin_lock_bh(&idxd->dev_lock); 153 idxd_device_wqs_clear_state(idxd); 154 dev_err(&idxd->pdev->dev, 155 "idxd halted, need %s.\n", 156 gensts.reset_type == IDXD_DEVICE_RESET_FLR ? 157 "FLR" : "system reset"); 158 spin_unlock_bh(&idxd->dev_lock); 159 } 160 } 161 162 idxd_unmask_msix_vector(idxd, irq_entry->id); 163 return IRQ_HANDLED; 164 } 165 166 static int irq_process_pending_llist(struct idxd_irq_entry *irq_entry, 167 int *processed) 168 { 169 struct idxd_desc *desc, *t; 170 struct llist_node *head; 171 int queued = 0; 172 173 *processed = 0; 174 head = llist_del_all(&irq_entry->pending_llist); 175 if (!head) 176 return 0; 177 178 llist_for_each_entry_safe(desc, t, head, llnode) { 179 if (desc->completion->status) { 180 idxd_dma_complete_txd(desc, IDXD_COMPLETE_NORMAL); 181 idxd_free_desc(desc->wq, desc); 182 (*processed)++; 183 } else { 184 list_add_tail(&desc->list, &irq_entry->work_list); 185 queued++; 186 } 187 } 188 189 return queued; 190 } 191 192 static int irq_process_work_list(struct idxd_irq_entry *irq_entry, 193 int *processed) 194 { 195 struct list_head *node, *next; 196 int queued = 0; 197 198 *processed = 0; 199 if (list_empty(&irq_entry->work_list)) 200 return 0; 201 202 list_for_each_safe(node, next, &irq_entry->work_list) { 203 struct idxd_desc *desc = 204 container_of(node, struct idxd_desc, list); 205 206 if (desc->completion->status) { 207 list_del(&desc->list); 208 /* process and callback */ 209 idxd_dma_complete_txd(desc, IDXD_COMPLETE_NORMAL); 210 idxd_free_desc(desc->wq, desc); 211 (*processed)++; 212 } else { 213 queued++; 214 } 215 } 216 217 return queued; 218 } 219 220 static int idxd_desc_process(struct idxd_irq_entry *irq_entry) 221 { 222 int rc, processed, total = 0; 223 224 /* 225 * There are two lists we are processing. The pending_llist is where 226 * submmiter adds all the submitted descriptor after sending it to 227 * the workqueue. It's a lockless singly linked list. The work_list 228 * is the common linux double linked list. We are in a scenario of 229 * multiple producers and a single consumer. The producers are all 230 * the kernel submitters of descriptors, and the consumer is the 231 * kernel irq handler thread for the msix vector when using threaded 232 * irq. To work with the restrictions of llist to remain lockless, 233 * we are doing the following steps: 234 * 1. Iterate through the work_list and process any completed 235 * descriptor. Delete the completed entries during iteration. 236 * 2. llist_del_all() from the pending list. 237 * 3. Iterate through the llist that was deleted from the pending list 238 * and process the completed entries. 239 * 4. If the entry is still waiting on hardware, list_add_tail() to 240 * the work_list. 241 * 5. Repeat until no more descriptors. 242 */ 243 do { 244 rc = irq_process_work_list(irq_entry, &processed); 245 total += processed; 246 if (rc != 0) 247 continue; 248 249 rc = irq_process_pending_llist(irq_entry, &processed); 250 total += processed; 251 } while (rc != 0); 252 253 return total; 254 } 255 256 irqreturn_t idxd_wq_thread(int irq, void *data) 257 { 258 struct idxd_irq_entry *irq_entry = data; 259 int processed; 260 261 processed = idxd_desc_process(irq_entry); 262 idxd_unmask_msix_vector(irq_entry->idxd, irq_entry->id); 263 264 if (processed == 0) 265 return IRQ_NONE; 266 267 return IRQ_HANDLED; 268 } 269