1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #include <linux/init.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/io-64-nonatomic-lo-hi.h> 8 #include <linux/dmaengine.h> 9 #include <linux/irq.h> 10 #include <linux/msi.h> 11 #include <uapi/linux/idxd.h> 12 #include "../dmaengine.h" 13 #include "idxd.h" 14 #include "registers.h" 15 16 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand, 17 u32 *status); 18 static void idxd_device_wqs_clear_state(struct idxd_device *idxd); 19 static void idxd_wq_disable_cleanup(struct idxd_wq *wq); 20 21 /* Interrupt control bits */ 22 void idxd_mask_msix_vector(struct idxd_device *idxd, int vec_id) 23 { 24 struct irq_data *data = irq_get_irq_data(idxd->irq_entries[vec_id].vector); 25 26 pci_msi_mask_irq(data); 27 } 28 29 void idxd_mask_msix_vectors(struct idxd_device *idxd) 30 { 31 struct pci_dev *pdev = idxd->pdev; 32 int msixcnt = pci_msix_vec_count(pdev); 33 int i; 34 35 for (i = 0; i < msixcnt; i++) 36 idxd_mask_msix_vector(idxd, i); 37 } 38 39 void idxd_unmask_msix_vector(struct idxd_device *idxd, int vec_id) 40 { 41 struct irq_data *data = irq_get_irq_data(idxd->irq_entries[vec_id].vector); 42 43 pci_msi_unmask_irq(data); 44 } 45 46 void idxd_unmask_error_interrupts(struct idxd_device *idxd) 47 { 48 union genctrl_reg genctrl; 49 50 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); 51 genctrl.softerr_int_en = 1; 52 genctrl.halt_int_en = 1; 53 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); 54 } 55 56 void idxd_mask_error_interrupts(struct idxd_device *idxd) 57 { 58 union genctrl_reg genctrl; 59 60 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); 61 genctrl.softerr_int_en = 0; 62 genctrl.halt_int_en = 0; 63 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); 64 } 65 66 static void free_hw_descs(struct idxd_wq *wq) 67 { 68 int i; 69 70 for (i = 0; i < wq->num_descs; i++) 71 kfree(wq->hw_descs[i]); 72 73 kfree(wq->hw_descs); 74 } 75 76 static int alloc_hw_descs(struct idxd_wq *wq, int num) 77 { 78 struct device *dev = &wq->idxd->pdev->dev; 79 int i; 80 int node = dev_to_node(dev); 81 82 wq->hw_descs = kcalloc_node(num, sizeof(struct dsa_hw_desc *), 83 GFP_KERNEL, node); 84 if (!wq->hw_descs) 85 return -ENOMEM; 86 87 for (i = 0; i < num; i++) { 88 wq->hw_descs[i] = kzalloc_node(sizeof(*wq->hw_descs[i]), 89 GFP_KERNEL, node); 90 if (!wq->hw_descs[i]) { 91 free_hw_descs(wq); 92 return -ENOMEM; 93 } 94 } 95 96 return 0; 97 } 98 99 static void free_descs(struct idxd_wq *wq) 100 { 101 int i; 102 103 for (i = 0; i < wq->num_descs; i++) 104 kfree(wq->descs[i]); 105 106 kfree(wq->descs); 107 } 108 109 static int alloc_descs(struct idxd_wq *wq, int num) 110 { 111 struct device *dev = &wq->idxd->pdev->dev; 112 int i; 113 int node = dev_to_node(dev); 114 115 wq->descs = kcalloc_node(num, sizeof(struct idxd_desc *), 116 GFP_KERNEL, node); 117 if (!wq->descs) 118 return -ENOMEM; 119 120 for (i = 0; i < num; i++) { 121 wq->descs[i] = kzalloc_node(sizeof(*wq->descs[i]), 122 GFP_KERNEL, node); 123 if (!wq->descs[i]) { 124 free_descs(wq); 125 return -ENOMEM; 126 } 127 } 128 129 return 0; 130 } 131 132 /* WQ control bits */ 133 int idxd_wq_alloc_resources(struct idxd_wq *wq) 134 { 135 struct idxd_device *idxd = wq->idxd; 136 struct device *dev = &idxd->pdev->dev; 137 int rc, num_descs, i; 138 int align; 139 u64 tmp; 140 141 if (wq->type != IDXD_WQT_KERNEL) 142 return 0; 143 144 num_descs = wq_dedicated(wq) ? wq->size : wq->threshold; 145 wq->num_descs = num_descs; 146 147 rc = alloc_hw_descs(wq, num_descs); 148 if (rc < 0) 149 return rc; 150 151 align = idxd->data->align; 152 wq->compls_size = num_descs * idxd->data->compl_size + align; 153 wq->compls_raw = dma_alloc_coherent(dev, wq->compls_size, 154 &wq->compls_addr_raw, GFP_KERNEL); 155 if (!wq->compls_raw) { 156 rc = -ENOMEM; 157 goto fail_alloc_compls; 158 } 159 160 /* Adjust alignment */ 161 wq->compls_addr = (wq->compls_addr_raw + (align - 1)) & ~(align - 1); 162 tmp = (u64)wq->compls_raw; 163 tmp = (tmp + (align - 1)) & ~(align - 1); 164 wq->compls = (struct dsa_completion_record *)tmp; 165 166 rc = alloc_descs(wq, num_descs); 167 if (rc < 0) 168 goto fail_alloc_descs; 169 170 rc = sbitmap_queue_init_node(&wq->sbq, num_descs, -1, false, GFP_KERNEL, 171 dev_to_node(dev)); 172 if (rc < 0) 173 goto fail_sbitmap_init; 174 175 for (i = 0; i < num_descs; i++) { 176 struct idxd_desc *desc = wq->descs[i]; 177 178 desc->hw = wq->hw_descs[i]; 179 if (idxd->data->type == IDXD_TYPE_DSA) 180 desc->completion = &wq->compls[i]; 181 else if (idxd->data->type == IDXD_TYPE_IAX) 182 desc->iax_completion = &wq->iax_compls[i]; 183 desc->compl_dma = wq->compls_addr + idxd->data->compl_size * i; 184 desc->id = i; 185 desc->wq = wq; 186 desc->cpu = -1; 187 } 188 189 return 0; 190 191 fail_sbitmap_init: 192 free_descs(wq); 193 fail_alloc_descs: 194 dma_free_coherent(dev, wq->compls_size, wq->compls_raw, 195 wq->compls_addr_raw); 196 fail_alloc_compls: 197 free_hw_descs(wq); 198 return rc; 199 } 200 201 void idxd_wq_free_resources(struct idxd_wq *wq) 202 { 203 struct device *dev = &wq->idxd->pdev->dev; 204 205 if (wq->type != IDXD_WQT_KERNEL) 206 return; 207 208 free_hw_descs(wq); 209 free_descs(wq); 210 dma_free_coherent(dev, wq->compls_size, wq->compls_raw, 211 wq->compls_addr_raw); 212 sbitmap_queue_free(&wq->sbq); 213 } 214 215 int idxd_wq_enable(struct idxd_wq *wq) 216 { 217 struct idxd_device *idxd = wq->idxd; 218 struct device *dev = &idxd->pdev->dev; 219 u32 status; 220 221 if (wq->state == IDXD_WQ_ENABLED) { 222 dev_dbg(dev, "WQ %d already enabled\n", wq->id); 223 return -ENXIO; 224 } 225 226 idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_WQ, wq->id, &status); 227 228 if (status != IDXD_CMDSTS_SUCCESS && 229 status != IDXD_CMDSTS_ERR_WQ_ENABLED) { 230 dev_dbg(dev, "WQ enable failed: %#x\n", status); 231 return -ENXIO; 232 } 233 234 wq->state = IDXD_WQ_ENABLED; 235 dev_dbg(dev, "WQ %d enabled\n", wq->id); 236 return 0; 237 } 238 239 int idxd_wq_disable(struct idxd_wq *wq, bool reset_config) 240 { 241 struct idxd_device *idxd = wq->idxd; 242 struct device *dev = &idxd->pdev->dev; 243 u32 status, operand; 244 245 dev_dbg(dev, "Disabling WQ %d\n", wq->id); 246 247 if (wq->state != IDXD_WQ_ENABLED) { 248 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 249 return 0; 250 } 251 252 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 253 idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_WQ, operand, &status); 254 255 if (status != IDXD_CMDSTS_SUCCESS) { 256 dev_dbg(dev, "WQ disable failed: %#x\n", status); 257 return -ENXIO; 258 } 259 260 if (reset_config) 261 idxd_wq_disable_cleanup(wq); 262 wq->state = IDXD_WQ_DISABLED; 263 dev_dbg(dev, "WQ %d disabled\n", wq->id); 264 return 0; 265 } 266 267 void idxd_wq_drain(struct idxd_wq *wq) 268 { 269 struct idxd_device *idxd = wq->idxd; 270 struct device *dev = &idxd->pdev->dev; 271 u32 operand; 272 273 if (wq->state != IDXD_WQ_ENABLED) { 274 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 275 return; 276 } 277 278 dev_dbg(dev, "Draining WQ %d\n", wq->id); 279 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 280 idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_WQ, operand, NULL); 281 } 282 283 void idxd_wq_reset(struct idxd_wq *wq) 284 { 285 struct idxd_device *idxd = wq->idxd; 286 struct device *dev = &idxd->pdev->dev; 287 u32 operand; 288 289 if (wq->state != IDXD_WQ_ENABLED) { 290 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 291 return; 292 } 293 294 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 295 idxd_cmd_exec(idxd, IDXD_CMD_RESET_WQ, operand, NULL); 296 idxd_wq_disable_cleanup(wq); 297 wq->state = IDXD_WQ_DISABLED; 298 } 299 300 int idxd_wq_map_portal(struct idxd_wq *wq) 301 { 302 struct idxd_device *idxd = wq->idxd; 303 struct pci_dev *pdev = idxd->pdev; 304 struct device *dev = &pdev->dev; 305 resource_size_t start; 306 307 start = pci_resource_start(pdev, IDXD_WQ_BAR); 308 start += idxd_get_wq_portal_full_offset(wq->id, IDXD_PORTAL_LIMITED); 309 310 wq->portal = devm_ioremap(dev, start, IDXD_PORTAL_SIZE); 311 if (!wq->portal) 312 return -ENOMEM; 313 314 return 0; 315 } 316 317 void idxd_wq_unmap_portal(struct idxd_wq *wq) 318 { 319 struct device *dev = &wq->idxd->pdev->dev; 320 321 devm_iounmap(dev, wq->portal); 322 wq->portal = NULL; 323 wq->portal_offset = 0; 324 } 325 326 void idxd_wqs_unmap_portal(struct idxd_device *idxd) 327 { 328 int i; 329 330 for (i = 0; i < idxd->max_wqs; i++) { 331 struct idxd_wq *wq = idxd->wqs[i]; 332 333 if (wq->portal) 334 idxd_wq_unmap_portal(wq); 335 } 336 } 337 338 int idxd_wq_set_pasid(struct idxd_wq *wq, int pasid) 339 { 340 struct idxd_device *idxd = wq->idxd; 341 int rc; 342 union wqcfg wqcfg; 343 unsigned int offset; 344 345 rc = idxd_wq_disable(wq, false); 346 if (rc < 0) 347 return rc; 348 349 offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX); 350 spin_lock(&idxd->dev_lock); 351 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset); 352 wqcfg.pasid_en = 1; 353 wqcfg.pasid = pasid; 354 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset); 355 spin_unlock(&idxd->dev_lock); 356 357 rc = idxd_wq_enable(wq); 358 if (rc < 0) 359 return rc; 360 361 return 0; 362 } 363 364 int idxd_wq_disable_pasid(struct idxd_wq *wq) 365 { 366 struct idxd_device *idxd = wq->idxd; 367 int rc; 368 union wqcfg wqcfg; 369 unsigned int offset; 370 371 rc = idxd_wq_disable(wq, false); 372 if (rc < 0) 373 return rc; 374 375 offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX); 376 spin_lock(&idxd->dev_lock); 377 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset); 378 wqcfg.pasid_en = 0; 379 wqcfg.pasid = 0; 380 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset); 381 spin_unlock(&idxd->dev_lock); 382 383 rc = idxd_wq_enable(wq); 384 if (rc < 0) 385 return rc; 386 387 return 0; 388 } 389 390 static void idxd_wq_disable_cleanup(struct idxd_wq *wq) 391 { 392 struct idxd_device *idxd = wq->idxd; 393 394 lockdep_assert_held(&wq->wq_lock); 395 memset(wq->wqcfg, 0, idxd->wqcfg_size); 396 wq->type = IDXD_WQT_NONE; 397 wq->size = 0; 398 wq->group = NULL; 399 wq->threshold = 0; 400 wq->priority = 0; 401 wq->ats_dis = 0; 402 clear_bit(WQ_FLAG_DEDICATED, &wq->flags); 403 clear_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags); 404 memset(wq->name, 0, WQ_NAME_SIZE); 405 } 406 407 static void idxd_wq_ref_release(struct percpu_ref *ref) 408 { 409 struct idxd_wq *wq = container_of(ref, struct idxd_wq, wq_active); 410 411 complete(&wq->wq_dead); 412 } 413 414 int idxd_wq_init_percpu_ref(struct idxd_wq *wq) 415 { 416 int rc; 417 418 memset(&wq->wq_active, 0, sizeof(wq->wq_active)); 419 rc = percpu_ref_init(&wq->wq_active, idxd_wq_ref_release, 0, GFP_KERNEL); 420 if (rc < 0) 421 return rc; 422 reinit_completion(&wq->wq_dead); 423 return 0; 424 } 425 426 void idxd_wq_quiesce(struct idxd_wq *wq) 427 { 428 percpu_ref_kill(&wq->wq_active); 429 wait_for_completion(&wq->wq_dead); 430 } 431 432 /* Device control bits */ 433 static inline bool idxd_is_enabled(struct idxd_device *idxd) 434 { 435 union gensts_reg gensts; 436 437 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET); 438 439 if (gensts.state == IDXD_DEVICE_STATE_ENABLED) 440 return true; 441 return false; 442 } 443 444 static inline bool idxd_device_is_halted(struct idxd_device *idxd) 445 { 446 union gensts_reg gensts; 447 448 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET); 449 450 return (gensts.state == IDXD_DEVICE_STATE_HALT); 451 } 452 453 /* 454 * This is function is only used for reset during probe and will 455 * poll for completion. Once the device is setup with interrupts, 456 * all commands will be done via interrupt completion. 457 */ 458 int idxd_device_init_reset(struct idxd_device *idxd) 459 { 460 struct device *dev = &idxd->pdev->dev; 461 union idxd_command_reg cmd; 462 463 if (idxd_device_is_halted(idxd)) { 464 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n"); 465 return -ENXIO; 466 } 467 468 memset(&cmd, 0, sizeof(cmd)); 469 cmd.cmd = IDXD_CMD_RESET_DEVICE; 470 dev_dbg(dev, "%s: sending reset for init.\n", __func__); 471 spin_lock(&idxd->cmd_lock); 472 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 473 474 while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) & 475 IDXD_CMDSTS_ACTIVE) 476 cpu_relax(); 477 spin_unlock(&idxd->cmd_lock); 478 return 0; 479 } 480 481 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand, 482 u32 *status) 483 { 484 union idxd_command_reg cmd; 485 DECLARE_COMPLETION_ONSTACK(done); 486 u32 stat; 487 488 if (idxd_device_is_halted(idxd)) { 489 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n"); 490 if (status) 491 *status = IDXD_CMDSTS_HW_ERR; 492 return; 493 } 494 495 memset(&cmd, 0, sizeof(cmd)); 496 cmd.cmd = cmd_code; 497 cmd.operand = operand; 498 cmd.int_req = 1; 499 500 spin_lock(&idxd->cmd_lock); 501 wait_event_lock_irq(idxd->cmd_waitq, 502 !test_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags), 503 idxd->cmd_lock); 504 505 dev_dbg(&idxd->pdev->dev, "%s: sending cmd: %#x op: %#x\n", 506 __func__, cmd_code, operand); 507 508 idxd->cmd_status = 0; 509 __set_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags); 510 idxd->cmd_done = &done; 511 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 512 513 /* 514 * After command submitted, release lock and go to sleep until 515 * the command completes via interrupt. 516 */ 517 spin_unlock(&idxd->cmd_lock); 518 wait_for_completion(&done); 519 stat = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET); 520 spin_lock(&idxd->cmd_lock); 521 if (status) 522 *status = stat; 523 idxd->cmd_status = stat & GENMASK(7, 0); 524 525 __clear_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags); 526 /* Wake up other pending commands */ 527 wake_up(&idxd->cmd_waitq); 528 spin_unlock(&idxd->cmd_lock); 529 } 530 531 int idxd_device_enable(struct idxd_device *idxd) 532 { 533 struct device *dev = &idxd->pdev->dev; 534 u32 status; 535 536 if (idxd_is_enabled(idxd)) { 537 dev_dbg(dev, "Device already enabled\n"); 538 return -ENXIO; 539 } 540 541 idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_DEVICE, 0, &status); 542 543 /* If the command is successful or if the device was enabled */ 544 if (status != IDXD_CMDSTS_SUCCESS && 545 status != IDXD_CMDSTS_ERR_DEV_ENABLED) { 546 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status); 547 return -ENXIO; 548 } 549 550 idxd->state = IDXD_DEV_ENABLED; 551 return 0; 552 } 553 554 int idxd_device_disable(struct idxd_device *idxd) 555 { 556 struct device *dev = &idxd->pdev->dev; 557 u32 status; 558 559 if (!idxd_is_enabled(idxd)) { 560 dev_dbg(dev, "Device is not enabled\n"); 561 return 0; 562 } 563 564 idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_DEVICE, 0, &status); 565 566 /* If the command is successful or if the device was disabled */ 567 if (status != IDXD_CMDSTS_SUCCESS && 568 !(status & IDXD_CMDSTS_ERR_DIS_DEV_EN)) { 569 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status); 570 return -ENXIO; 571 } 572 573 spin_lock(&idxd->dev_lock); 574 idxd_device_clear_state(idxd); 575 idxd->state = IDXD_DEV_DISABLED; 576 spin_unlock(&idxd->dev_lock); 577 return 0; 578 } 579 580 void idxd_device_reset(struct idxd_device *idxd) 581 { 582 idxd_cmd_exec(idxd, IDXD_CMD_RESET_DEVICE, 0, NULL); 583 spin_lock(&idxd->dev_lock); 584 idxd_device_clear_state(idxd); 585 idxd->state = IDXD_DEV_DISABLED; 586 spin_unlock(&idxd->dev_lock); 587 } 588 589 void idxd_device_drain_pasid(struct idxd_device *idxd, int pasid) 590 { 591 struct device *dev = &idxd->pdev->dev; 592 u32 operand; 593 594 operand = pasid; 595 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_DRAIN_PASID, operand); 596 idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_PASID, operand, NULL); 597 dev_dbg(dev, "pasid %d drained\n", pasid); 598 } 599 600 int idxd_device_request_int_handle(struct idxd_device *idxd, int idx, int *handle, 601 enum idxd_interrupt_type irq_type) 602 { 603 struct device *dev = &idxd->pdev->dev; 604 u32 operand, status; 605 606 if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE))) 607 return -EOPNOTSUPP; 608 609 dev_dbg(dev, "get int handle, idx %d\n", idx); 610 611 operand = idx & GENMASK(15, 0); 612 if (irq_type == IDXD_IRQ_IMS) 613 operand |= CMD_INT_HANDLE_IMS; 614 615 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_REQUEST_INT_HANDLE, operand); 616 617 idxd_cmd_exec(idxd, IDXD_CMD_REQUEST_INT_HANDLE, operand, &status); 618 619 if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) { 620 dev_dbg(dev, "request int handle failed: %#x\n", status); 621 return -ENXIO; 622 } 623 624 *handle = (status >> IDXD_CMDSTS_RES_SHIFT) & GENMASK(15, 0); 625 626 dev_dbg(dev, "int handle acquired: %u\n", *handle); 627 return 0; 628 } 629 630 int idxd_device_release_int_handle(struct idxd_device *idxd, int handle, 631 enum idxd_interrupt_type irq_type) 632 { 633 struct device *dev = &idxd->pdev->dev; 634 u32 operand, status; 635 union idxd_command_reg cmd; 636 637 if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_RELEASE_INT_HANDLE))) 638 return -EOPNOTSUPP; 639 640 dev_dbg(dev, "release int handle, handle %d\n", handle); 641 642 memset(&cmd, 0, sizeof(cmd)); 643 operand = handle & GENMASK(15, 0); 644 645 if (irq_type == IDXD_IRQ_IMS) 646 operand |= CMD_INT_HANDLE_IMS; 647 648 cmd.cmd = IDXD_CMD_RELEASE_INT_HANDLE; 649 cmd.operand = operand; 650 651 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_RELEASE_INT_HANDLE, operand); 652 653 spin_lock(&idxd->cmd_lock); 654 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 655 656 while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) & IDXD_CMDSTS_ACTIVE) 657 cpu_relax(); 658 status = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET); 659 spin_unlock(&idxd->cmd_lock); 660 661 if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) { 662 dev_dbg(dev, "release int handle failed: %#x\n", status); 663 return -ENXIO; 664 } 665 666 dev_dbg(dev, "int handle released.\n"); 667 return 0; 668 } 669 670 /* Device configuration bits */ 671 static void idxd_engines_clear_state(struct idxd_device *idxd) 672 { 673 struct idxd_engine *engine; 674 int i; 675 676 lockdep_assert_held(&idxd->dev_lock); 677 for (i = 0; i < idxd->max_engines; i++) { 678 engine = idxd->engines[i]; 679 engine->group = NULL; 680 } 681 } 682 683 static void idxd_groups_clear_state(struct idxd_device *idxd) 684 { 685 struct idxd_group *group; 686 int i; 687 688 lockdep_assert_held(&idxd->dev_lock); 689 for (i = 0; i < idxd->max_groups; i++) { 690 group = idxd->groups[i]; 691 memset(&group->grpcfg, 0, sizeof(group->grpcfg)); 692 group->num_engines = 0; 693 group->num_wqs = 0; 694 group->use_token_limit = false; 695 group->tokens_allowed = 0; 696 group->tokens_reserved = 0; 697 group->tc_a = -1; 698 group->tc_b = -1; 699 } 700 } 701 702 static void idxd_device_wqs_clear_state(struct idxd_device *idxd) 703 { 704 int i; 705 706 lockdep_assert_held(&idxd->dev_lock); 707 for (i = 0; i < idxd->max_wqs; i++) { 708 struct idxd_wq *wq = idxd->wqs[i]; 709 710 if (wq->state == IDXD_WQ_ENABLED) { 711 idxd_wq_disable_cleanup(wq); 712 wq->state = IDXD_WQ_DISABLED; 713 } 714 } 715 } 716 717 void idxd_device_clear_state(struct idxd_device *idxd) 718 { 719 idxd_groups_clear_state(idxd); 720 idxd_engines_clear_state(idxd); 721 idxd_device_wqs_clear_state(idxd); 722 } 723 724 void idxd_msix_perm_setup(struct idxd_device *idxd) 725 { 726 union msix_perm mperm; 727 int i, msixcnt; 728 729 msixcnt = pci_msix_vec_count(idxd->pdev); 730 if (msixcnt < 0) 731 return; 732 733 mperm.bits = 0; 734 mperm.pasid = idxd->pasid; 735 mperm.pasid_en = device_pasid_enabled(idxd); 736 for (i = 1; i < msixcnt; i++) 737 iowrite32(mperm.bits, idxd->reg_base + idxd->msix_perm_offset + i * 8); 738 } 739 740 void idxd_msix_perm_clear(struct idxd_device *idxd) 741 { 742 union msix_perm mperm; 743 int i, msixcnt; 744 745 msixcnt = pci_msix_vec_count(idxd->pdev); 746 if (msixcnt < 0) 747 return; 748 749 mperm.bits = 0; 750 for (i = 1; i < msixcnt; i++) 751 iowrite32(mperm.bits, idxd->reg_base + idxd->msix_perm_offset + i * 8); 752 } 753 754 static void idxd_group_config_write(struct idxd_group *group) 755 { 756 struct idxd_device *idxd = group->idxd; 757 struct device *dev = &idxd->pdev->dev; 758 int i; 759 u32 grpcfg_offset; 760 761 dev_dbg(dev, "Writing group %d cfg registers\n", group->id); 762 763 /* setup GRPWQCFG */ 764 for (i = 0; i < GRPWQCFG_STRIDES; i++) { 765 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i); 766 iowrite64(group->grpcfg.wqs[i], idxd->reg_base + grpcfg_offset); 767 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n", 768 group->id, i, grpcfg_offset, 769 ioread64(idxd->reg_base + grpcfg_offset)); 770 } 771 772 /* setup GRPENGCFG */ 773 grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id); 774 iowrite64(group->grpcfg.engines, idxd->reg_base + grpcfg_offset); 775 dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id, 776 grpcfg_offset, ioread64(idxd->reg_base + grpcfg_offset)); 777 778 /* setup GRPFLAGS */ 779 grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id); 780 iowrite32(group->grpcfg.flags.bits, idxd->reg_base + grpcfg_offset); 781 dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#x\n", 782 group->id, grpcfg_offset, 783 ioread32(idxd->reg_base + grpcfg_offset)); 784 } 785 786 static int idxd_groups_config_write(struct idxd_device *idxd) 787 788 { 789 union gencfg_reg reg; 790 int i; 791 struct device *dev = &idxd->pdev->dev; 792 793 /* Setup bandwidth token limit */ 794 if (idxd->token_limit) { 795 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET); 796 reg.token_limit = idxd->token_limit; 797 iowrite32(reg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET); 798 } 799 800 dev_dbg(dev, "GENCFG(%#x): %#x\n", IDXD_GENCFG_OFFSET, 801 ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET)); 802 803 for (i = 0; i < idxd->max_groups; i++) { 804 struct idxd_group *group = idxd->groups[i]; 805 806 idxd_group_config_write(group); 807 } 808 809 return 0; 810 } 811 812 static bool idxd_device_pasid_priv_enabled(struct idxd_device *idxd) 813 { 814 struct pci_dev *pdev = idxd->pdev; 815 816 if (pdev->pasid_enabled && (pdev->pasid_features & PCI_PASID_CAP_PRIV)) 817 return true; 818 return false; 819 } 820 821 static int idxd_wq_config_write(struct idxd_wq *wq) 822 { 823 struct idxd_device *idxd = wq->idxd; 824 struct device *dev = &idxd->pdev->dev; 825 u32 wq_offset; 826 int i; 827 828 if (!wq->group) 829 return 0; 830 831 /* 832 * Instead of memset the entire shadow copy of WQCFG, copy from the hardware after 833 * wq reset. This will copy back the sticky values that are present on some devices. 834 */ 835 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 836 wq_offset = WQCFG_OFFSET(idxd, wq->id, i); 837 wq->wqcfg->bits[i] = ioread32(idxd->reg_base + wq_offset); 838 } 839 840 /* byte 0-3 */ 841 wq->wqcfg->wq_size = wq->size; 842 843 if (wq->size == 0) { 844 idxd->cmd_status = IDXD_SCMD_WQ_NO_SIZE; 845 dev_warn(dev, "Incorrect work queue size: 0\n"); 846 return -EINVAL; 847 } 848 849 /* bytes 4-7 */ 850 wq->wqcfg->wq_thresh = wq->threshold; 851 852 /* byte 8-11 */ 853 if (wq_dedicated(wq)) 854 wq->wqcfg->mode = 1; 855 856 if (device_pasid_enabled(idxd)) { 857 wq->wqcfg->pasid_en = 1; 858 if (wq->type == IDXD_WQT_KERNEL && wq_dedicated(wq)) 859 wq->wqcfg->pasid = idxd->pasid; 860 } 861 862 /* 863 * Here the priv bit is set depending on the WQ type. priv = 1 if the 864 * WQ type is kernel to indicate privileged access. This setting only 865 * matters for dedicated WQ. According to the DSA spec: 866 * If the WQ is in dedicated mode, WQ PASID Enable is 1, and the 867 * Privileged Mode Enable field of the PCI Express PASID capability 868 * is 0, this field must be 0. 869 * 870 * In the case of a dedicated kernel WQ that is not able to support 871 * the PASID cap, then the configuration will be rejected. 872 */ 873 wq->wqcfg->priv = !!(wq->type == IDXD_WQT_KERNEL); 874 if (wq_dedicated(wq) && wq->wqcfg->pasid_en && 875 !idxd_device_pasid_priv_enabled(idxd) && 876 wq->type == IDXD_WQT_KERNEL) { 877 idxd->cmd_status = IDXD_SCMD_WQ_NO_PRIV; 878 return -EOPNOTSUPP; 879 } 880 881 wq->wqcfg->priority = wq->priority; 882 883 if (idxd->hw.gen_cap.block_on_fault && 884 test_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags)) 885 wq->wqcfg->bof = 1; 886 887 if (idxd->hw.wq_cap.wq_ats_support) 888 wq->wqcfg->wq_ats_disable = wq->ats_dis; 889 890 /* bytes 12-15 */ 891 wq->wqcfg->max_xfer_shift = ilog2(wq->max_xfer_bytes); 892 wq->wqcfg->max_batch_shift = ilog2(wq->max_batch_size); 893 894 dev_dbg(dev, "WQ %d CFGs\n", wq->id); 895 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 896 wq_offset = WQCFG_OFFSET(idxd, wq->id, i); 897 iowrite32(wq->wqcfg->bits[i], idxd->reg_base + wq_offset); 898 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", 899 wq->id, i, wq_offset, 900 ioread32(idxd->reg_base + wq_offset)); 901 } 902 903 return 0; 904 } 905 906 static int idxd_wqs_config_write(struct idxd_device *idxd) 907 { 908 int i, rc; 909 910 for (i = 0; i < idxd->max_wqs; i++) { 911 struct idxd_wq *wq = idxd->wqs[i]; 912 913 rc = idxd_wq_config_write(wq); 914 if (rc < 0) 915 return rc; 916 } 917 918 return 0; 919 } 920 921 static void idxd_group_flags_setup(struct idxd_device *idxd) 922 { 923 int i; 924 925 /* TC-A 0 and TC-B 1 should be defaults */ 926 for (i = 0; i < idxd->max_groups; i++) { 927 struct idxd_group *group = idxd->groups[i]; 928 929 if (group->tc_a == -1) 930 group->tc_a = group->grpcfg.flags.tc_a = 0; 931 else 932 group->grpcfg.flags.tc_a = group->tc_a; 933 if (group->tc_b == -1) 934 group->tc_b = group->grpcfg.flags.tc_b = 1; 935 else 936 group->grpcfg.flags.tc_b = group->tc_b; 937 group->grpcfg.flags.use_token_limit = group->use_token_limit; 938 group->grpcfg.flags.tokens_reserved = group->tokens_reserved; 939 if (group->tokens_allowed) 940 group->grpcfg.flags.tokens_allowed = 941 group->tokens_allowed; 942 else 943 group->grpcfg.flags.tokens_allowed = idxd->max_tokens; 944 } 945 } 946 947 static int idxd_engines_setup(struct idxd_device *idxd) 948 { 949 int i, engines = 0; 950 struct idxd_engine *eng; 951 struct idxd_group *group; 952 953 for (i = 0; i < idxd->max_groups; i++) { 954 group = idxd->groups[i]; 955 group->grpcfg.engines = 0; 956 } 957 958 for (i = 0; i < idxd->max_engines; i++) { 959 eng = idxd->engines[i]; 960 group = eng->group; 961 962 if (!group) 963 continue; 964 965 group->grpcfg.engines |= BIT(eng->id); 966 engines++; 967 } 968 969 if (!engines) 970 return -EINVAL; 971 972 return 0; 973 } 974 975 static int idxd_wqs_setup(struct idxd_device *idxd) 976 { 977 struct idxd_wq *wq; 978 struct idxd_group *group; 979 int i, j, configured = 0; 980 struct device *dev = &idxd->pdev->dev; 981 982 for (i = 0; i < idxd->max_groups; i++) { 983 group = idxd->groups[i]; 984 for (j = 0; j < 4; j++) 985 group->grpcfg.wqs[j] = 0; 986 } 987 988 for (i = 0; i < idxd->max_wqs; i++) { 989 wq = idxd->wqs[i]; 990 group = wq->group; 991 992 if (!wq->group) 993 continue; 994 if (!wq->size) 995 continue; 996 997 if (wq_shared(wq) && !device_swq_supported(idxd)) { 998 idxd->cmd_status = IDXD_SCMD_WQ_NO_SWQ_SUPPORT; 999 dev_warn(dev, "No shared wq support but configured.\n"); 1000 return -EINVAL; 1001 } 1002 1003 group->grpcfg.wqs[wq->id / 64] |= BIT(wq->id % 64); 1004 configured++; 1005 } 1006 1007 if (configured == 0) { 1008 idxd->cmd_status = IDXD_SCMD_WQ_NONE_CONFIGURED; 1009 return -EINVAL; 1010 } 1011 1012 return 0; 1013 } 1014 1015 int idxd_device_config(struct idxd_device *idxd) 1016 { 1017 int rc; 1018 1019 lockdep_assert_held(&idxd->dev_lock); 1020 rc = idxd_wqs_setup(idxd); 1021 if (rc < 0) 1022 return rc; 1023 1024 rc = idxd_engines_setup(idxd); 1025 if (rc < 0) 1026 return rc; 1027 1028 idxd_group_flags_setup(idxd); 1029 1030 rc = idxd_wqs_config_write(idxd); 1031 if (rc < 0) 1032 return rc; 1033 1034 rc = idxd_groups_config_write(idxd); 1035 if (rc < 0) 1036 return rc; 1037 1038 return 0; 1039 } 1040 1041 static int idxd_wq_load_config(struct idxd_wq *wq) 1042 { 1043 struct idxd_device *idxd = wq->idxd; 1044 struct device *dev = &idxd->pdev->dev; 1045 int wqcfg_offset; 1046 int i; 1047 1048 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, 0); 1049 memcpy_fromio(wq->wqcfg, idxd->reg_base + wqcfg_offset, idxd->wqcfg_size); 1050 1051 wq->size = wq->wqcfg->wq_size; 1052 wq->threshold = wq->wqcfg->wq_thresh; 1053 if (wq->wqcfg->priv) 1054 wq->type = IDXD_WQT_KERNEL; 1055 1056 /* The driver does not support shared WQ mode in read-only config yet */ 1057 if (wq->wqcfg->mode == 0 || wq->wqcfg->pasid_en) 1058 return -EOPNOTSUPP; 1059 1060 set_bit(WQ_FLAG_DEDICATED, &wq->flags); 1061 1062 wq->priority = wq->wqcfg->priority; 1063 1064 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 1065 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, i); 1066 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", wq->id, i, wqcfg_offset, wq->wqcfg->bits[i]); 1067 } 1068 1069 return 0; 1070 } 1071 1072 static void idxd_group_load_config(struct idxd_group *group) 1073 { 1074 struct idxd_device *idxd = group->idxd; 1075 struct device *dev = &idxd->pdev->dev; 1076 int i, j, grpcfg_offset; 1077 1078 /* 1079 * Load WQS bit fields 1080 * Iterate through all 256 bits 64 bits at a time 1081 */ 1082 for (i = 0; i < GRPWQCFG_STRIDES; i++) { 1083 struct idxd_wq *wq; 1084 1085 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i); 1086 group->grpcfg.wqs[i] = ioread64(idxd->reg_base + grpcfg_offset); 1087 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n", 1088 group->id, i, grpcfg_offset, group->grpcfg.wqs[i]); 1089 1090 if (i * 64 >= idxd->max_wqs) 1091 break; 1092 1093 /* Iterate through all 64 bits and check for wq set */ 1094 for (j = 0; j < 64; j++) { 1095 int id = i * 64 + j; 1096 1097 /* No need to check beyond max wqs */ 1098 if (id >= idxd->max_wqs) 1099 break; 1100 1101 /* Set group assignment for wq if wq bit is set */ 1102 if (group->grpcfg.wqs[i] & BIT(j)) { 1103 wq = idxd->wqs[id]; 1104 wq->group = group; 1105 } 1106 } 1107 } 1108 1109 grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id); 1110 group->grpcfg.engines = ioread64(idxd->reg_base + grpcfg_offset); 1111 dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id, 1112 grpcfg_offset, group->grpcfg.engines); 1113 1114 /* Iterate through all 64 bits to check engines set */ 1115 for (i = 0; i < 64; i++) { 1116 if (i >= idxd->max_engines) 1117 break; 1118 1119 if (group->grpcfg.engines & BIT(i)) { 1120 struct idxd_engine *engine = idxd->engines[i]; 1121 1122 engine->group = group; 1123 } 1124 } 1125 1126 grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id); 1127 group->grpcfg.flags.bits = ioread32(idxd->reg_base + grpcfg_offset); 1128 dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#x\n", 1129 group->id, grpcfg_offset, group->grpcfg.flags.bits); 1130 } 1131 1132 int idxd_device_load_config(struct idxd_device *idxd) 1133 { 1134 union gencfg_reg reg; 1135 int i, rc; 1136 1137 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET); 1138 idxd->token_limit = reg.token_limit; 1139 1140 for (i = 0; i < idxd->max_groups; i++) { 1141 struct idxd_group *group = idxd->groups[i]; 1142 1143 idxd_group_load_config(group); 1144 } 1145 1146 for (i = 0; i < idxd->max_wqs; i++) { 1147 struct idxd_wq *wq = idxd->wqs[i]; 1148 1149 rc = idxd_wq_load_config(wq); 1150 if (rc < 0) 1151 return rc; 1152 } 1153 1154 return 0; 1155 } 1156 1157 int __drv_enable_wq(struct idxd_wq *wq) 1158 { 1159 struct idxd_device *idxd = wq->idxd; 1160 struct device *dev = &idxd->pdev->dev; 1161 int rc = -ENXIO; 1162 1163 lockdep_assert_held(&wq->wq_lock); 1164 1165 if (idxd->state != IDXD_DEV_ENABLED) { 1166 idxd->cmd_status = IDXD_SCMD_DEV_NOT_ENABLED; 1167 goto err; 1168 } 1169 1170 if (wq->state != IDXD_WQ_DISABLED) { 1171 dev_dbg(dev, "wq %d already enabled.\n", wq->id); 1172 idxd->cmd_status = IDXD_SCMD_WQ_ENABLED; 1173 rc = -EBUSY; 1174 goto err; 1175 } 1176 1177 if (!wq->group) { 1178 dev_dbg(dev, "wq %d not attached to group.\n", wq->id); 1179 idxd->cmd_status = IDXD_SCMD_WQ_NO_GRP; 1180 goto err; 1181 } 1182 1183 if (strlen(wq->name) == 0) { 1184 idxd->cmd_status = IDXD_SCMD_WQ_NO_NAME; 1185 dev_dbg(dev, "wq %d name not set.\n", wq->id); 1186 goto err; 1187 } 1188 1189 /* Shared WQ checks */ 1190 if (wq_shared(wq)) { 1191 if (!device_swq_supported(idxd)) { 1192 idxd->cmd_status = IDXD_SCMD_WQ_NO_SVM; 1193 dev_dbg(dev, "PASID not enabled and shared wq.\n"); 1194 goto err; 1195 } 1196 /* 1197 * Shared wq with the threshold set to 0 means the user 1198 * did not set the threshold or transitioned from a 1199 * dedicated wq but did not set threshold. A value 1200 * of 0 would effectively disable the shared wq. The 1201 * driver does not allow a value of 0 to be set for 1202 * threshold via sysfs. 1203 */ 1204 if (wq->threshold == 0) { 1205 idxd->cmd_status = IDXD_SCMD_WQ_NO_THRESH; 1206 dev_dbg(dev, "Shared wq and threshold 0.\n"); 1207 goto err; 1208 } 1209 } 1210 1211 rc = 0; 1212 spin_lock(&idxd->dev_lock); 1213 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) 1214 rc = idxd_device_config(idxd); 1215 spin_unlock(&idxd->dev_lock); 1216 if (rc < 0) { 1217 dev_dbg(dev, "Writing wq %d config failed: %d\n", wq->id, rc); 1218 goto err; 1219 } 1220 1221 rc = idxd_wq_enable(wq); 1222 if (rc < 0) { 1223 dev_dbg(dev, "wq %d enabling failed: %d\n", wq->id, rc); 1224 goto err; 1225 } 1226 1227 rc = idxd_wq_map_portal(wq); 1228 if (rc < 0) { 1229 idxd->cmd_status = IDXD_SCMD_WQ_PORTAL_ERR; 1230 dev_dbg(dev, "wq %d portal mapping failed: %d\n", wq->id, rc); 1231 goto err_map_portal; 1232 } 1233 1234 wq->client_count = 0; 1235 return 0; 1236 1237 err_map_portal: 1238 rc = idxd_wq_disable(wq, false); 1239 if (rc < 0) 1240 dev_dbg(dev, "wq %s disable failed\n", dev_name(wq_confdev(wq))); 1241 err: 1242 return rc; 1243 } 1244 1245 int drv_enable_wq(struct idxd_wq *wq) 1246 { 1247 int rc; 1248 1249 mutex_lock(&wq->wq_lock); 1250 rc = __drv_enable_wq(wq); 1251 mutex_unlock(&wq->wq_lock); 1252 return rc; 1253 } 1254 1255 void __drv_disable_wq(struct idxd_wq *wq) 1256 { 1257 struct idxd_device *idxd = wq->idxd; 1258 struct device *dev = &idxd->pdev->dev; 1259 1260 lockdep_assert_held(&wq->wq_lock); 1261 1262 if (idxd_wq_refcount(wq)) 1263 dev_warn(dev, "Clients has claim on wq %d: %d\n", 1264 wq->id, idxd_wq_refcount(wq)); 1265 1266 idxd_wq_unmap_portal(wq); 1267 1268 idxd_wq_drain(wq); 1269 idxd_wq_reset(wq); 1270 1271 wq->client_count = 0; 1272 } 1273 1274 void drv_disable_wq(struct idxd_wq *wq) 1275 { 1276 mutex_lock(&wq->wq_lock); 1277 __drv_disable_wq(wq); 1278 mutex_unlock(&wq->wq_lock); 1279 } 1280 1281 int idxd_device_drv_probe(struct idxd_dev *idxd_dev) 1282 { 1283 struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev); 1284 int rc = 0; 1285 1286 /* 1287 * Device should be in disabled state for the idxd_drv to load. If it's in 1288 * enabled state, then the device was altered outside of driver's control. 1289 * If the state is in halted state, then we don't want to proceed. 1290 */ 1291 if (idxd->state != IDXD_DEV_DISABLED) { 1292 idxd->cmd_status = IDXD_SCMD_DEV_ENABLED; 1293 return -ENXIO; 1294 } 1295 1296 /* Device configuration */ 1297 spin_lock(&idxd->dev_lock); 1298 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) 1299 rc = idxd_device_config(idxd); 1300 spin_unlock(&idxd->dev_lock); 1301 if (rc < 0) 1302 return -ENXIO; 1303 1304 /* Start device */ 1305 rc = idxd_device_enable(idxd); 1306 if (rc < 0) 1307 return rc; 1308 1309 /* Setup DMA device without channels */ 1310 rc = idxd_register_dma_device(idxd); 1311 if (rc < 0) { 1312 idxd_device_disable(idxd); 1313 idxd->cmd_status = IDXD_SCMD_DEV_DMA_ERR; 1314 return rc; 1315 } 1316 1317 idxd->cmd_status = 0; 1318 return 0; 1319 } 1320 1321 void idxd_device_drv_remove(struct idxd_dev *idxd_dev) 1322 { 1323 struct device *dev = &idxd_dev->conf_dev; 1324 struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev); 1325 int i; 1326 1327 for (i = 0; i < idxd->max_wqs; i++) { 1328 struct idxd_wq *wq = idxd->wqs[i]; 1329 struct device *wq_dev = wq_confdev(wq); 1330 1331 if (wq->state == IDXD_WQ_DISABLED) 1332 continue; 1333 dev_warn(dev, "Active wq %d on disable %s.\n", i, dev_name(wq_dev)); 1334 device_release_driver(wq_dev); 1335 } 1336 1337 idxd_unregister_dma_device(idxd); 1338 idxd_device_disable(idxd); 1339 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) 1340 idxd_device_reset(idxd); 1341 } 1342 1343 static enum idxd_dev_type dev_types[] = { 1344 IDXD_DEV_DSA, 1345 IDXD_DEV_IAX, 1346 IDXD_DEV_NONE, 1347 }; 1348 1349 struct idxd_device_driver idxd_drv = { 1350 .type = dev_types, 1351 .probe = idxd_device_drv_probe, 1352 .remove = idxd_device_drv_remove, 1353 .name = "idxd", 1354 }; 1355 EXPORT_SYMBOL_GPL(idxd_drv); 1356