xref: /openbmc/linux/drivers/dma/dw/internal.h (revision ed4543328f7108e1047b83b96ca7f7208747d930)
1b466a37fSAndy Shevchenko /* SPDX-License-Identifier: GPL-2.0 */
29cade1a4SAndy Shevchenko /*
39cade1a4SAndy Shevchenko  * Driver for the Synopsys DesignWare DMA Controller
49cade1a4SAndy Shevchenko  *
59cade1a4SAndy Shevchenko  * Copyright (C) 2013 Intel Corporation
69cade1a4SAndy Shevchenko  */
79cade1a4SAndy Shevchenko 
82a52f6e4SAndy Shevchenko #ifndef _DMA_DW_INTERNAL_H
92a52f6e4SAndy Shevchenko #define _DMA_DW_INTERNAL_H
103d588f83SAndy Shevchenko 
113d588f83SAndy Shevchenko #include <linux/dma/dw.h>
129cade1a4SAndy Shevchenko 
139cade1a4SAndy Shevchenko #include "regs.h"
149cade1a4SAndy Shevchenko 
1569da8be9SAndy Shevchenko int do_dma_probe(struct dw_dma_chip *chip);
1669da8be9SAndy Shevchenko int do_dma_remove(struct dw_dma_chip *chip);
1769da8be9SAndy Shevchenko 
1869da8be9SAndy Shevchenko void do_dw_dma_on(struct dw_dma *dw);
1969da8be9SAndy Shevchenko void do_dw_dma_off(struct dw_dma *dw);
2069da8be9SAndy Shevchenko 
2169da8be9SAndy Shevchenko int do_dw_dma_disable(struct dw_dma_chip *chip);
2269da8be9SAndy Shevchenko int do_dw_dma_enable(struct dw_dma_chip *chip);
239cade1a4SAndy Shevchenko 
244d130de2SAndy Shevchenko extern bool dw_dma_filter(struct dma_chan *chan, void *param);
259cade1a4SAndy Shevchenko 
26b685fe26SAndy Shevchenko #ifdef CONFIG_ACPI
27b685fe26SAndy Shevchenko void dw_dma_acpi_controller_register(struct dw_dma *dw);
28b685fe26SAndy Shevchenko void dw_dma_acpi_controller_free(struct dw_dma *dw);
29b685fe26SAndy Shevchenko #else /* !CONFIG_ACPI */
dw_dma_acpi_controller_register(struct dw_dma * dw)30b685fe26SAndy Shevchenko static inline void dw_dma_acpi_controller_register(struct dw_dma *dw) {}
dw_dma_acpi_controller_free(struct dw_dma * dw)31b685fe26SAndy Shevchenko static inline void dw_dma_acpi_controller_free(struct dw_dma *dw) {}
32b685fe26SAndy Shevchenko #endif /* !CONFIG_ACPI */
33b685fe26SAndy Shevchenko 
34f5e84eaeSAndy Shevchenko struct platform_device;
35f5e84eaeSAndy Shevchenko 
36f5e84eaeSAndy Shevchenko #ifdef CONFIG_OF
37f5e84eaeSAndy Shevchenko struct dw_dma_platform_data *dw_dma_parse_dt(struct platform_device *pdev);
38f5e84eaeSAndy Shevchenko void dw_dma_of_controller_register(struct dw_dma *dw);
39f5e84eaeSAndy Shevchenko void dw_dma_of_controller_free(struct dw_dma *dw);
40f5e84eaeSAndy Shevchenko #else
dw_dma_parse_dt(struct platform_device * pdev)41f5e84eaeSAndy Shevchenko static inline struct dw_dma_platform_data *dw_dma_parse_dt(struct platform_device *pdev)
42f5e84eaeSAndy Shevchenko {
43f5e84eaeSAndy Shevchenko 	return NULL;
44f5e84eaeSAndy Shevchenko }
dw_dma_of_controller_register(struct dw_dma * dw)45f5e84eaeSAndy Shevchenko static inline void dw_dma_of_controller_register(struct dw_dma *dw) {}
dw_dma_of_controller_free(struct dw_dma * dw)46f5e84eaeSAndy Shevchenko static inline void dw_dma_of_controller_free(struct dw_dma *dw) {}
47f5e84eaeSAndy Shevchenko #endif
48f5e84eaeSAndy Shevchenko 
49ae923c91SAndy Shevchenko struct dw_dma_chip_pdata {
50ae923c91SAndy Shevchenko 	const struct dw_dma_platform_data *pdata;
51ae923c91SAndy Shevchenko 	int (*probe)(struct dw_dma_chip *chip);
52ae923c91SAndy Shevchenko 	int (*remove)(struct dw_dma_chip *chip);
53ae923c91SAndy Shevchenko 	struct dw_dma_chip *chip;
54*8cf5aa06SAndy Shevchenko 	u8 m_master;
55*8cf5aa06SAndy Shevchenko 	u8 p_master;
56ae923c91SAndy Shevchenko };
57ae923c91SAndy Shevchenko 
58ae923c91SAndy Shevchenko static __maybe_unused const struct dw_dma_chip_pdata dw_dma_chip_pdata = {
59ae923c91SAndy Shevchenko 	.probe = dw_dma_probe,
60ae923c91SAndy Shevchenko 	.remove = dw_dma_remove,
61*8cf5aa06SAndy Shevchenko 	.m_master = 0,
62*8cf5aa06SAndy Shevchenko 	.p_master = 1,
63ae923c91SAndy Shevchenko };
64ae923c91SAndy Shevchenko 
65ae923c91SAndy Shevchenko static const struct dw_dma_platform_data idma32_pdata = {
66ae923c91SAndy Shevchenko 	.nr_channels = 8,
67ae923c91SAndy Shevchenko 	.chan_allocation_order = CHAN_ALLOCATION_ASCENDING,
68ae923c91SAndy Shevchenko 	.chan_priority = CHAN_PRIORITY_ASCENDING,
69ae923c91SAndy Shevchenko 	.block_size = 131071,
70ae923c91SAndy Shevchenko 	.nr_masters = 1,
71ae923c91SAndy Shevchenko 	.data_width = {4},
72ae923c91SAndy Shevchenko 	.multi_block = {1, 1, 1, 1, 1, 1, 1, 1},
73ae923c91SAndy Shevchenko };
74ae923c91SAndy Shevchenko 
75ae923c91SAndy Shevchenko static __maybe_unused const struct dw_dma_chip_pdata idma32_chip_pdata = {
76ae923c91SAndy Shevchenko 	.pdata = &idma32_pdata,
77ae923c91SAndy Shevchenko 	.probe = idma32_dma_probe,
78ae923c91SAndy Shevchenko 	.remove = idma32_dma_remove,
79*8cf5aa06SAndy Shevchenko 	.m_master = 0,
80*8cf5aa06SAndy Shevchenko 	.p_master = 0,
81ae923c91SAndy Shevchenko };
82ae923c91SAndy Shevchenko 
83fe364a7dSAndy Shevchenko static const struct dw_dma_platform_data xbar_pdata = {
84fe364a7dSAndy Shevchenko 	.nr_channels = 8,
85fe364a7dSAndy Shevchenko 	.chan_allocation_order = CHAN_ALLOCATION_ASCENDING,
86fe364a7dSAndy Shevchenko 	.chan_priority = CHAN_PRIORITY_ASCENDING,
87fe364a7dSAndy Shevchenko 	.block_size = 131071,
88fe364a7dSAndy Shevchenko 	.nr_masters = 1,
89fe364a7dSAndy Shevchenko 	.data_width = {4},
90fe364a7dSAndy Shevchenko 	.quirks = DW_DMA_QUIRK_XBAR_PRESENT,
91fe364a7dSAndy Shevchenko };
92fe364a7dSAndy Shevchenko 
93fe364a7dSAndy Shevchenko static __maybe_unused const struct dw_dma_chip_pdata xbar_chip_pdata = {
94fe364a7dSAndy Shevchenko 	.pdata = &xbar_pdata,
95fe364a7dSAndy Shevchenko 	.probe = idma32_dma_probe,
96fe364a7dSAndy Shevchenko 	.remove = idma32_dma_remove,
97*8cf5aa06SAndy Shevchenko 	.m_master = 0,
98*8cf5aa06SAndy Shevchenko 	.p_master = 0,
99fe364a7dSAndy Shevchenko };
100fe364a7dSAndy Shevchenko 
1012a52f6e4SAndy Shevchenko #endif /* _DMA_DW_INTERNAL_H */
102