161a76496SAndy Shevchenko# 261a76496SAndy Shevchenko# DMA engine configuration for dw 361a76496SAndy Shevchenko# 461a76496SAndy Shevchenko 59cade1a4SAndy Shevchenkoconfig DW_DMAC_CORE 661a76496SAndy Shevchenko tristate "Synopsys DesignWare AHB DMA support" 761a76496SAndy Shevchenko depends on GENERIC_HARDIRQS 861a76496SAndy Shevchenko select DMA_ENGINE 99cade1a4SAndy Shevchenko 109cade1a4SAndy Shevchenkoconfig DW_DMAC 119cade1a4SAndy Shevchenko tristate "Synopsys DesignWare AHB DMA platform driver" 129cade1a4SAndy Shevchenko select DW_DMAC_CORE 1361a76496SAndy Shevchenko default y if CPU_AT32AP7000 1461a76496SAndy Shevchenko help 1561a76496SAndy Shevchenko Support the Synopsys DesignWare AHB DMA controller. This 1661a76496SAndy Shevchenko can be integrated in chips such as the Atmel AT32ap7000. 1761a76496SAndy Shevchenko 18*fed42c19SAndy Shevchenkoconfig DW_DMAC_PCI 19*fed42c19SAndy Shevchenko tristate "Synopsys DesignWare AHB DMA PCI driver" 20*fed42c19SAndy Shevchenko depends on PCI 21*fed42c19SAndy Shevchenko select DW_DMAC_CORE 22*fed42c19SAndy Shevchenko help 23*fed42c19SAndy Shevchenko Support the Synopsys DesignWare AHB DMA controller on the 24*fed42c19SAndy Shevchenko platfroms that enumerate it as a PCI device. For example, 25*fed42c19SAndy Shevchenko Intel Medfield has integrated this GPDMA controller. 26*fed42c19SAndy Shevchenko 2761a76496SAndy Shevchenkoconfig DW_DMAC_BIG_ENDIAN_IO 2861a76496SAndy Shevchenko bool "Use big endian I/O register access" 2961a76496SAndy Shevchenko default y if AVR32 309cade1a4SAndy Shevchenko depends on DW_DMAC_CORE 3161a76496SAndy Shevchenko help 3261a76496SAndy Shevchenko Say yes here to use big endian I/O access when reading and writing 3361a76496SAndy Shevchenko to the DMA controller registers. This is needed on some platforms, 3461a76496SAndy Shevchenko like the Atmel AVR32 architecture. 3561a76496SAndy Shevchenko 3661a76496SAndy Shevchenko If unsure, use the default setting. 37