161a76496SAndy Shevchenko# 261a76496SAndy Shevchenko# DMA engine configuration for dw 361a76496SAndy Shevchenko# 461a76496SAndy Shevchenko 5*9cade1a4SAndy Shevchenkoconfig DW_DMAC_CORE 661a76496SAndy Shevchenko tristate "Synopsys DesignWare AHB DMA support" 761a76496SAndy Shevchenko depends on GENERIC_HARDIRQS 861a76496SAndy Shevchenko select DMA_ENGINE 9*9cade1a4SAndy Shevchenko 10*9cade1a4SAndy Shevchenkoconfig DW_DMAC 11*9cade1a4SAndy Shevchenko tristate "Synopsys DesignWare AHB DMA platform driver" 12*9cade1a4SAndy Shevchenko select DW_DMAC_CORE 1361a76496SAndy Shevchenko default y if CPU_AT32AP7000 1461a76496SAndy Shevchenko help 1561a76496SAndy Shevchenko Support the Synopsys DesignWare AHB DMA controller. This 1661a76496SAndy Shevchenko can be integrated in chips such as the Atmel AT32ap7000. 1761a76496SAndy Shevchenko 1861a76496SAndy Shevchenkoconfig DW_DMAC_BIG_ENDIAN_IO 1961a76496SAndy Shevchenko bool "Use big endian I/O register access" 2061a76496SAndy Shevchenko default y if AVR32 21*9cade1a4SAndy Shevchenko depends on DW_DMAC_CORE 2261a76496SAndy Shevchenko help 2361a76496SAndy Shevchenko Say yes here to use big endian I/O access when reading and writing 2461a76496SAndy Shevchenko to the DMA controller registers. This is needed on some platforms, 2561a76496SAndy Shevchenko like the Atmel AVR32 architecture. 2661a76496SAndy Shevchenko 2761a76496SAndy Shevchenko If unsure, use the default setting. 28