1*61a76496SAndy Shevchenko# 2*61a76496SAndy Shevchenko# DMA engine configuration for dw 3*61a76496SAndy Shevchenko# 4*61a76496SAndy Shevchenko 5*61a76496SAndy Shevchenkoconfig DW_DMAC 6*61a76496SAndy Shevchenko tristate "Synopsys DesignWare AHB DMA support" 7*61a76496SAndy Shevchenko depends on GENERIC_HARDIRQS 8*61a76496SAndy Shevchenko select DMA_ENGINE 9*61a76496SAndy Shevchenko default y if CPU_AT32AP7000 10*61a76496SAndy Shevchenko help 11*61a76496SAndy Shevchenko Support the Synopsys DesignWare AHB DMA controller. This 12*61a76496SAndy Shevchenko can be integrated in chips such as the Atmel AT32ap7000. 13*61a76496SAndy Shevchenko 14*61a76496SAndy Shevchenkoconfig DW_DMAC_BIG_ENDIAN_IO 15*61a76496SAndy Shevchenko bool "Use big endian I/O register access" 16*61a76496SAndy Shevchenko default y if AVR32 17*61a76496SAndy Shevchenko depends on DW_DMAC 18*61a76496SAndy Shevchenko help 19*61a76496SAndy Shevchenko Say yes here to use big endian I/O access when reading and writing 20*61a76496SAndy Shevchenko to the DMA controller registers. This is needed on some platforms, 21*61a76496SAndy Shevchenko like the Atmel AVR32 architecture. 22*61a76496SAndy Shevchenko 23*61a76496SAndy Shevchenko If unsure, use the default setting. 24