1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ 3 #include <linux/io-64-nonatomic-lo-hi.h> 4 #include <linux/moduleparam.h> 5 #include <linux/module.h> 6 #include <linux/delay.h> 7 #include <linux/sizes.h> 8 #include <linux/mutex.h> 9 #include <linux/list.h> 10 #include <linux/pci.h> 11 #include <linux/aer.h> 12 #include <linux/io.h> 13 #include "cxlmem.h" 14 #include "cxlpci.h" 15 #include "cxl.h" 16 17 /** 18 * DOC: cxl pci 19 * 20 * This implements the PCI exclusive functionality for a CXL device as it is 21 * defined by the Compute Express Link specification. CXL devices may surface 22 * certain functionality even if it isn't CXL enabled. While this driver is 23 * focused around the PCI specific aspects of a CXL device, it binds to the 24 * specific CXL memory device class code, and therefore the implementation of 25 * cxl_pci is focused around CXL memory devices. 26 * 27 * The driver has several responsibilities, mainly: 28 * - Create the memX device and register on the CXL bus. 29 * - Enumerate device's register interface and map them. 30 * - Registers nvdimm bridge device with cxl_core. 31 * - Registers a CXL mailbox with cxl_core. 32 */ 33 34 #define cxl_doorbell_busy(cxlds) \ 35 (readl((cxlds)->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET) & \ 36 CXLDEV_MBOX_CTRL_DOORBELL) 37 38 /* CXL 2.0 - 8.2.8.4 */ 39 #define CXL_MAILBOX_TIMEOUT_MS (2 * HZ) 40 41 /* 42 * CXL 2.0 ECN "Add Mailbox Ready Time" defines a capability field to 43 * dictate how long to wait for the mailbox to become ready. The new 44 * field allows the device to tell software the amount of time to wait 45 * before mailbox ready. This field per the spec theoretically allows 46 * for up to 255 seconds. 255 seconds is unreasonably long, its longer 47 * than the maximum SATA port link recovery wait. Default to 60 seconds 48 * until someone builds a CXL device that needs more time in practice. 49 */ 50 static unsigned short mbox_ready_timeout = 60; 51 module_param(mbox_ready_timeout, ushort, 0644); 52 MODULE_PARM_DESC(mbox_ready_timeout, "seconds to wait for mailbox ready"); 53 54 static int cxl_pci_mbox_wait_for_doorbell(struct cxl_dev_state *cxlds) 55 { 56 const unsigned long start = jiffies; 57 unsigned long end = start; 58 59 while (cxl_doorbell_busy(cxlds)) { 60 end = jiffies; 61 62 if (time_after(end, start + CXL_MAILBOX_TIMEOUT_MS)) { 63 /* Check again in case preempted before timeout test */ 64 if (!cxl_doorbell_busy(cxlds)) 65 break; 66 return -ETIMEDOUT; 67 } 68 cpu_relax(); 69 } 70 71 dev_dbg(cxlds->dev, "Doorbell wait took %dms", 72 jiffies_to_msecs(end) - jiffies_to_msecs(start)); 73 return 0; 74 } 75 76 #define cxl_err(dev, status, msg) \ 77 dev_err_ratelimited(dev, msg ", device state %s%s\n", \ 78 status & CXLMDEV_DEV_FATAL ? " fatal" : "", \ 79 status & CXLMDEV_FW_HALT ? " firmware-halt" : "") 80 81 #define cxl_cmd_err(dev, cmd, status, msg) \ 82 dev_err_ratelimited(dev, msg " (opcode: %#x), device state %s%s\n", \ 83 (cmd)->opcode, \ 84 status & CXLMDEV_DEV_FATAL ? " fatal" : "", \ 85 status & CXLMDEV_FW_HALT ? " firmware-halt" : "") 86 87 struct cxl_dev_id { 88 struct cxl_dev_state *cxlds; 89 }; 90 91 static int cxl_request_irq(struct cxl_dev_state *cxlds, int irq, 92 irq_handler_t handler, irq_handler_t thread_fn) 93 { 94 struct device *dev = cxlds->dev; 95 struct cxl_dev_id *dev_id; 96 97 /* dev_id must be globally unique and must contain the cxlds */ 98 dev_id = devm_kzalloc(dev, sizeof(*dev_id), GFP_KERNEL); 99 if (!dev_id) 100 return -ENOMEM; 101 dev_id->cxlds = cxlds; 102 103 return devm_request_threaded_irq(dev, irq, handler, thread_fn, 104 IRQF_SHARED | IRQF_ONESHOT, 105 NULL, dev_id); 106 } 107 108 static bool cxl_mbox_background_complete(struct cxl_dev_state *cxlds) 109 { 110 u64 reg; 111 112 reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_BG_CMD_STATUS_OFFSET); 113 return FIELD_GET(CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK, reg) == 100; 114 } 115 116 static irqreturn_t cxl_pci_mbox_irq(int irq, void *id) 117 { 118 u64 reg; 119 u16 opcode; 120 struct cxl_dev_id *dev_id = id; 121 struct cxl_dev_state *cxlds = dev_id->cxlds; 122 123 if (!cxl_mbox_background_complete(cxlds)) 124 return IRQ_NONE; 125 126 reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_BG_CMD_STATUS_OFFSET); 127 opcode = FIELD_GET(CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK, reg); 128 if (opcode == CXL_MBOX_OP_SANITIZE) { 129 if (cxlds->security.sanitize_node) 130 sysfs_notify_dirent(cxlds->security.sanitize_node); 131 132 dev_dbg(cxlds->dev, "Sanitization operation ended\n"); 133 } else { 134 /* short-circuit the wait in __cxl_pci_mbox_send_cmd() */ 135 rcuwait_wake_up(&cxlds->mbox_wait); 136 } 137 138 return IRQ_HANDLED; 139 } 140 141 /* 142 * Sanitization operation polling mode. 143 */ 144 static void cxl_mbox_sanitize_work(struct work_struct *work) 145 { 146 struct cxl_dev_state *cxlds; 147 148 cxlds = container_of(work, 149 struct cxl_dev_state, security.poll_dwork.work); 150 151 mutex_lock(&cxlds->mbox_mutex); 152 if (cxl_mbox_background_complete(cxlds)) { 153 cxlds->security.poll_tmo_secs = 0; 154 put_device(cxlds->dev); 155 156 if (cxlds->security.sanitize_node) 157 sysfs_notify_dirent(cxlds->security.sanitize_node); 158 159 dev_dbg(cxlds->dev, "Sanitization operation ended\n"); 160 } else { 161 int timeout = cxlds->security.poll_tmo_secs + 10; 162 163 cxlds->security.poll_tmo_secs = min(15 * 60, timeout); 164 queue_delayed_work(system_wq, &cxlds->security.poll_dwork, 165 timeout * HZ); 166 } 167 mutex_unlock(&cxlds->mbox_mutex); 168 } 169 170 /** 171 * __cxl_pci_mbox_send_cmd() - Execute a mailbox command 172 * @cxlds: The device state to communicate with. 173 * @mbox_cmd: Command to send to the memory device. 174 * 175 * Context: Any context. Expects mbox_mutex to be held. 176 * Return: -ETIMEDOUT if timeout occurred waiting for completion. 0 on success. 177 * Caller should check the return code in @mbox_cmd to make sure it 178 * succeeded. 179 * 180 * This is a generic form of the CXL mailbox send command thus only using the 181 * registers defined by the mailbox capability ID - CXL 2.0 8.2.8.4. Memory 182 * devices, and perhaps other types of CXL devices may have further information 183 * available upon error conditions. Driver facilities wishing to send mailbox 184 * commands should use the wrapper command. 185 * 186 * The CXL spec allows for up to two mailboxes. The intention is for the primary 187 * mailbox to be OS controlled and the secondary mailbox to be used by system 188 * firmware. This allows the OS and firmware to communicate with the device and 189 * not need to coordinate with each other. The driver only uses the primary 190 * mailbox. 191 */ 192 static int __cxl_pci_mbox_send_cmd(struct cxl_dev_state *cxlds, 193 struct cxl_mbox_cmd *mbox_cmd) 194 { 195 void __iomem *payload = cxlds->regs.mbox + CXLDEV_MBOX_PAYLOAD_OFFSET; 196 struct device *dev = cxlds->dev; 197 u64 cmd_reg, status_reg; 198 size_t out_len; 199 int rc; 200 201 lockdep_assert_held(&cxlds->mbox_mutex); 202 203 /* 204 * Here are the steps from 8.2.8.4 of the CXL 2.0 spec. 205 * 1. Caller reads MB Control Register to verify doorbell is clear 206 * 2. Caller writes Command Register 207 * 3. Caller writes Command Payload Registers if input payload is non-empty 208 * 4. Caller writes MB Control Register to set doorbell 209 * 5. Caller either polls for doorbell to be clear or waits for interrupt if configured 210 * 6. Caller reads MB Status Register to fetch Return code 211 * 7. If command successful, Caller reads Command Register to get Payload Length 212 * 8. If output payload is non-empty, host reads Command Payload Registers 213 * 214 * Hardware is free to do whatever it wants before the doorbell is rung, 215 * and isn't allowed to change anything after it clears the doorbell. As 216 * such, steps 2 and 3 can happen in any order, and steps 6, 7, 8 can 217 * also happen in any order (though some orders might not make sense). 218 */ 219 220 /* #1 */ 221 if (cxl_doorbell_busy(cxlds)) { 222 u64 md_status = 223 readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); 224 225 cxl_cmd_err(cxlds->dev, mbox_cmd, md_status, 226 "mailbox queue busy"); 227 return -EBUSY; 228 } 229 230 /* 231 * With sanitize polling, hardware might be done and the poller still 232 * not be in sync. Ensure no new command comes in until so. Keep the 233 * hardware semantics and only allow device health status. 234 */ 235 if (cxlds->security.poll_tmo_secs > 0) { 236 if (mbox_cmd->opcode != CXL_MBOX_OP_GET_HEALTH_INFO) 237 return -EBUSY; 238 } 239 240 cmd_reg = FIELD_PREP(CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK, 241 mbox_cmd->opcode); 242 if (mbox_cmd->size_in) { 243 if (WARN_ON(!mbox_cmd->payload_in)) 244 return -EINVAL; 245 246 cmd_reg |= FIELD_PREP(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, 247 mbox_cmd->size_in); 248 memcpy_toio(payload, mbox_cmd->payload_in, mbox_cmd->size_in); 249 } 250 251 /* #2, #3 */ 252 writeq(cmd_reg, cxlds->regs.mbox + CXLDEV_MBOX_CMD_OFFSET); 253 254 /* #4 */ 255 dev_dbg(dev, "Sending command: 0x%04x\n", mbox_cmd->opcode); 256 writel(CXLDEV_MBOX_CTRL_DOORBELL, 257 cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); 258 259 /* #5 */ 260 rc = cxl_pci_mbox_wait_for_doorbell(cxlds); 261 if (rc == -ETIMEDOUT) { 262 u64 md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); 263 264 cxl_cmd_err(cxlds->dev, mbox_cmd, md_status, "mailbox timeout"); 265 return rc; 266 } 267 268 /* #6 */ 269 status_reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_STATUS_OFFSET); 270 mbox_cmd->return_code = 271 FIELD_GET(CXLDEV_MBOX_STATUS_RET_CODE_MASK, status_reg); 272 273 /* 274 * Handle the background command in a synchronous manner. 275 * 276 * All other mailbox commands will serialize/queue on the mbox_mutex, 277 * which we currently hold. Furthermore this also guarantees that 278 * cxl_mbox_background_complete() checks are safe amongst each other, 279 * in that no new bg operation can occur in between. 280 * 281 * Background operations are timesliced in accordance with the nature 282 * of the command. In the event of timeout, the mailbox state is 283 * indeterminate until the next successful command submission and the 284 * driver can get back in sync with the hardware state. 285 */ 286 if (mbox_cmd->return_code == CXL_MBOX_CMD_RC_BACKGROUND) { 287 u64 bg_status_reg; 288 int i, timeout; 289 290 /* 291 * Sanitization is a special case which monopolizes the device 292 * and cannot be timesliced. Handle asynchronously instead, 293 * and allow userspace to poll(2) for completion. 294 */ 295 if (mbox_cmd->opcode == CXL_MBOX_OP_SANITIZE) { 296 if (cxlds->security.poll_tmo_secs != -1) { 297 /* hold the device throughout */ 298 get_device(cxlds->dev); 299 300 /* give first timeout a second */ 301 timeout = 1; 302 cxlds->security.poll_tmo_secs = timeout; 303 queue_delayed_work(system_wq, 304 &cxlds->security.poll_dwork, 305 timeout * HZ); 306 } 307 308 dev_dbg(dev, "Sanitization operation started\n"); 309 goto success; 310 } 311 312 dev_dbg(dev, "Mailbox background operation (0x%04x) started\n", 313 mbox_cmd->opcode); 314 315 timeout = mbox_cmd->poll_interval_ms; 316 for (i = 0; i < mbox_cmd->poll_count; i++) { 317 if (rcuwait_wait_event_timeout(&cxlds->mbox_wait, 318 cxl_mbox_background_complete(cxlds), 319 TASK_UNINTERRUPTIBLE, 320 msecs_to_jiffies(timeout)) > 0) 321 break; 322 } 323 324 if (!cxl_mbox_background_complete(cxlds)) { 325 dev_err(dev, "timeout waiting for background (%d ms)\n", 326 timeout * mbox_cmd->poll_count); 327 return -ETIMEDOUT; 328 } 329 330 bg_status_reg = readq(cxlds->regs.mbox + 331 CXLDEV_MBOX_BG_CMD_STATUS_OFFSET); 332 mbox_cmd->return_code = 333 FIELD_GET(CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK, 334 bg_status_reg); 335 dev_dbg(dev, 336 "Mailbox background operation (0x%04x) completed\n", 337 mbox_cmd->opcode); 338 } 339 340 if (mbox_cmd->return_code != CXL_MBOX_CMD_RC_SUCCESS) { 341 dev_dbg(dev, "Mailbox operation had an error: %s\n", 342 cxl_mbox_cmd_rc2str(mbox_cmd)); 343 return 0; /* completed but caller must check return_code */ 344 } 345 346 success: 347 /* #7 */ 348 cmd_reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_CMD_OFFSET); 349 out_len = FIELD_GET(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, cmd_reg); 350 351 /* #8 */ 352 if (out_len && mbox_cmd->payload_out) { 353 /* 354 * Sanitize the copy. If hardware misbehaves, out_len per the 355 * spec can actually be greater than the max allowed size (21 356 * bits available but spec defined 1M max). The caller also may 357 * have requested less data than the hardware supplied even 358 * within spec. 359 */ 360 size_t n = min3(mbox_cmd->size_out, cxlds->payload_size, out_len); 361 362 memcpy_fromio(mbox_cmd->payload_out, payload, n); 363 mbox_cmd->size_out = n; 364 } else { 365 mbox_cmd->size_out = 0; 366 } 367 368 return 0; 369 } 370 371 static int cxl_pci_mbox_send(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd) 372 { 373 int rc; 374 375 mutex_lock_io(&cxlds->mbox_mutex); 376 rc = __cxl_pci_mbox_send_cmd(cxlds, cmd); 377 mutex_unlock(&cxlds->mbox_mutex); 378 379 return rc; 380 } 381 382 static int cxl_pci_setup_mailbox(struct cxl_dev_state *cxlds) 383 { 384 const int cap = readl(cxlds->regs.mbox + CXLDEV_MBOX_CAPS_OFFSET); 385 unsigned long timeout; 386 u64 md_status; 387 388 timeout = jiffies + mbox_ready_timeout * HZ; 389 do { 390 md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); 391 if (md_status & CXLMDEV_MBOX_IF_READY) 392 break; 393 if (msleep_interruptible(100)) 394 break; 395 } while (!time_after(jiffies, timeout)); 396 397 if (!(md_status & CXLMDEV_MBOX_IF_READY)) { 398 cxl_err(cxlds->dev, md_status, 399 "timeout awaiting mailbox ready"); 400 return -ETIMEDOUT; 401 } 402 403 /* 404 * A command may be in flight from a previous driver instance, 405 * think kexec, do one doorbell wait so that 406 * __cxl_pci_mbox_send_cmd() can assume that it is the only 407 * source for future doorbell busy events. 408 */ 409 if (cxl_pci_mbox_wait_for_doorbell(cxlds) != 0) { 410 cxl_err(cxlds->dev, md_status, "timeout awaiting mailbox idle"); 411 return -ETIMEDOUT; 412 } 413 414 cxlds->mbox_send = cxl_pci_mbox_send; 415 cxlds->payload_size = 416 1 << FIELD_GET(CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK, cap); 417 418 /* 419 * CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register 420 * 421 * If the size is too small, mandatory commands will not work and so 422 * there's no point in going forward. If the size is too large, there's 423 * no harm is soft limiting it. 424 */ 425 cxlds->payload_size = min_t(size_t, cxlds->payload_size, SZ_1M); 426 if (cxlds->payload_size < 256) { 427 dev_err(cxlds->dev, "Mailbox is too small (%zub)", 428 cxlds->payload_size); 429 return -ENXIO; 430 } 431 432 dev_dbg(cxlds->dev, "Mailbox payload sized %zu", 433 cxlds->payload_size); 434 435 rcuwait_init(&cxlds->mbox_wait); 436 437 if (cap & CXLDEV_MBOX_CAP_BG_CMD_IRQ) { 438 u32 ctrl; 439 int irq, msgnum; 440 struct pci_dev *pdev = to_pci_dev(cxlds->dev); 441 442 msgnum = FIELD_GET(CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK, cap); 443 irq = pci_irq_vector(pdev, msgnum); 444 if (irq < 0) 445 goto mbox_poll; 446 447 if (cxl_request_irq(cxlds, irq, cxl_pci_mbox_irq, NULL)) 448 goto mbox_poll; 449 450 /* enable background command mbox irq support */ 451 ctrl = readl(cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); 452 ctrl |= CXLDEV_MBOX_CTRL_BG_CMD_IRQ; 453 writel(ctrl, cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); 454 455 return 0; 456 } 457 458 mbox_poll: 459 cxlds->security.poll = true; 460 INIT_DELAYED_WORK(&cxlds->security.poll_dwork, cxl_mbox_sanitize_work); 461 462 dev_dbg(cxlds->dev, "Mailbox interrupts are unsupported"); 463 return 0; 464 } 465 466 static int cxl_map_regblock(struct pci_dev *pdev, struct cxl_register_map *map) 467 { 468 struct device *dev = &pdev->dev; 469 470 map->base = ioremap(map->resource, map->max_size); 471 if (!map->base) { 472 dev_err(dev, "failed to map registers\n"); 473 return -ENOMEM; 474 } 475 476 dev_dbg(dev, "Mapped CXL Memory Device resource %pa\n", &map->resource); 477 return 0; 478 } 479 480 static void cxl_unmap_regblock(struct pci_dev *pdev, 481 struct cxl_register_map *map) 482 { 483 iounmap(map->base); 484 map->base = NULL; 485 } 486 487 static int cxl_probe_regs(struct pci_dev *pdev, struct cxl_register_map *map) 488 { 489 struct cxl_component_reg_map *comp_map; 490 struct cxl_device_reg_map *dev_map; 491 struct device *dev = &pdev->dev; 492 void __iomem *base = map->base; 493 494 switch (map->reg_type) { 495 case CXL_REGLOC_RBI_COMPONENT: 496 comp_map = &map->component_map; 497 cxl_probe_component_regs(dev, base, comp_map); 498 if (!comp_map->hdm_decoder.valid) { 499 dev_err(dev, "HDM decoder registers not found\n"); 500 return -ENXIO; 501 } 502 503 if (!comp_map->ras.valid) 504 dev_dbg(dev, "RAS registers not found\n"); 505 506 dev_dbg(dev, "Set up component registers\n"); 507 break; 508 case CXL_REGLOC_RBI_MEMDEV: 509 dev_map = &map->device_map; 510 cxl_probe_device_regs(dev, base, dev_map); 511 if (!dev_map->status.valid || !dev_map->mbox.valid || 512 !dev_map->memdev.valid) { 513 dev_err(dev, "registers not found: %s%s%s\n", 514 !dev_map->status.valid ? "status " : "", 515 !dev_map->mbox.valid ? "mbox " : "", 516 !dev_map->memdev.valid ? "memdev " : ""); 517 return -ENXIO; 518 } 519 520 dev_dbg(dev, "Probing device registers...\n"); 521 break; 522 default: 523 break; 524 } 525 526 return 0; 527 } 528 529 static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, 530 struct cxl_register_map *map) 531 { 532 int rc; 533 534 rc = cxl_find_regblock(pdev, type, map); 535 if (rc) 536 return rc; 537 538 rc = cxl_map_regblock(pdev, map); 539 if (rc) 540 return rc; 541 542 rc = cxl_probe_regs(pdev, map); 543 cxl_unmap_regblock(pdev, map); 544 545 return rc; 546 } 547 548 /* 549 * Assume that any RCIEP that emits the CXL memory expander class code 550 * is an RCD 551 */ 552 static bool is_cxl_restricted(struct pci_dev *pdev) 553 { 554 return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; 555 } 556 557 /* 558 * CXL v3.0 6.2.3 Table 6-4 559 * The table indicates that if PCIe Flit Mode is set, then CXL is in 256B flits 560 * mode, otherwise it's 68B flits mode. 561 */ 562 static bool cxl_pci_flit_256(struct pci_dev *pdev) 563 { 564 u16 lnksta2; 565 566 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA2, &lnksta2); 567 return lnksta2 & PCI_EXP_LNKSTA2_FLIT; 568 } 569 570 static int cxl_pci_ras_unmask(struct pci_dev *pdev) 571 { 572 struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); 573 struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); 574 void __iomem *addr; 575 u32 orig_val, val, mask; 576 u16 cap; 577 int rc; 578 579 if (!cxlds->regs.ras) { 580 dev_dbg(&pdev->dev, "No RAS registers.\n"); 581 return 0; 582 } 583 584 /* BIOS has CXL error control */ 585 if (!host_bridge->native_cxl_error) 586 return -ENXIO; 587 588 rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap); 589 if (rc) 590 return rc; 591 592 if (cap & PCI_EXP_DEVCTL_URRE) { 593 addr = cxlds->regs.ras + CXL_RAS_UNCORRECTABLE_MASK_OFFSET; 594 orig_val = readl(addr); 595 596 mask = CXL_RAS_UNCORRECTABLE_MASK_MASK; 597 if (!cxl_pci_flit_256(pdev)) 598 mask &= ~CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK; 599 val = orig_val & ~mask; 600 writel(val, addr); 601 dev_dbg(&pdev->dev, 602 "Uncorrectable RAS Errors Mask: %#x -> %#x\n", 603 orig_val, val); 604 } 605 606 if (cap & PCI_EXP_DEVCTL_CERE) { 607 addr = cxlds->regs.ras + CXL_RAS_CORRECTABLE_MASK_OFFSET; 608 orig_val = readl(addr); 609 val = orig_val & ~CXL_RAS_CORRECTABLE_MASK_MASK; 610 writel(val, addr); 611 dev_dbg(&pdev->dev, "Correctable RAS Errors Mask: %#x -> %#x\n", 612 orig_val, val); 613 } 614 615 return 0; 616 } 617 618 static void free_event_buf(void *buf) 619 { 620 kvfree(buf); 621 } 622 623 /* 624 * There is a single buffer for reading event logs from the mailbox. All logs 625 * share this buffer protected by the cxlds->event_log_lock. 626 */ 627 static int cxl_mem_alloc_event_buf(struct cxl_dev_state *cxlds) 628 { 629 struct cxl_get_event_payload *buf; 630 631 buf = kvmalloc(cxlds->payload_size, GFP_KERNEL); 632 if (!buf) 633 return -ENOMEM; 634 cxlds->event.buf = buf; 635 636 return devm_add_action_or_reset(cxlds->dev, free_event_buf, buf); 637 } 638 639 static int cxl_alloc_irq_vectors(struct pci_dev *pdev) 640 { 641 int nvecs; 642 643 /* 644 * Per CXL 3.0 3.1.1 CXL.io Endpoint a function on a CXL device must 645 * not generate INTx messages if that function participates in 646 * CXL.cache or CXL.mem. 647 * 648 * Additionally pci_alloc_irq_vectors() handles calling 649 * pci_free_irq_vectors() automatically despite not being called 650 * pcim_*. See pci_setup_msi_context(). 651 */ 652 nvecs = pci_alloc_irq_vectors(pdev, 1, CXL_PCI_DEFAULT_MAX_VECTORS, 653 PCI_IRQ_MSIX | PCI_IRQ_MSI); 654 if (nvecs < 1) { 655 dev_dbg(&pdev->dev, "Failed to alloc irq vectors: %d\n", nvecs); 656 return -ENXIO; 657 } 658 return 0; 659 } 660 661 static irqreturn_t cxl_event_thread(int irq, void *id) 662 { 663 struct cxl_dev_id *dev_id = id; 664 struct cxl_dev_state *cxlds = dev_id->cxlds; 665 u32 status; 666 667 do { 668 /* 669 * CXL 3.0 8.2.8.3.1: The lower 32 bits are the status; 670 * ignore the reserved upper 32 bits 671 */ 672 status = readl(cxlds->regs.status + CXLDEV_DEV_EVENT_STATUS_OFFSET); 673 /* Ignore logs unknown to the driver */ 674 status &= CXLDEV_EVENT_STATUS_ALL; 675 if (!status) 676 break; 677 cxl_mem_get_event_records(cxlds, status); 678 cond_resched(); 679 } while (status); 680 681 return IRQ_HANDLED; 682 } 683 684 static int cxl_event_req_irq(struct cxl_dev_state *cxlds, u8 setting) 685 { 686 struct pci_dev *pdev = to_pci_dev(cxlds->dev); 687 int irq; 688 689 if (FIELD_GET(CXLDEV_EVENT_INT_MODE_MASK, setting) != CXL_INT_MSI_MSIX) 690 return -ENXIO; 691 692 irq = pci_irq_vector(pdev, 693 FIELD_GET(CXLDEV_EVENT_INT_MSGNUM_MASK, setting)); 694 if (irq < 0) 695 return irq; 696 697 return cxl_request_irq(cxlds, irq, NULL, cxl_event_thread); 698 } 699 700 static int cxl_event_get_int_policy(struct cxl_dev_state *cxlds, 701 struct cxl_event_interrupt_policy *policy) 702 { 703 struct cxl_mbox_cmd mbox_cmd = { 704 .opcode = CXL_MBOX_OP_GET_EVT_INT_POLICY, 705 .payload_out = policy, 706 .size_out = sizeof(*policy), 707 }; 708 int rc; 709 710 rc = cxl_internal_send_cmd(cxlds, &mbox_cmd); 711 if (rc < 0) 712 dev_err(cxlds->dev, "Failed to get event interrupt policy : %d", 713 rc); 714 715 return rc; 716 } 717 718 static int cxl_event_config_msgnums(struct cxl_dev_state *cxlds, 719 struct cxl_event_interrupt_policy *policy) 720 { 721 struct cxl_mbox_cmd mbox_cmd; 722 int rc; 723 724 *policy = (struct cxl_event_interrupt_policy) { 725 .info_settings = CXL_INT_MSI_MSIX, 726 .warn_settings = CXL_INT_MSI_MSIX, 727 .failure_settings = CXL_INT_MSI_MSIX, 728 .fatal_settings = CXL_INT_MSI_MSIX, 729 }; 730 731 mbox_cmd = (struct cxl_mbox_cmd) { 732 .opcode = CXL_MBOX_OP_SET_EVT_INT_POLICY, 733 .payload_in = policy, 734 .size_in = sizeof(*policy), 735 }; 736 737 rc = cxl_internal_send_cmd(cxlds, &mbox_cmd); 738 if (rc < 0) { 739 dev_err(cxlds->dev, "Failed to set event interrupt policy : %d", 740 rc); 741 return rc; 742 } 743 744 /* Retrieve final interrupt settings */ 745 return cxl_event_get_int_policy(cxlds, policy); 746 } 747 748 static int cxl_event_irqsetup(struct cxl_dev_state *cxlds) 749 { 750 struct cxl_event_interrupt_policy policy; 751 int rc; 752 753 rc = cxl_event_config_msgnums(cxlds, &policy); 754 if (rc) 755 return rc; 756 757 rc = cxl_event_req_irq(cxlds, policy.info_settings); 758 if (rc) { 759 dev_err(cxlds->dev, "Failed to get interrupt for event Info log\n"); 760 return rc; 761 } 762 763 rc = cxl_event_req_irq(cxlds, policy.warn_settings); 764 if (rc) { 765 dev_err(cxlds->dev, "Failed to get interrupt for event Warn log\n"); 766 return rc; 767 } 768 769 rc = cxl_event_req_irq(cxlds, policy.failure_settings); 770 if (rc) { 771 dev_err(cxlds->dev, "Failed to get interrupt for event Failure log\n"); 772 return rc; 773 } 774 775 rc = cxl_event_req_irq(cxlds, policy.fatal_settings); 776 if (rc) { 777 dev_err(cxlds->dev, "Failed to get interrupt for event Fatal log\n"); 778 return rc; 779 } 780 781 return 0; 782 } 783 784 static bool cxl_event_int_is_fw(u8 setting) 785 { 786 u8 mode = FIELD_GET(CXLDEV_EVENT_INT_MODE_MASK, setting); 787 788 return mode == CXL_INT_FW; 789 } 790 791 static int cxl_event_config(struct pci_host_bridge *host_bridge, 792 struct cxl_dev_state *cxlds) 793 { 794 struct cxl_event_interrupt_policy policy; 795 int rc; 796 797 /* 798 * When BIOS maintains CXL error reporting control, it will process 799 * event records. Only one agent can do so. 800 */ 801 if (!host_bridge->native_cxl_error) 802 return 0; 803 804 rc = cxl_mem_alloc_event_buf(cxlds); 805 if (rc) 806 return rc; 807 808 rc = cxl_event_get_int_policy(cxlds, &policy); 809 if (rc) 810 return rc; 811 812 if (cxl_event_int_is_fw(policy.info_settings) || 813 cxl_event_int_is_fw(policy.warn_settings) || 814 cxl_event_int_is_fw(policy.failure_settings) || 815 cxl_event_int_is_fw(policy.fatal_settings)) { 816 dev_err(cxlds->dev, "FW still in control of Event Logs despite _OSC settings\n"); 817 return -EBUSY; 818 } 819 820 rc = cxl_event_irqsetup(cxlds); 821 if (rc) 822 return rc; 823 824 cxl_mem_get_event_records(cxlds, CXLDEV_EVENT_STATUS_ALL); 825 826 return 0; 827 } 828 829 static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 830 { 831 struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); 832 struct cxl_register_map map; 833 struct cxl_memdev *cxlmd; 834 struct cxl_dev_state *cxlds; 835 int rc; 836 837 /* 838 * Double check the anonymous union trickery in struct cxl_regs 839 * FIXME switch to struct_group() 840 */ 841 BUILD_BUG_ON(offsetof(struct cxl_regs, memdev) != 842 offsetof(struct cxl_regs, device_regs.memdev)); 843 844 rc = pcim_enable_device(pdev); 845 if (rc) 846 return rc; 847 pci_set_master(pdev); 848 849 cxlds = cxl_dev_state_create(&pdev->dev); 850 if (IS_ERR(cxlds)) 851 return PTR_ERR(cxlds); 852 pci_set_drvdata(pdev, cxlds); 853 854 cxlds->rcd = is_cxl_restricted(pdev); 855 cxlds->serial = pci_get_dsn(pdev); 856 cxlds->cxl_dvsec = pci_find_dvsec_capability( 857 pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE); 858 if (!cxlds->cxl_dvsec) 859 dev_warn(&pdev->dev, 860 "Device DVSEC not present, skip CXL.mem init\n"); 861 862 rc = cxl_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map); 863 if (rc) 864 return rc; 865 866 rc = cxl_map_device_regs(&pdev->dev, &cxlds->regs.device_regs, &map); 867 if (rc) 868 return rc; 869 870 /* 871 * If the component registers can't be found, the cxl_pci driver may 872 * still be useful for management functions so don't return an error. 873 */ 874 cxlds->component_reg_phys = CXL_RESOURCE_NONE; 875 rc = cxl_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map); 876 if (rc) 877 dev_warn(&pdev->dev, "No component registers (%d)\n", rc); 878 879 cxlds->component_reg_phys = map.resource; 880 881 rc = cxl_map_component_regs(&pdev->dev, &cxlds->regs.component, 882 &map, BIT(CXL_CM_CAP_CAP_ID_RAS)); 883 if (rc) 884 dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); 885 886 rc = cxl_await_media_ready(cxlds); 887 if (rc == 0) 888 cxlds->media_ready = true; 889 else 890 dev_warn(&pdev->dev, "Media not active (%d)\n", rc); 891 892 rc = cxl_alloc_irq_vectors(pdev); 893 if (rc) 894 return rc; 895 896 rc = cxl_pci_setup_mailbox(cxlds); 897 if (rc) 898 return rc; 899 900 rc = cxl_enumerate_cmds(cxlds); 901 if (rc) 902 return rc; 903 904 rc = cxl_set_timestamp(cxlds); 905 if (rc) 906 return rc; 907 908 rc = cxl_poison_state_init(cxlds); 909 if (rc) 910 return rc; 911 912 rc = cxl_dev_state_identify(cxlds); 913 if (rc) 914 return rc; 915 916 rc = cxl_mem_create_range_info(cxlds); 917 if (rc) 918 return rc; 919 920 cxlmd = devm_cxl_add_memdev(cxlds); 921 if (IS_ERR(cxlmd)) 922 return PTR_ERR(cxlmd); 923 924 rc = cxl_memdev_setup_fw_upload(cxlds); 925 if (rc) 926 return rc; 927 928 rc = cxl_event_config(host_bridge, cxlds); 929 if (rc) 930 return rc; 931 932 rc = cxl_pci_ras_unmask(pdev); 933 if (rc) 934 dev_dbg(&pdev->dev, "No RAS reporting unmasked\n"); 935 936 pci_save_state(pdev); 937 938 return rc; 939 } 940 941 static const struct pci_device_id cxl_mem_pci_tbl[] = { 942 /* PCI class code for CXL.mem Type-3 Devices */ 943 { PCI_DEVICE_CLASS((PCI_CLASS_MEMORY_CXL << 8 | CXL_MEMORY_PROGIF), ~0)}, 944 { /* terminate list */ }, 945 }; 946 MODULE_DEVICE_TABLE(pci, cxl_mem_pci_tbl); 947 948 static pci_ers_result_t cxl_slot_reset(struct pci_dev *pdev) 949 { 950 struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); 951 struct cxl_memdev *cxlmd = cxlds->cxlmd; 952 struct device *dev = &cxlmd->dev; 953 954 dev_info(&pdev->dev, "%s: restart CXL.mem after slot reset\n", 955 dev_name(dev)); 956 pci_restore_state(pdev); 957 if (device_attach(dev) <= 0) 958 return PCI_ERS_RESULT_DISCONNECT; 959 return PCI_ERS_RESULT_RECOVERED; 960 } 961 962 static void cxl_error_resume(struct pci_dev *pdev) 963 { 964 struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); 965 struct cxl_memdev *cxlmd = cxlds->cxlmd; 966 struct device *dev = &cxlmd->dev; 967 968 dev_info(&pdev->dev, "%s: error resume %s\n", dev_name(dev), 969 dev->driver ? "successful" : "failed"); 970 } 971 972 static const struct pci_error_handlers cxl_error_handlers = { 973 .error_detected = cxl_error_detected, 974 .slot_reset = cxl_slot_reset, 975 .resume = cxl_error_resume, 976 .cor_error_detected = cxl_cor_error_detected, 977 }; 978 979 static struct pci_driver cxl_pci_driver = { 980 .name = KBUILD_MODNAME, 981 .id_table = cxl_mem_pci_tbl, 982 .probe = cxl_pci_probe, 983 .err_handler = &cxl_error_handlers, 984 .driver = { 985 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 986 }, 987 }; 988 989 MODULE_LICENSE("GPL v2"); 990 module_pci_driver(cxl_pci_driver); 991 MODULE_IMPORT_NS(CXL); 992