1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright(c) 2022 Intel Corporation. All rights reserved. */ 3 #include <linux/debugfs.h> 4 #include <linux/device.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 8 #include "cxlmem.h" 9 #include "cxlpci.h" 10 11 /** 12 * DOC: cxl mem 13 * 14 * CXL memory endpoint devices and switches are CXL capable devices that are 15 * participating in CXL.mem protocol. Their functionality builds on top of the 16 * CXL.io protocol that allows enumerating and configuring components via 17 * standard PCI mechanisms. 18 * 19 * The cxl_mem driver owns kicking off the enumeration of this CXL.mem 20 * capability. With the detection of a CXL capable endpoint, the driver will 21 * walk up to find the platform specific port it is connected to, and determine 22 * if there are intervening switches in the path. If there are switches, a 23 * secondary action is to enumerate those (implemented in cxl_core). Finally the 24 * cxl_mem driver adds the device it is bound to as a CXL endpoint-port for use 25 * in higher level operations. 26 */ 27 28 static void enable_suspend(void *data) 29 { 30 cxl_mem_active_dec(); 31 } 32 33 static void remove_debugfs(void *dentry) 34 { 35 debugfs_remove_recursive(dentry); 36 } 37 38 static int cxl_mem_dpa_show(struct seq_file *file, void *data) 39 { 40 struct device *dev = file->private; 41 struct cxl_memdev *cxlmd = to_cxl_memdev(dev); 42 43 cxl_dpa_debug(file, cxlmd->cxlds); 44 45 return 0; 46 } 47 48 static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, 49 struct cxl_dport *parent_dport) 50 { 51 struct cxl_port *parent_port = parent_dport->port; 52 struct cxl_dev_state *cxlds = cxlmd->cxlds; 53 struct cxl_port *endpoint, *iter, *down; 54 resource_size_t component_reg_phys; 55 int rc; 56 57 /* 58 * Now that the path to the root is established record all the 59 * intervening ports in the chain. 60 */ 61 for (iter = parent_port, down = NULL; !is_cxl_root(iter); 62 down = iter, iter = to_cxl_port(iter->dev.parent)) { 63 struct cxl_ep *ep; 64 65 ep = cxl_ep_load(iter, cxlmd); 66 ep->next = down; 67 } 68 69 /* 70 * The component registers for an RCD might come from the 71 * host-bridge RCRB if they are not already mapped via the 72 * typical register locator mechanism. 73 */ 74 if (parent_dport->rch && cxlds->component_reg_phys == CXL_RESOURCE_NONE) 75 component_reg_phys = cxl_rcrb_to_component( 76 &cxlmd->dev, parent_dport->rcrb, CXL_RCRB_UPSTREAM); 77 else 78 component_reg_phys = cxlds->component_reg_phys; 79 endpoint = devm_cxl_add_port(host, &cxlmd->dev, component_reg_phys, 80 parent_dport); 81 if (IS_ERR(endpoint)) 82 return PTR_ERR(endpoint); 83 84 rc = cxl_endpoint_autoremove(cxlmd, endpoint); 85 if (rc) 86 return rc; 87 88 if (!endpoint->dev.driver) { 89 dev_err(&cxlmd->dev, "%s failed probe\n", 90 dev_name(&endpoint->dev)); 91 return -ENXIO; 92 } 93 94 return 0; 95 } 96 97 static int cxl_debugfs_poison_inject(void *data, u64 dpa) 98 { 99 struct cxl_memdev *cxlmd = data; 100 101 return cxl_inject_poison(cxlmd, dpa); 102 } 103 104 DEFINE_DEBUGFS_ATTRIBUTE(cxl_poison_inject_fops, NULL, 105 cxl_debugfs_poison_inject, "%llx\n"); 106 107 static int cxl_debugfs_poison_clear(void *data, u64 dpa) 108 { 109 struct cxl_memdev *cxlmd = data; 110 111 return cxl_clear_poison(cxlmd, dpa); 112 } 113 114 DEFINE_DEBUGFS_ATTRIBUTE(cxl_poison_clear_fops, NULL, 115 cxl_debugfs_poison_clear, "%llx\n"); 116 117 static int cxl_mem_probe(struct device *dev) 118 { 119 struct cxl_memdev *cxlmd = to_cxl_memdev(dev); 120 struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds); 121 struct cxl_dev_state *cxlds = cxlmd->cxlds; 122 struct device *endpoint_parent; 123 struct cxl_port *parent_port; 124 struct cxl_dport *dport; 125 struct dentry *dentry; 126 int rc; 127 128 if (!cxlds->media_ready) 129 return -EBUSY; 130 131 /* 132 * Someone is trying to reattach this device after it lost its port 133 * connection (an endpoint port previously registered by this memdev was 134 * disabled). This racy check is ok because if the port is still gone, 135 * no harm done, and if the port hierarchy comes back it will re-trigger 136 * this probe. Port rescan and memdev detach work share the same 137 * single-threaded workqueue. 138 */ 139 if (work_pending(&cxlmd->detach_work)) 140 return -EBUSY; 141 142 dentry = cxl_debugfs_create_dir(dev_name(dev)); 143 debugfs_create_devm_seqfile(dev, "dpamem", dentry, cxl_mem_dpa_show); 144 145 if (test_bit(CXL_POISON_ENABLED_INJECT, mds->poison.enabled_cmds)) 146 debugfs_create_file("inject_poison", 0200, dentry, cxlmd, 147 &cxl_poison_inject_fops); 148 if (test_bit(CXL_POISON_ENABLED_CLEAR, mds->poison.enabled_cmds)) 149 debugfs_create_file("clear_poison", 0200, dentry, cxlmd, 150 &cxl_poison_clear_fops); 151 152 rc = devm_add_action_or_reset(dev, remove_debugfs, dentry); 153 if (rc) 154 return rc; 155 156 rc = devm_cxl_enumerate_ports(cxlmd); 157 if (rc) 158 return rc; 159 160 parent_port = cxl_mem_find_port(cxlmd, &dport); 161 if (!parent_port) { 162 dev_err(dev, "CXL port topology not found\n"); 163 return -ENXIO; 164 } 165 166 if (dport->rch) 167 endpoint_parent = parent_port->uport; 168 else 169 endpoint_parent = &parent_port->dev; 170 171 device_lock(endpoint_parent); 172 if (!endpoint_parent->driver) { 173 dev_err(dev, "CXL port topology %s not enabled\n", 174 dev_name(endpoint_parent)); 175 rc = -ENXIO; 176 goto unlock; 177 } 178 179 rc = devm_cxl_add_endpoint(endpoint_parent, cxlmd, dport); 180 unlock: 181 device_unlock(endpoint_parent); 182 put_device(&parent_port->dev); 183 if (rc) 184 return rc; 185 186 if (resource_size(&cxlds->pmem_res) && IS_ENABLED(CONFIG_CXL_PMEM)) { 187 rc = devm_cxl_add_nvdimm(cxlmd); 188 if (rc == -ENODEV) 189 dev_info(dev, "PMEM disabled by platform\n"); 190 else 191 return rc; 192 } 193 194 /* 195 * The kernel may be operating out of CXL memory on this device, 196 * there is no spec defined way to determine whether this device 197 * preserves contents over suspend, and there is no simple way 198 * to arrange for the suspend image to avoid CXL memory which 199 * would setup a circular dependency between PCI resume and save 200 * state restoration. 201 * 202 * TODO: support suspend when all the regions this device is 203 * hosting are locked and covered by the system address map, 204 * i.e. platform firmware owns restoring the HDM configuration 205 * that it locked. 206 */ 207 cxl_mem_active_inc(); 208 return devm_add_action_or_reset(dev, enable_suspend, NULL); 209 } 210 211 static ssize_t trigger_poison_list_store(struct device *dev, 212 struct device_attribute *attr, 213 const char *buf, size_t len) 214 { 215 bool trigger; 216 int rc; 217 218 if (kstrtobool(buf, &trigger) || !trigger) 219 return -EINVAL; 220 221 rc = cxl_trigger_poison_list(to_cxl_memdev(dev)); 222 223 return rc ? rc : len; 224 } 225 static DEVICE_ATTR_WO(trigger_poison_list); 226 227 static umode_t cxl_mem_visible(struct kobject *kobj, struct attribute *a, int n) 228 { 229 if (a == &dev_attr_trigger_poison_list.attr) { 230 struct device *dev = kobj_to_dev(kobj); 231 struct cxl_memdev *cxlmd = to_cxl_memdev(dev); 232 struct cxl_memdev_state *mds = 233 to_cxl_memdev_state(cxlmd->cxlds); 234 235 if (!test_bit(CXL_POISON_ENABLED_LIST, 236 mds->poison.enabled_cmds)) 237 return 0; 238 } 239 return a->mode; 240 } 241 242 static struct attribute *cxl_mem_attrs[] = { 243 &dev_attr_trigger_poison_list.attr, 244 NULL 245 }; 246 247 static struct attribute_group cxl_mem_group = { 248 .attrs = cxl_mem_attrs, 249 .is_visible = cxl_mem_visible, 250 }; 251 252 __ATTRIBUTE_GROUPS(cxl_mem); 253 254 static struct cxl_driver cxl_mem_driver = { 255 .name = "cxl_mem", 256 .probe = cxl_mem_probe, 257 .id = CXL_DEVICE_MEMORY_EXPANDER, 258 .drv = { 259 .dev_groups = cxl_mem_groups, 260 }, 261 }; 262 263 module_cxl_driver(cxl_mem_driver); 264 265 MODULE_LICENSE("GPL v2"); 266 MODULE_IMPORT_NS(CXL); 267 MODULE_ALIAS_CXL(CXL_DEVICE_MEMORY_EXPANDER); 268 /* 269 * create_endpoint() wants to validate port driver attach immediately after 270 * endpoint registration. 271 */ 272 MODULE_SOFTDEP("pre: cxl_port"); 273