1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020-2021 Intel Corporation. */ 3 #ifndef __CXL_MEM_H__ 4 #define __CXL_MEM_H__ 5 #include <uapi/linux/cxl_mem.h> 6 #include <linux/cdev.h> 7 #include <linux/uuid.h> 8 #include <linux/rcuwait.h> 9 #include "cxl.h" 10 11 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ 12 #define CXLMDEV_STATUS_OFFSET 0x0 13 #define CXLMDEV_DEV_FATAL BIT(0) 14 #define CXLMDEV_FW_HALT BIT(1) 15 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2) 16 #define CXLMDEV_MS_NOT_READY 0 17 #define CXLMDEV_MS_READY 1 18 #define CXLMDEV_MS_ERROR 2 19 #define CXLMDEV_MS_DISABLED 3 20 #define CXLMDEV_READY(status) \ 21 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \ 22 CXLMDEV_MS_READY) 23 #define CXLMDEV_MBOX_IF_READY BIT(4) 24 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5) 25 #define CXLMDEV_RESET_NEEDED_NOT 0 26 #define CXLMDEV_RESET_NEEDED_COLD 1 27 #define CXLMDEV_RESET_NEEDED_WARM 2 28 #define CXLMDEV_RESET_NEEDED_HOT 3 29 #define CXLMDEV_RESET_NEEDED_CXL 4 30 #define CXLMDEV_RESET_NEEDED(status) \ 31 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ 32 CXLMDEV_RESET_NEEDED_NOT) 33 34 /** 35 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device 36 * @dev: driver core device object 37 * @cdev: char dev core object for ioctl operations 38 * @cxlds: The device state backing this device 39 * @detach_work: active memdev lost a port in its ancestry 40 * @cxl_nvb: coordinate removal of @cxl_nvd if present 41 * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem 42 * @id: id number of this memdev instance. 43 * @depth: endpoint port depth 44 */ 45 struct cxl_memdev { 46 struct device dev; 47 struct cdev cdev; 48 struct cxl_dev_state *cxlds; 49 struct work_struct detach_work; 50 struct cxl_nvdimm_bridge *cxl_nvb; 51 struct cxl_nvdimm *cxl_nvd; 52 int id; 53 int depth; 54 }; 55 56 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev) 57 { 58 return container_of(dev, struct cxl_memdev, dev); 59 } 60 61 static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled) 62 { 63 return to_cxl_port(cxled->cxld.dev.parent); 64 } 65 66 static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd) 67 { 68 return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent); 69 } 70 71 static inline struct cxl_memdev * 72 cxled_to_memdev(struct cxl_endpoint_decoder *cxled) 73 { 74 struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent); 75 76 return to_cxl_memdev(port->uport); 77 } 78 79 bool is_cxl_memdev(const struct device *dev); 80 static inline bool is_cxl_endpoint(struct cxl_port *port) 81 { 82 return is_cxl_memdev(port->uport); 83 } 84 85 struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds); 86 int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled, 87 resource_size_t base, resource_size_t len, 88 resource_size_t skipped); 89 90 static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port, 91 struct cxl_memdev *cxlmd) 92 { 93 if (!port) 94 return NULL; 95 96 return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev); 97 } 98 99 /** 100 * struct cxl_mbox_cmd - A command to be submitted to hardware. 101 * @opcode: (input) The command set and command submitted to hardware. 102 * @payload_in: (input) Pointer to the input payload. 103 * @payload_out: (output) Pointer to the output payload. Must be allocated by 104 * the caller. 105 * @size_in: (input) Number of bytes to load from @payload_in. 106 * @size_out: (input) Max number of bytes loaded into @payload_out. 107 * (output) Number of bytes generated by the device. For fixed size 108 * outputs commands this is always expected to be deterministic. For 109 * variable sized output commands, it tells the exact number of bytes 110 * written. 111 * @min_out: (input) internal command output payload size validation 112 * @poll_count: (input) Number of timeouts to attempt. 113 * @poll_interval_ms: (input) Time between mailbox background command polling 114 * interval timeouts. 115 * @return_code: (output) Error code returned from hardware. 116 * 117 * This is the primary mechanism used to send commands to the hardware. 118 * All the fields except @payload_* correspond exactly to the fields described in 119 * Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and 120 * @payload_out are written to, and read from the Command Payload Registers 121 * defined in CXL 2.0 8.2.8.4.8. 122 */ 123 struct cxl_mbox_cmd { 124 u16 opcode; 125 void *payload_in; 126 void *payload_out; 127 size_t size_in; 128 size_t size_out; 129 size_t min_out; 130 int poll_count; 131 int poll_interval_ms; 132 u16 return_code; 133 }; 134 135 /* 136 * Per CXL 3.0 Section 8.2.8.4.5.1 137 */ 138 #define CMD_CMD_RC_TABLE \ 139 C(SUCCESS, 0, NULL), \ 140 C(BACKGROUND, -ENXIO, "background cmd started successfully"), \ 141 C(INPUT, -ENXIO, "cmd input was invalid"), \ 142 C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \ 143 C(INTERNAL, -ENXIO, "internal device error"), \ 144 C(RETRY, -ENXIO, "temporary error, retry once"), \ 145 C(BUSY, -ENXIO, "ongoing background operation"), \ 146 C(MEDIADISABLED, -ENXIO, "media access is disabled"), \ 147 C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \ 148 C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \ 149 C(FWAUTH, -ENXIO, "FW package authentication failed"), \ 150 C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \ 151 C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \ 152 C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \ 153 C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \ 154 C(PADDR, -EFAULT, "physical address specified is invalid"), \ 155 C(POISONLMT, -ENXIO, "poison injection limit has been reached"), \ 156 C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \ 157 C(ABORT, -ENXIO, "background cmd was aborted by device"), \ 158 C(SECURITY, -ENXIO, "not valid in the current security state"), \ 159 C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \ 160 C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\ 161 C(PAYLOADLEN, -ENXIO, "invalid payload length"), \ 162 C(LOG, -ENXIO, "invalid or unsupported log page"), \ 163 C(INTERRUPTED, -ENXIO, "asynchronous event occured"), \ 164 C(FEATUREVERSION, -ENXIO, "unsupported feature version"), \ 165 C(FEATURESELVALUE, -ENXIO, "unsupported feature selection value"), \ 166 C(FEATURETRANSFERIP, -ENXIO, "feature transfer in progress"), \ 167 C(FEATURETRANSFEROOO, -ENXIO, "feature transfer out of order"), \ 168 C(RESOURCEEXHAUSTED, -ENXIO, "resources are exhausted"), \ 169 C(EXTLIST, -ENXIO, "invalid Extent List"), \ 170 171 #undef C 172 #define C(a, b, c) CXL_MBOX_CMD_RC_##a 173 enum { CMD_CMD_RC_TABLE }; 174 #undef C 175 #define C(a, b, c) { b, c } 176 struct cxl_mbox_cmd_rc { 177 int err; 178 const char *desc; 179 }; 180 181 static const 182 struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE }; 183 #undef C 184 185 static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd) 186 { 187 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc; 188 } 189 190 static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd) 191 { 192 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err; 193 } 194 195 /* 196 * CXL 2.0 - Memory capacity multiplier 197 * See Section 8.2.9.5 198 * 199 * Volatile, Persistent, and Partition capacities are specified to be in 200 * multiples of 256MB - define a multiplier to convert to/from bytes. 201 */ 202 #define CXL_CAPACITY_MULTIPLIER SZ_256M 203 204 /** 205 * Event Interrupt Policy 206 * 207 * CXL rev 3.0 section 8.2.9.2.4; Table 8-52 208 */ 209 enum cxl_event_int_mode { 210 CXL_INT_NONE = 0x00, 211 CXL_INT_MSI_MSIX = 0x01, 212 CXL_INT_FW = 0x02 213 }; 214 struct cxl_event_interrupt_policy { 215 u8 info_settings; 216 u8 warn_settings; 217 u8 failure_settings; 218 u8 fatal_settings; 219 } __packed; 220 221 /** 222 * struct cxl_event_state - Event log driver state 223 * 224 * @event_buf: Buffer to receive event data 225 * @event_log_lock: Serialize event_buf and log use 226 */ 227 struct cxl_event_state { 228 struct cxl_get_event_payload *buf; 229 struct mutex log_lock; 230 }; 231 232 /* Device enabled poison commands */ 233 enum poison_cmd_enabled_bits { 234 CXL_POISON_ENABLED_LIST, 235 CXL_POISON_ENABLED_INJECT, 236 CXL_POISON_ENABLED_CLEAR, 237 CXL_POISON_ENABLED_SCAN_CAPS, 238 CXL_POISON_ENABLED_SCAN_MEDIA, 239 CXL_POISON_ENABLED_SCAN_RESULTS, 240 CXL_POISON_ENABLED_MAX 241 }; 242 243 /** 244 * struct cxl_poison_state - Driver poison state info 245 * 246 * @max_errors: Maximum media error records held in device cache 247 * @enabled_cmds: All poison commands enabled in the CEL 248 * @list_out: The poison list payload returned by device 249 * @lock: Protect reads of the poison list 250 * 251 * Reads of the poison list are synchronized to ensure that a reader 252 * does not get an incomplete list because their request overlapped 253 * (was interrupted or preceded by) another read request of the same 254 * DPA range. CXL Spec 3.0 Section 8.2.9.8.4.1 255 */ 256 struct cxl_poison_state { 257 u32 max_errors; 258 DECLARE_BITMAP(enabled_cmds, CXL_POISON_ENABLED_MAX); 259 struct cxl_mbox_poison_out *list_out; 260 struct mutex lock; /* Protect reads of poison list */ 261 }; 262 263 /** 264 * struct cxl_security_state - Device security state 265 * 266 * @state: state of last security operation 267 * @poll: polling for sanitization is enabled, device has no mbox irq support 268 * @poll_tmo_secs: polling timeout 269 * @poll_dwork: polling work item 270 * @sanitize_node: sanitation sysfs file to notify 271 */ 272 struct cxl_security_state { 273 unsigned long state; 274 bool poll; 275 int poll_tmo_secs; 276 struct delayed_work poll_dwork; 277 struct kernfs_node *sanitize_node; 278 }; 279 280 /** 281 * struct cxl_dev_state - The driver device state 282 * 283 * cxl_dev_state represents the CXL driver/device state. It provides an 284 * interface to mailbox commands as well as some cached data about the device. 285 * Currently only memory devices are represented. 286 * 287 * @dev: The device associated with this CXL state 288 * @cxlmd: The device representing the CXL.mem capabilities of @dev 289 * @regs: Parsed register blocks 290 * @cxl_dvsec: Offset to the PCIe device DVSEC 291 * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH) 292 * @media_ready: Indicate whether the device media is usable 293 * @payload_size: Size of space for payload 294 * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) 295 * @lsa_size: Size of Label Storage Area 296 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device) 297 * @mbox_mutex: Mutex to synchronize mailbox access. 298 * @firmware_version: Firmware version for the memory device. 299 * @enabled_cmds: Hardware commands found enabled in CEL. 300 * @exclusive_cmds: Commands that are kernel-internal only 301 * @dpa_res: Overall DPA resource tree for the device 302 * @pmem_res: Active Persistent memory capacity configuration 303 * @ram_res: Active Volatile memory capacity configuration 304 * @total_bytes: sum of all possible capacities 305 * @volatile_only_bytes: hard volatile capacity 306 * @persistent_only_bytes: hard persistent capacity 307 * @partition_align_bytes: alignment size for partition-able capacity 308 * @active_volatile_bytes: sum of hard + soft volatile 309 * @active_persistent_bytes: sum of hard + soft persistent 310 * @next_volatile_bytes: volatile capacity change pending device reset 311 * @next_persistent_bytes: persistent capacity change pending device reset 312 * @component_reg_phys: register base of component registers 313 * @info: Cached DVSEC information about the device. 314 * @serial: PCIe Device Serial Number 315 * @event: event log driver state 316 * @poison: poison driver state info 317 * @mbox_send: @dev specific transport for transmitting mailbox commands 318 * 319 * See section 8.2.9.5.2 Capacity Configuration and Label Storage for 320 * details on capacity parameters. 321 */ 322 struct cxl_dev_state { 323 struct device *dev; 324 struct cxl_memdev *cxlmd; 325 326 struct cxl_regs regs; 327 int cxl_dvsec; 328 329 bool rcd; 330 bool media_ready; 331 size_t payload_size; 332 size_t lsa_size; 333 struct mutex mbox_mutex; /* Protects device mailbox and firmware */ 334 char firmware_version[0x10]; 335 DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX); 336 DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX); 337 338 struct resource dpa_res; 339 struct resource pmem_res; 340 struct resource ram_res; 341 u64 total_bytes; 342 u64 volatile_only_bytes; 343 u64 persistent_only_bytes; 344 u64 partition_align_bytes; 345 346 u64 active_volatile_bytes; 347 u64 active_persistent_bytes; 348 u64 next_volatile_bytes; 349 u64 next_persistent_bytes; 350 351 resource_size_t component_reg_phys; 352 u64 serial; 353 354 struct cxl_event_state event; 355 struct cxl_poison_state poison; 356 struct cxl_security_state security; 357 358 struct rcuwait mbox_wait; 359 int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd); 360 }; 361 362 enum cxl_opcode { 363 CXL_MBOX_OP_INVALID = 0x0000, 364 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID, 365 CXL_MBOX_OP_GET_EVENT_RECORD = 0x0100, 366 CXL_MBOX_OP_CLEAR_EVENT_RECORD = 0x0101, 367 CXL_MBOX_OP_GET_EVT_INT_POLICY = 0x0102, 368 CXL_MBOX_OP_SET_EVT_INT_POLICY = 0x0103, 369 CXL_MBOX_OP_GET_FW_INFO = 0x0200, 370 CXL_MBOX_OP_ACTIVATE_FW = 0x0202, 371 CXL_MBOX_OP_SET_TIMESTAMP = 0x0301, 372 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400, 373 CXL_MBOX_OP_GET_LOG = 0x0401, 374 CXL_MBOX_OP_IDENTIFY = 0x4000, 375 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100, 376 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, 377 CXL_MBOX_OP_GET_LSA = 0x4102, 378 CXL_MBOX_OP_SET_LSA = 0x4103, 379 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200, 380 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201, 381 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202, 382 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203, 383 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204, 384 CXL_MBOX_OP_GET_POISON = 0x4300, 385 CXL_MBOX_OP_INJECT_POISON = 0x4301, 386 CXL_MBOX_OP_CLEAR_POISON = 0x4302, 387 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303, 388 CXL_MBOX_OP_SCAN_MEDIA = 0x4304, 389 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305, 390 CXL_MBOX_OP_SANITIZE = 0x4400, 391 CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500, 392 CXL_MBOX_OP_SET_PASSPHRASE = 0x4501, 393 CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502, 394 CXL_MBOX_OP_UNLOCK = 0x4503, 395 CXL_MBOX_OP_FREEZE_SECURITY = 0x4504, 396 CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505, 397 CXL_MBOX_OP_MAX = 0x10000 398 }; 399 400 #define DEFINE_CXL_CEL_UUID \ 401 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \ 402 0x3b, 0x3f, 0x17) 403 404 #define DEFINE_CXL_VENDOR_DEBUG_UUID \ 405 UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \ 406 0x40, 0x3d, 0x86) 407 408 struct cxl_mbox_get_supported_logs { 409 __le16 entries; 410 u8 rsvd[6]; 411 struct cxl_gsl_entry { 412 uuid_t uuid; 413 __le32 size; 414 } __packed entry[]; 415 } __packed; 416 417 struct cxl_cel_entry { 418 __le16 opcode; 419 __le16 effect; 420 } __packed; 421 422 struct cxl_mbox_get_log { 423 uuid_t uuid; 424 __le32 offset; 425 __le32 length; 426 } __packed; 427 428 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */ 429 struct cxl_mbox_identify { 430 char fw_revision[0x10]; 431 __le64 total_capacity; 432 __le64 volatile_capacity; 433 __le64 persistent_capacity; 434 __le64 partition_align; 435 __le16 info_event_log_size; 436 __le16 warning_event_log_size; 437 __le16 failure_event_log_size; 438 __le16 fatal_event_log_size; 439 __le32 lsa_size; 440 u8 poison_list_max_mer[3]; 441 __le16 inject_poison_limit; 442 u8 poison_caps; 443 u8 qos_telemetry_caps; 444 } __packed; 445 446 /* 447 * Common Event Record Format 448 * CXL rev 3.0 section 8.2.9.2.1; Table 8-42 449 */ 450 struct cxl_event_record_hdr { 451 uuid_t id; 452 u8 length; 453 u8 flags[3]; 454 __le16 handle; 455 __le16 related_handle; 456 __le64 timestamp; 457 u8 maint_op_class; 458 u8 reserved[15]; 459 } __packed; 460 461 #define CXL_EVENT_RECORD_DATA_LENGTH 0x50 462 struct cxl_event_record_raw { 463 struct cxl_event_record_hdr hdr; 464 u8 data[CXL_EVENT_RECORD_DATA_LENGTH]; 465 } __packed; 466 467 /* 468 * Get Event Records output payload 469 * CXL rev 3.0 section 8.2.9.2.2; Table 8-50 470 */ 471 #define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0) 472 #define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1) 473 struct cxl_get_event_payload { 474 u8 flags; 475 u8 reserved1; 476 __le16 overflow_err_count; 477 __le64 first_overflow_timestamp; 478 __le64 last_overflow_timestamp; 479 __le16 record_count; 480 u8 reserved2[10]; 481 struct cxl_event_record_raw records[]; 482 } __packed; 483 484 /* 485 * CXL rev 3.0 section 8.2.9.2.2; Table 8-49 486 */ 487 enum cxl_event_log_type { 488 CXL_EVENT_TYPE_INFO = 0x00, 489 CXL_EVENT_TYPE_WARN, 490 CXL_EVENT_TYPE_FAIL, 491 CXL_EVENT_TYPE_FATAL, 492 CXL_EVENT_TYPE_MAX 493 }; 494 495 /* 496 * Clear Event Records input payload 497 * CXL rev 3.0 section 8.2.9.2.3; Table 8-51 498 */ 499 struct cxl_mbox_clear_event_payload { 500 u8 event_log; /* enum cxl_event_log_type */ 501 u8 clear_flags; 502 u8 nr_recs; 503 u8 reserved[3]; 504 __le16 handles[]; 505 } __packed; 506 #define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAX 507 508 /* 509 * General Media Event Record 510 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43 511 */ 512 #define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10 513 struct cxl_event_gen_media { 514 struct cxl_event_record_hdr hdr; 515 __le64 phys_addr; 516 u8 descriptor; 517 u8 type; 518 u8 transaction_type; 519 u8 validity_flags[2]; 520 u8 channel; 521 u8 rank; 522 u8 device[3]; 523 u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE]; 524 u8 reserved[46]; 525 } __packed; 526 527 /* 528 * DRAM Event Record - DER 529 * CXL rev 3.0 section 8.2.9.2.1.2; Table 3-44 530 */ 531 #define CXL_EVENT_DER_CORRECTION_MASK_SIZE 0x20 532 struct cxl_event_dram { 533 struct cxl_event_record_hdr hdr; 534 __le64 phys_addr; 535 u8 descriptor; 536 u8 type; 537 u8 transaction_type; 538 u8 validity_flags[2]; 539 u8 channel; 540 u8 rank; 541 u8 nibble_mask[3]; 542 u8 bank_group; 543 u8 bank; 544 u8 row[3]; 545 u8 column[2]; 546 u8 correction_mask[CXL_EVENT_DER_CORRECTION_MASK_SIZE]; 547 u8 reserved[0x17]; 548 } __packed; 549 550 /* 551 * Get Health Info Record 552 * CXL rev 3.0 section 8.2.9.8.3.1; Table 8-100 553 */ 554 struct cxl_get_health_info { 555 u8 health_status; 556 u8 media_status; 557 u8 add_status; 558 u8 life_used; 559 u8 device_temp[2]; 560 u8 dirty_shutdown_cnt[4]; 561 u8 cor_vol_err_cnt[4]; 562 u8 cor_per_err_cnt[4]; 563 } __packed; 564 565 /* 566 * Memory Module Event Record 567 * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45 568 */ 569 struct cxl_event_mem_module { 570 struct cxl_event_record_hdr hdr; 571 u8 event_type; 572 struct cxl_get_health_info info; 573 u8 reserved[0x3d]; 574 } __packed; 575 576 struct cxl_mbox_get_partition_info { 577 __le64 active_volatile_cap; 578 __le64 active_persistent_cap; 579 __le64 next_volatile_cap; 580 __le64 next_persistent_cap; 581 } __packed; 582 583 struct cxl_mbox_get_lsa { 584 __le32 offset; 585 __le32 length; 586 } __packed; 587 588 struct cxl_mbox_set_lsa { 589 __le32 offset; 590 __le32 reserved; 591 u8 data[]; 592 } __packed; 593 594 struct cxl_mbox_set_partition_info { 595 __le64 volatile_capacity; 596 u8 flags; 597 } __packed; 598 599 #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0) 600 601 /* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */ 602 struct cxl_mbox_set_timestamp_in { 603 __le64 timestamp; 604 605 } __packed; 606 607 /* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */ 608 struct cxl_mbox_poison_in { 609 __le64 offset; 610 __le64 length; 611 } __packed; 612 613 struct cxl_mbox_poison_out { 614 u8 flags; 615 u8 rsvd1; 616 __le64 overflow_ts; 617 __le16 count; 618 u8 rsvd2[20]; 619 struct cxl_poison_record { 620 __le64 address; 621 __le32 length; 622 __le32 rsvd; 623 } __packed record[]; 624 } __packed; 625 626 /* 627 * Get Poison List address field encodes the starting 628 * address of poison, and the source of the poison. 629 */ 630 #define CXL_POISON_START_MASK GENMASK_ULL(63, 6) 631 #define CXL_POISON_SOURCE_MASK GENMASK(2, 0) 632 633 /* Get Poison List record length is in units of 64 bytes */ 634 #define CXL_POISON_LEN_MULT 64 635 636 /* Kernel defined maximum for a list of poison errors */ 637 #define CXL_POISON_LIST_MAX 1024 638 639 /* Get Poison List: Payload out flags */ 640 #define CXL_POISON_FLAG_MORE BIT(0) 641 #define CXL_POISON_FLAG_OVERFLOW BIT(1) 642 #define CXL_POISON_FLAG_SCANNING BIT(2) 643 644 /* Get Poison List: Poison Source */ 645 #define CXL_POISON_SOURCE_UNKNOWN 0 646 #define CXL_POISON_SOURCE_EXTERNAL 1 647 #define CXL_POISON_SOURCE_INTERNAL 2 648 #define CXL_POISON_SOURCE_INJECTED 3 649 #define CXL_POISON_SOURCE_VENDOR 7 650 651 /* Inject & Clear Poison CXL 3.0 Spec 8.2.9.8.4.2/3 */ 652 struct cxl_mbox_inject_poison { 653 __le64 address; 654 }; 655 656 /* Clear Poison CXL 3.0 Spec 8.2.9.8.4.3 */ 657 struct cxl_mbox_clear_poison { 658 __le64 address; 659 u8 write_data[CXL_POISON_LEN_MULT]; 660 } __packed; 661 662 /** 663 * struct cxl_mem_command - Driver representation of a memory device command 664 * @info: Command information as it exists for the UAPI 665 * @opcode: The actual bits used for the mailbox protocol 666 * @flags: Set of flags effecting driver behavior. 667 * 668 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag 669 * will be enabled by the driver regardless of what hardware may have 670 * advertised. 671 * 672 * The cxl_mem_command is the driver's internal representation of commands that 673 * are supported by the driver. Some of these commands may not be supported by 674 * the hardware. The driver will use @info to validate the fields passed in by 675 * the user then submit the @opcode to the hardware. 676 * 677 * See struct cxl_command_info. 678 */ 679 struct cxl_mem_command { 680 struct cxl_command_info info; 681 enum cxl_opcode opcode; 682 u32 flags; 683 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0) 684 }; 685 686 #define CXL_PMEM_SEC_STATE_USER_PASS_SET 0x01 687 #define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0x02 688 #define CXL_PMEM_SEC_STATE_LOCKED 0x04 689 #define CXL_PMEM_SEC_STATE_FROZEN 0x08 690 #define CXL_PMEM_SEC_STATE_USER_PLIMIT 0x10 691 #define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0x20 692 693 /* set passphrase input payload */ 694 struct cxl_set_pass { 695 u8 type; 696 u8 reserved[31]; 697 /* CXL field using NVDIMM define, same length */ 698 u8 old_pass[NVDIMM_PASSPHRASE_LEN]; 699 u8 new_pass[NVDIMM_PASSPHRASE_LEN]; 700 } __packed; 701 702 /* disable passphrase input payload */ 703 struct cxl_disable_pass { 704 u8 type; 705 u8 reserved[31]; 706 u8 pass[NVDIMM_PASSPHRASE_LEN]; 707 } __packed; 708 709 /* passphrase secure erase payload */ 710 struct cxl_pass_erase { 711 u8 type; 712 u8 reserved[31]; 713 u8 pass[NVDIMM_PASSPHRASE_LEN]; 714 } __packed; 715 716 enum { 717 CXL_PMEM_SEC_PASS_MASTER = 0, 718 CXL_PMEM_SEC_PASS_USER, 719 }; 720 721 int cxl_internal_send_cmd(struct cxl_dev_state *cxlds, 722 struct cxl_mbox_cmd *cmd); 723 int cxl_dev_state_identify(struct cxl_dev_state *cxlds); 724 int cxl_await_media_ready(struct cxl_dev_state *cxlds); 725 int cxl_enumerate_cmds(struct cxl_dev_state *cxlds); 726 int cxl_mem_create_range_info(struct cxl_dev_state *cxlds); 727 struct cxl_dev_state *cxl_dev_state_create(struct device *dev); 728 void set_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds); 729 void clear_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds); 730 void cxl_mem_get_event_records(struct cxl_dev_state *cxlds, u32 status); 731 int cxl_set_timestamp(struct cxl_dev_state *cxlds); 732 int cxl_poison_state_init(struct cxl_dev_state *cxlds); 733 int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len, 734 struct cxl_region *cxlr); 735 int cxl_trigger_poison_list(struct cxl_memdev *cxlmd); 736 int cxl_inject_poison(struct cxl_memdev *cxlmd, u64 dpa); 737 int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa); 738 739 #ifdef CONFIG_CXL_SUSPEND 740 void cxl_mem_active_inc(void); 741 void cxl_mem_active_dec(void); 742 #else 743 static inline void cxl_mem_active_inc(void) 744 { 745 } 746 static inline void cxl_mem_active_dec(void) 747 { 748 } 749 #endif 750 751 int cxl_mem_sanitize(struct cxl_dev_state *cxlds, u16 cmd); 752 753 struct cxl_hdm { 754 struct cxl_component_regs regs; 755 unsigned int decoder_count; 756 unsigned int target_count; 757 unsigned int interleave_mask; 758 struct cxl_port *port; 759 }; 760 761 struct seq_file; 762 struct dentry *cxl_debugfs_create_dir(const char *dir); 763 void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds); 764 #endif /* __CXL_MEM_H__ */ 765