1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020-2021 Intel Corporation. */ 3 #ifndef __CXL_MEM_H__ 4 #define __CXL_MEM_H__ 5 #include <uapi/linux/cxl_mem.h> 6 #include <linux/cdev.h> 7 #include <linux/uuid.h> 8 #include "cxl.h" 9 10 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ 11 #define CXLMDEV_STATUS_OFFSET 0x0 12 #define CXLMDEV_DEV_FATAL BIT(0) 13 #define CXLMDEV_FW_HALT BIT(1) 14 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2) 15 #define CXLMDEV_MS_NOT_READY 0 16 #define CXLMDEV_MS_READY 1 17 #define CXLMDEV_MS_ERROR 2 18 #define CXLMDEV_MS_DISABLED 3 19 #define CXLMDEV_READY(status) \ 20 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \ 21 CXLMDEV_MS_READY) 22 #define CXLMDEV_MBOX_IF_READY BIT(4) 23 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5) 24 #define CXLMDEV_RESET_NEEDED_NOT 0 25 #define CXLMDEV_RESET_NEEDED_COLD 1 26 #define CXLMDEV_RESET_NEEDED_WARM 2 27 #define CXLMDEV_RESET_NEEDED_HOT 3 28 #define CXLMDEV_RESET_NEEDED_CXL 4 29 #define CXLMDEV_RESET_NEEDED(status) \ 30 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ 31 CXLMDEV_RESET_NEEDED_NOT) 32 33 /** 34 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device 35 * @dev: driver core device object 36 * @cdev: char dev core object for ioctl operations 37 * @cxlds: The device state backing this device 38 * @detach_work: active memdev lost a port in its ancestry 39 * @cxl_nvb: coordinate removal of @cxl_nvd if present 40 * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem 41 * @endpoint: connection to the CXL port topology for this memory device 42 * @id: id number of this memdev instance. 43 * @depth: endpoint port depth 44 */ 45 struct cxl_memdev { 46 struct device dev; 47 struct cdev cdev; 48 struct cxl_dev_state *cxlds; 49 struct work_struct detach_work; 50 struct cxl_nvdimm_bridge *cxl_nvb; 51 struct cxl_nvdimm *cxl_nvd; 52 struct cxl_port *endpoint; 53 int id; 54 int depth; 55 }; 56 57 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev) 58 { 59 return container_of(dev, struct cxl_memdev, dev); 60 } 61 62 static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled) 63 { 64 return to_cxl_port(cxled->cxld.dev.parent); 65 } 66 67 static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd) 68 { 69 return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent); 70 } 71 72 static inline struct cxl_memdev * 73 cxled_to_memdev(struct cxl_endpoint_decoder *cxled) 74 { 75 struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent); 76 77 return to_cxl_memdev(port->uport); 78 } 79 80 bool is_cxl_memdev(const struct device *dev); 81 static inline bool is_cxl_endpoint(struct cxl_port *port) 82 { 83 return is_cxl_memdev(port->uport); 84 } 85 86 struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds); 87 int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled, 88 resource_size_t base, resource_size_t len, 89 resource_size_t skipped); 90 91 static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port, 92 struct cxl_memdev *cxlmd) 93 { 94 if (!port) 95 return NULL; 96 97 return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev); 98 } 99 100 /** 101 * struct cxl_mbox_cmd - A command to be submitted to hardware. 102 * @opcode: (input) The command set and command submitted to hardware. 103 * @payload_in: (input) Pointer to the input payload. 104 * @payload_out: (output) Pointer to the output payload. Must be allocated by 105 * the caller. 106 * @size_in: (input) Number of bytes to load from @payload_in. 107 * @size_out: (input) Max number of bytes loaded into @payload_out. 108 * (output) Number of bytes generated by the device. For fixed size 109 * outputs commands this is always expected to be deterministic. For 110 * variable sized output commands, it tells the exact number of bytes 111 * written. 112 * @min_out: (input) internal command output payload size validation 113 * @return_code: (output) Error code returned from hardware. 114 * 115 * This is the primary mechanism used to send commands to the hardware. 116 * All the fields except @payload_* correspond exactly to the fields described in 117 * Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and 118 * @payload_out are written to, and read from the Command Payload Registers 119 * defined in CXL 2.0 8.2.8.4.8. 120 */ 121 struct cxl_mbox_cmd { 122 u16 opcode; 123 void *payload_in; 124 void *payload_out; 125 size_t size_in; 126 size_t size_out; 127 size_t min_out; 128 u16 return_code; 129 }; 130 131 /* 132 * Per CXL 3.0 Section 8.2.8.4.5.1 133 */ 134 #define CMD_CMD_RC_TABLE \ 135 C(SUCCESS, 0, NULL), \ 136 C(BACKGROUND, -ENXIO, "background cmd started successfully"), \ 137 C(INPUT, -ENXIO, "cmd input was invalid"), \ 138 C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \ 139 C(INTERNAL, -ENXIO, "internal device error"), \ 140 C(RETRY, -ENXIO, "temporary error, retry once"), \ 141 C(BUSY, -ENXIO, "ongoing background operation"), \ 142 C(MEDIADISABLED, -ENXIO, "media access is disabled"), \ 143 C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \ 144 C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \ 145 C(FWAUTH, -ENXIO, "FW package authentication failed"), \ 146 C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \ 147 C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \ 148 C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \ 149 C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \ 150 C(PADDR, -EFAULT, "physical address specified is invalid"), \ 151 C(POISONLMT, -ENXIO, "poison injection limit has been reached"), \ 152 C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \ 153 C(ABORT, -ENXIO, "background cmd was aborted by device"), \ 154 C(SECURITY, -ENXIO, "not valid in the current security state"), \ 155 C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \ 156 C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\ 157 C(PAYLOADLEN, -ENXIO, "invalid payload length"), \ 158 C(LOG, -ENXIO, "invalid or unsupported log page"), \ 159 C(INTERRUPTED, -ENXIO, "asynchronous event occured"), \ 160 C(FEATUREVERSION, -ENXIO, "unsupported feature version"), \ 161 C(FEATURESELVALUE, -ENXIO, "unsupported feature selection value"), \ 162 C(FEATURETRANSFERIP, -ENXIO, "feature transfer in progress"), \ 163 C(FEATURETRANSFEROOO, -ENXIO, "feature transfer out of order"), \ 164 C(RESOURCEEXHAUSTED, -ENXIO, "resources are exhausted"), \ 165 C(EXTLIST, -ENXIO, "invalid Extent List"), \ 166 167 #undef C 168 #define C(a, b, c) CXL_MBOX_CMD_RC_##a 169 enum { CMD_CMD_RC_TABLE }; 170 #undef C 171 #define C(a, b, c) { b, c } 172 struct cxl_mbox_cmd_rc { 173 int err; 174 const char *desc; 175 }; 176 177 static const 178 struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE }; 179 #undef C 180 181 static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd) 182 { 183 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc; 184 } 185 186 static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd) 187 { 188 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err; 189 } 190 191 /* 192 * CXL 2.0 - Memory capacity multiplier 193 * See Section 8.2.9.5 194 * 195 * Volatile, Persistent, and Partition capacities are specified to be in 196 * multiples of 256MB - define a multiplier to convert to/from bytes. 197 */ 198 #define CXL_CAPACITY_MULTIPLIER SZ_256M 199 200 /* 201 * Event Interrupt Policy 202 * 203 * CXL rev 3.0 section 8.2.9.2.4; Table 8-52 204 */ 205 enum cxl_event_int_mode { 206 CXL_INT_NONE = 0x00, 207 CXL_INT_MSI_MSIX = 0x01, 208 CXL_INT_FW = 0x02 209 }; 210 struct cxl_event_interrupt_policy { 211 u8 info_settings; 212 u8 warn_settings; 213 u8 failure_settings; 214 u8 fatal_settings; 215 } __packed; 216 217 /** 218 * struct cxl_event_state - Event log driver state 219 * 220 * @buf: Buffer to receive event data 221 * @log_lock: Serialize event_buf and log use 222 */ 223 struct cxl_event_state { 224 struct cxl_get_event_payload *buf; 225 struct mutex log_lock; 226 }; 227 228 /* Device enabled poison commands */ 229 enum poison_cmd_enabled_bits { 230 CXL_POISON_ENABLED_LIST, 231 CXL_POISON_ENABLED_INJECT, 232 CXL_POISON_ENABLED_CLEAR, 233 CXL_POISON_ENABLED_SCAN_CAPS, 234 CXL_POISON_ENABLED_SCAN_MEDIA, 235 CXL_POISON_ENABLED_SCAN_RESULTS, 236 CXL_POISON_ENABLED_MAX 237 }; 238 239 /** 240 * struct cxl_poison_state - Driver poison state info 241 * 242 * @max_errors: Maximum media error records held in device cache 243 * @enabled_cmds: All poison commands enabled in the CEL 244 * @list_out: The poison list payload returned by device 245 * @lock: Protect reads of the poison list 246 * 247 * Reads of the poison list are synchronized to ensure that a reader 248 * does not get an incomplete list because their request overlapped 249 * (was interrupted or preceded by) another read request of the same 250 * DPA range. CXL Spec 3.0 Section 8.2.9.8.4.1 251 */ 252 struct cxl_poison_state { 253 u32 max_errors; 254 DECLARE_BITMAP(enabled_cmds, CXL_POISON_ENABLED_MAX); 255 struct cxl_mbox_poison_out *list_out; 256 struct mutex lock; /* Protect reads of poison list */ 257 }; 258 259 /* 260 * enum cxl_devtype - delineate type-2 from a generic type-3 device 261 * @CXL_DEVTYPE_DEVMEM - Vendor specific CXL Type-2 device implementing HDM-D or 262 * HDM-DB, no requirement that this device implements a 263 * mailbox, or other memory-device-standard manageability 264 * flows. 265 * @CXL_DEVTYPE_CLASSMEM - Common class definition of a CXL Type-3 device with 266 * HDM-H and class-mandatory memory device registers 267 */ 268 enum cxl_devtype { 269 CXL_DEVTYPE_DEVMEM, 270 CXL_DEVTYPE_CLASSMEM, 271 }; 272 273 /** 274 * struct cxl_dev_state - The driver device state 275 * 276 * cxl_dev_state represents the CXL driver/device state. It provides an 277 * interface to mailbox commands as well as some cached data about the device. 278 * Currently only memory devices are represented. 279 * 280 * @dev: The device associated with this CXL state 281 * @cxlmd: The device representing the CXL.mem capabilities of @dev 282 * @regs: Parsed register blocks 283 * @cxl_dvsec: Offset to the PCIe device DVSEC 284 * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH) 285 * @media_ready: Indicate whether the device media is usable 286 * @dpa_res: Overall DPA resource tree for the device 287 * @pmem_res: Active Persistent memory capacity configuration 288 * @ram_res: Active Volatile memory capacity configuration 289 * @component_reg_phys: register base of component registers 290 * @serial: PCIe Device Serial Number 291 * @type: Generic Memory Class device or Vendor Specific Memory device 292 */ 293 struct cxl_dev_state { 294 struct device *dev; 295 struct cxl_memdev *cxlmd; 296 struct cxl_regs regs; 297 int cxl_dvsec; 298 bool rcd; 299 bool media_ready; 300 struct resource dpa_res; 301 struct resource pmem_res; 302 struct resource ram_res; 303 resource_size_t component_reg_phys; 304 u64 serial; 305 enum cxl_devtype type; 306 }; 307 308 /** 309 * struct cxl_memdev_state - Generic Type-3 Memory Device Class driver data 310 * 311 * CXL 8.1.12.1 PCI Header - Class Code Register Memory Device defines 312 * common memory device functionality like the presence of a mailbox and 313 * the functionality related to that like Identify Memory Device and Get 314 * Partition Info 315 * @cxlds: Core driver state common across Type-2 and Type-3 devices 316 * @payload_size: Size of space for payload 317 * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) 318 * @lsa_size: Size of Label Storage Area 319 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device) 320 * @mbox_mutex: Mutex to synchronize mailbox access. 321 * @firmware_version: Firmware version for the memory device. 322 * @enabled_cmds: Hardware commands found enabled in CEL. 323 * @exclusive_cmds: Commands that are kernel-internal only 324 * @total_bytes: sum of all possible capacities 325 * @volatile_only_bytes: hard volatile capacity 326 * @persistent_only_bytes: hard persistent capacity 327 * @partition_align_bytes: alignment size for partition-able capacity 328 * @active_volatile_bytes: sum of hard + soft volatile 329 * @active_persistent_bytes: sum of hard + soft persistent 330 * @next_volatile_bytes: volatile capacity change pending device reset 331 * @next_persistent_bytes: persistent capacity change pending device reset 332 * @event: event log driver state 333 * @poison: poison driver state info 334 * @mbox_send: @dev specific transport for transmitting mailbox commands 335 * 336 * See CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for 337 * details on capacity parameters. 338 */ 339 struct cxl_memdev_state { 340 struct cxl_dev_state cxlds; 341 size_t payload_size; 342 size_t lsa_size; 343 struct mutex mbox_mutex; /* Protects device mailbox and firmware */ 344 char firmware_version[0x10]; 345 DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX); 346 DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX); 347 u64 total_bytes; 348 u64 volatile_only_bytes; 349 u64 persistent_only_bytes; 350 u64 partition_align_bytes; 351 u64 active_volatile_bytes; 352 u64 active_persistent_bytes; 353 u64 next_volatile_bytes; 354 u64 next_persistent_bytes; 355 struct cxl_event_state event; 356 struct cxl_poison_state poison; 357 int (*mbox_send)(struct cxl_memdev_state *mds, 358 struct cxl_mbox_cmd *cmd); 359 }; 360 361 static inline struct cxl_memdev_state * 362 to_cxl_memdev_state(struct cxl_dev_state *cxlds) 363 { 364 if (cxlds->type != CXL_DEVTYPE_CLASSMEM) 365 return NULL; 366 return container_of(cxlds, struct cxl_memdev_state, cxlds); 367 } 368 369 enum cxl_opcode { 370 CXL_MBOX_OP_INVALID = 0x0000, 371 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID, 372 CXL_MBOX_OP_GET_EVENT_RECORD = 0x0100, 373 CXL_MBOX_OP_CLEAR_EVENT_RECORD = 0x0101, 374 CXL_MBOX_OP_GET_EVT_INT_POLICY = 0x0102, 375 CXL_MBOX_OP_SET_EVT_INT_POLICY = 0x0103, 376 CXL_MBOX_OP_GET_FW_INFO = 0x0200, 377 CXL_MBOX_OP_ACTIVATE_FW = 0x0202, 378 CXL_MBOX_OP_SET_TIMESTAMP = 0x0301, 379 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400, 380 CXL_MBOX_OP_GET_LOG = 0x0401, 381 CXL_MBOX_OP_IDENTIFY = 0x4000, 382 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100, 383 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, 384 CXL_MBOX_OP_GET_LSA = 0x4102, 385 CXL_MBOX_OP_SET_LSA = 0x4103, 386 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200, 387 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201, 388 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202, 389 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203, 390 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204, 391 CXL_MBOX_OP_GET_POISON = 0x4300, 392 CXL_MBOX_OP_INJECT_POISON = 0x4301, 393 CXL_MBOX_OP_CLEAR_POISON = 0x4302, 394 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303, 395 CXL_MBOX_OP_SCAN_MEDIA = 0x4304, 396 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305, 397 CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500, 398 CXL_MBOX_OP_SET_PASSPHRASE = 0x4501, 399 CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502, 400 CXL_MBOX_OP_UNLOCK = 0x4503, 401 CXL_MBOX_OP_FREEZE_SECURITY = 0x4504, 402 CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505, 403 CXL_MBOX_OP_MAX = 0x10000 404 }; 405 406 #define DEFINE_CXL_CEL_UUID \ 407 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \ 408 0x3b, 0x3f, 0x17) 409 410 #define DEFINE_CXL_VENDOR_DEBUG_UUID \ 411 UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \ 412 0x40, 0x3d, 0x86) 413 414 struct cxl_mbox_get_supported_logs { 415 __le16 entries; 416 u8 rsvd[6]; 417 struct cxl_gsl_entry { 418 uuid_t uuid; 419 __le32 size; 420 } __packed entry[]; 421 } __packed; 422 423 struct cxl_cel_entry { 424 __le16 opcode; 425 __le16 effect; 426 } __packed; 427 428 struct cxl_mbox_get_log { 429 uuid_t uuid; 430 __le32 offset; 431 __le32 length; 432 } __packed; 433 434 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */ 435 struct cxl_mbox_identify { 436 char fw_revision[0x10]; 437 __le64 total_capacity; 438 __le64 volatile_capacity; 439 __le64 persistent_capacity; 440 __le64 partition_align; 441 __le16 info_event_log_size; 442 __le16 warning_event_log_size; 443 __le16 failure_event_log_size; 444 __le16 fatal_event_log_size; 445 __le32 lsa_size; 446 u8 poison_list_max_mer[3]; 447 __le16 inject_poison_limit; 448 u8 poison_caps; 449 u8 qos_telemetry_caps; 450 } __packed; 451 452 /* 453 * Common Event Record Format 454 * CXL rev 3.0 section 8.2.9.2.1; Table 8-42 455 */ 456 struct cxl_event_record_hdr { 457 uuid_t id; 458 u8 length; 459 u8 flags[3]; 460 __le16 handle; 461 __le16 related_handle; 462 __le64 timestamp; 463 u8 maint_op_class; 464 u8 reserved[15]; 465 } __packed; 466 467 #define CXL_EVENT_RECORD_DATA_LENGTH 0x50 468 struct cxl_event_record_raw { 469 struct cxl_event_record_hdr hdr; 470 u8 data[CXL_EVENT_RECORD_DATA_LENGTH]; 471 } __packed; 472 473 /* 474 * Get Event Records output payload 475 * CXL rev 3.0 section 8.2.9.2.2; Table 8-50 476 */ 477 #define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0) 478 #define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1) 479 struct cxl_get_event_payload { 480 u8 flags; 481 u8 reserved1; 482 __le16 overflow_err_count; 483 __le64 first_overflow_timestamp; 484 __le64 last_overflow_timestamp; 485 __le16 record_count; 486 u8 reserved2[10]; 487 struct cxl_event_record_raw records[]; 488 } __packed; 489 490 /* 491 * CXL rev 3.0 section 8.2.9.2.2; Table 8-49 492 */ 493 enum cxl_event_log_type { 494 CXL_EVENT_TYPE_INFO = 0x00, 495 CXL_EVENT_TYPE_WARN, 496 CXL_EVENT_TYPE_FAIL, 497 CXL_EVENT_TYPE_FATAL, 498 CXL_EVENT_TYPE_MAX 499 }; 500 501 /* 502 * Clear Event Records input payload 503 * CXL rev 3.0 section 8.2.9.2.3; Table 8-51 504 */ 505 struct cxl_mbox_clear_event_payload { 506 u8 event_log; /* enum cxl_event_log_type */ 507 u8 clear_flags; 508 u8 nr_recs; 509 u8 reserved[3]; 510 __le16 handles[]; 511 } __packed; 512 #define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAX 513 514 /* 515 * General Media Event Record 516 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43 517 */ 518 #define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10 519 struct cxl_event_gen_media { 520 struct cxl_event_record_hdr hdr; 521 __le64 phys_addr; 522 u8 descriptor; 523 u8 type; 524 u8 transaction_type; 525 u8 validity_flags[2]; 526 u8 channel; 527 u8 rank; 528 u8 device[3]; 529 u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE]; 530 u8 reserved[46]; 531 } __packed; 532 533 /* 534 * DRAM Event Record - DER 535 * CXL rev 3.0 section 8.2.9.2.1.2; Table 3-44 536 */ 537 #define CXL_EVENT_DER_CORRECTION_MASK_SIZE 0x20 538 struct cxl_event_dram { 539 struct cxl_event_record_hdr hdr; 540 __le64 phys_addr; 541 u8 descriptor; 542 u8 type; 543 u8 transaction_type; 544 u8 validity_flags[2]; 545 u8 channel; 546 u8 rank; 547 u8 nibble_mask[3]; 548 u8 bank_group; 549 u8 bank; 550 u8 row[3]; 551 u8 column[2]; 552 u8 correction_mask[CXL_EVENT_DER_CORRECTION_MASK_SIZE]; 553 u8 reserved[0x17]; 554 } __packed; 555 556 /* 557 * Get Health Info Record 558 * CXL rev 3.0 section 8.2.9.8.3.1; Table 8-100 559 */ 560 struct cxl_get_health_info { 561 u8 health_status; 562 u8 media_status; 563 u8 add_status; 564 u8 life_used; 565 u8 device_temp[2]; 566 u8 dirty_shutdown_cnt[4]; 567 u8 cor_vol_err_cnt[4]; 568 u8 cor_per_err_cnt[4]; 569 } __packed; 570 571 /* 572 * Memory Module Event Record 573 * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45 574 */ 575 struct cxl_event_mem_module { 576 struct cxl_event_record_hdr hdr; 577 u8 event_type; 578 struct cxl_get_health_info info; 579 u8 reserved[0x3d]; 580 } __packed; 581 582 struct cxl_mbox_get_partition_info { 583 __le64 active_volatile_cap; 584 __le64 active_persistent_cap; 585 __le64 next_volatile_cap; 586 __le64 next_persistent_cap; 587 } __packed; 588 589 struct cxl_mbox_get_lsa { 590 __le32 offset; 591 __le32 length; 592 } __packed; 593 594 struct cxl_mbox_set_lsa { 595 __le32 offset; 596 __le32 reserved; 597 u8 data[]; 598 } __packed; 599 600 struct cxl_mbox_set_partition_info { 601 __le64 volatile_capacity; 602 u8 flags; 603 } __packed; 604 605 #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0) 606 607 /* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */ 608 struct cxl_mbox_set_timestamp_in { 609 __le64 timestamp; 610 611 } __packed; 612 613 /* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */ 614 struct cxl_mbox_poison_in { 615 __le64 offset; 616 __le64 length; 617 } __packed; 618 619 struct cxl_mbox_poison_out { 620 u8 flags; 621 u8 rsvd1; 622 __le64 overflow_ts; 623 __le16 count; 624 u8 rsvd2[20]; 625 struct cxl_poison_record { 626 __le64 address; 627 __le32 length; 628 __le32 rsvd; 629 } __packed record[]; 630 } __packed; 631 632 /* 633 * Get Poison List address field encodes the starting 634 * address of poison, and the source of the poison. 635 */ 636 #define CXL_POISON_START_MASK GENMASK_ULL(63, 6) 637 #define CXL_POISON_SOURCE_MASK GENMASK(2, 0) 638 639 /* Get Poison List record length is in units of 64 bytes */ 640 #define CXL_POISON_LEN_MULT 64 641 642 /* Kernel defined maximum for a list of poison errors */ 643 #define CXL_POISON_LIST_MAX 1024 644 645 /* Get Poison List: Payload out flags */ 646 #define CXL_POISON_FLAG_MORE BIT(0) 647 #define CXL_POISON_FLAG_OVERFLOW BIT(1) 648 #define CXL_POISON_FLAG_SCANNING BIT(2) 649 650 /* Get Poison List: Poison Source */ 651 #define CXL_POISON_SOURCE_UNKNOWN 0 652 #define CXL_POISON_SOURCE_EXTERNAL 1 653 #define CXL_POISON_SOURCE_INTERNAL 2 654 #define CXL_POISON_SOURCE_INJECTED 3 655 #define CXL_POISON_SOURCE_VENDOR 7 656 657 /* Inject & Clear Poison CXL 3.0 Spec 8.2.9.8.4.2/3 */ 658 struct cxl_mbox_inject_poison { 659 __le64 address; 660 }; 661 662 /* Clear Poison CXL 3.0 Spec 8.2.9.8.4.3 */ 663 struct cxl_mbox_clear_poison { 664 __le64 address; 665 u8 write_data[CXL_POISON_LEN_MULT]; 666 } __packed; 667 668 /** 669 * struct cxl_mem_command - Driver representation of a memory device command 670 * @info: Command information as it exists for the UAPI 671 * @opcode: The actual bits used for the mailbox protocol 672 * @flags: Set of flags effecting driver behavior. 673 * 674 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag 675 * will be enabled by the driver regardless of what hardware may have 676 * advertised. 677 * 678 * The cxl_mem_command is the driver's internal representation of commands that 679 * are supported by the driver. Some of these commands may not be supported by 680 * the hardware. The driver will use @info to validate the fields passed in by 681 * the user then submit the @opcode to the hardware. 682 * 683 * See struct cxl_command_info. 684 */ 685 struct cxl_mem_command { 686 struct cxl_command_info info; 687 enum cxl_opcode opcode; 688 u32 flags; 689 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0) 690 }; 691 692 #define CXL_PMEM_SEC_STATE_USER_PASS_SET 0x01 693 #define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0x02 694 #define CXL_PMEM_SEC_STATE_LOCKED 0x04 695 #define CXL_PMEM_SEC_STATE_FROZEN 0x08 696 #define CXL_PMEM_SEC_STATE_USER_PLIMIT 0x10 697 #define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0x20 698 699 /* set passphrase input payload */ 700 struct cxl_set_pass { 701 u8 type; 702 u8 reserved[31]; 703 /* CXL field using NVDIMM define, same length */ 704 u8 old_pass[NVDIMM_PASSPHRASE_LEN]; 705 u8 new_pass[NVDIMM_PASSPHRASE_LEN]; 706 } __packed; 707 708 /* disable passphrase input payload */ 709 struct cxl_disable_pass { 710 u8 type; 711 u8 reserved[31]; 712 u8 pass[NVDIMM_PASSPHRASE_LEN]; 713 } __packed; 714 715 /* passphrase secure erase payload */ 716 struct cxl_pass_erase { 717 u8 type; 718 u8 reserved[31]; 719 u8 pass[NVDIMM_PASSPHRASE_LEN]; 720 } __packed; 721 722 enum { 723 CXL_PMEM_SEC_PASS_MASTER = 0, 724 CXL_PMEM_SEC_PASS_USER, 725 }; 726 727 int cxl_internal_send_cmd(struct cxl_memdev_state *mds, 728 struct cxl_mbox_cmd *cmd); 729 int cxl_dev_state_identify(struct cxl_memdev_state *mds); 730 int cxl_await_media_ready(struct cxl_dev_state *cxlds); 731 int cxl_enumerate_cmds(struct cxl_memdev_state *mds); 732 int cxl_mem_create_range_info(struct cxl_memdev_state *mds); 733 struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev); 734 void set_exclusive_cxl_commands(struct cxl_memdev_state *mds, 735 unsigned long *cmds); 736 void clear_exclusive_cxl_commands(struct cxl_memdev_state *mds, 737 unsigned long *cmds); 738 void cxl_mem_get_event_records(struct cxl_memdev_state *mds, u32 status); 739 int cxl_set_timestamp(struct cxl_memdev_state *mds); 740 int cxl_poison_state_init(struct cxl_memdev_state *mds); 741 int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len, 742 struct cxl_region *cxlr); 743 int cxl_trigger_poison_list(struct cxl_memdev *cxlmd); 744 int cxl_inject_poison(struct cxl_memdev *cxlmd, u64 dpa); 745 int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa); 746 747 #ifdef CONFIG_CXL_SUSPEND 748 void cxl_mem_active_inc(void); 749 void cxl_mem_active_dec(void); 750 #else 751 static inline void cxl_mem_active_inc(void) 752 { 753 } 754 static inline void cxl_mem_active_dec(void) 755 { 756 } 757 #endif 758 759 struct cxl_hdm { 760 struct cxl_component_regs regs; 761 unsigned int decoder_count; 762 unsigned int target_count; 763 unsigned int interleave_mask; 764 struct cxl_port *port; 765 }; 766 767 struct seq_file; 768 struct dentry *cxl_debugfs_create_dir(const char *dir); 769 void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds); 770 #endif /* __CXL_MEM_H__ */ 771