1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020 Intel Corporation. */ 3 4 #ifndef __CXL_H__ 5 #define __CXL_H__ 6 7 #include <linux/libnvdimm.h> 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/log2.h> 11 #include <linux/io.h> 12 13 /** 14 * DOC: cxl objects 15 * 16 * The CXL core objects like ports, decoders, and regions are shared 17 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers 18 * (port-driver, region-driver, nvdimm object-drivers... etc). 19 */ 20 21 /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ 22 #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K 23 24 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/ 25 #define CXL_CM_OFFSET 0x1000 26 #define CXL_CM_CAP_HDR_OFFSET 0x0 27 #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0) 28 #define CM_CAP_HDR_CAP_ID 1 29 #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16) 30 #define CM_CAP_HDR_CAP_VERSION 1 31 #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20) 32 #define CM_CAP_HDR_CACHE_MEM_VERSION 1 33 #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24) 34 #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20) 35 36 #define CXL_CM_CAP_CAP_ID_RAS 0x2 37 #define CXL_CM_CAP_CAP_ID_HDM 0x5 38 #define CXL_CM_CAP_CAP_HDM_VERSION 1 39 40 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ 41 #define CXL_HDM_DECODER_CAP_OFFSET 0x0 42 #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0) 43 #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) 44 #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) 45 #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) 46 #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 47 #define CXL_HDM_DECODER_ENABLE BIT(1) 48 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) 49 #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14) 50 #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18) 51 #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c) 52 #define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) 53 #define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0) 54 #define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4) 55 #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8) 56 #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9) 57 #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10) 58 #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11) 59 #define CXL_HDM_DECODER0_CTRL_TYPE BIT(12) 60 #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24) 61 #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28) 62 #define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i) 63 #define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i) 64 65 /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */ 66 #define CXL_DECODER_MIN_GRANULARITY 256 67 #define CXL_DECODER_MAX_ENCODED_IG 6 68 69 static inline int cxl_hdm_decoder_count(u32 cap_hdr) 70 { 71 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr); 72 73 return val ? val * 2 : 1; 74 } 75 76 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ 77 static inline int eig_to_granularity(u16 eig, unsigned int *granularity) 78 { 79 if (eig > CXL_DECODER_MAX_ENCODED_IG) 80 return -EINVAL; 81 *granularity = CXL_DECODER_MIN_GRANULARITY << eig; 82 return 0; 83 } 84 85 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */ 86 static inline int eiw_to_ways(u8 eiw, unsigned int *ways) 87 { 88 switch (eiw) { 89 case 0 ... 4: 90 *ways = 1 << eiw; 91 break; 92 case 8 ... 10: 93 *ways = 3 << (eiw - 8); 94 break; 95 default: 96 return -EINVAL; 97 } 98 99 return 0; 100 } 101 102 static inline int granularity_to_eig(int granularity, u16 *eig) 103 { 104 if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY || 105 !is_power_of_2(granularity)) 106 return -EINVAL; 107 *eig = ilog2(granularity) - 8; 108 return 0; 109 } 110 111 static inline int ways_to_eiw(unsigned int ways, u8 *eiw) 112 { 113 if (ways > 16) 114 return -EINVAL; 115 if (is_power_of_2(ways)) { 116 *eiw = ilog2(ways); 117 return 0; 118 } 119 if (ways % 3) 120 return -EINVAL; 121 ways /= 3; 122 if (!is_power_of_2(ways)) 123 return -EINVAL; 124 *eiw = ilog2(ways) + 8; 125 return 0; 126 } 127 128 /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */ 129 #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0 130 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 131 #define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4 132 #define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 133 #define CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK BIT(8) 134 #define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8 135 #define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 136 #define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC 137 #define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0) 138 #define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10 139 #define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0) 140 #define CXL_RAS_CAP_CONTROL_OFFSET 0x14 141 #define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0) 142 #define CXL_RAS_HEADER_LOG_OFFSET 0x18 143 #define CXL_RAS_CAPABILITY_LENGTH 0x58 144 #define CXL_HEADERLOG_SIZE SZ_512 145 #define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32) 146 147 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ 148 #define CXLDEV_CAP_ARRAY_OFFSET 0x0 149 #define CXLDEV_CAP_ARRAY_CAP_ID 0 150 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) 151 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) 152 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ 153 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0) 154 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */ 155 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1 156 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2 157 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3 158 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000 159 160 /* CXL 3.0 8.2.8.3.1 Event Status Register */ 161 #define CXLDEV_DEV_EVENT_STATUS_OFFSET 0x00 162 #define CXLDEV_EVENT_STATUS_INFO BIT(0) 163 #define CXLDEV_EVENT_STATUS_WARN BIT(1) 164 #define CXLDEV_EVENT_STATUS_FAIL BIT(2) 165 #define CXLDEV_EVENT_STATUS_FATAL BIT(3) 166 167 #define CXLDEV_EVENT_STATUS_ALL (CXLDEV_EVENT_STATUS_INFO | \ 168 CXLDEV_EVENT_STATUS_WARN | \ 169 CXLDEV_EVENT_STATUS_FAIL | \ 170 CXLDEV_EVENT_STATUS_FATAL) 171 172 /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */ 173 #define CXLDEV_EVENT_INT_MODE_MASK GENMASK(1, 0) 174 #define CXLDEV_EVENT_INT_MSGNUM_MASK GENMASK(7, 4) 175 176 /* CXL 2.0 8.2.8.4 Mailbox Registers */ 177 #define CXLDEV_MBOX_CAPS_OFFSET 0x00 178 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) 179 #define CXLDEV_MBOX_CTRL_OFFSET 0x04 180 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) 181 #define CXLDEV_MBOX_CMD_OFFSET 0x08 182 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 183 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16) 184 #define CXLDEV_MBOX_STATUS_OFFSET 0x10 185 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32) 186 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 187 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 188 189 /* 190 * Using struct_group() allows for per register-block-type helper routines, 191 * without requiring block-type agnostic code to include the prefix. 192 */ 193 struct cxl_regs { 194 /* 195 * Common set of CXL Component register block base pointers 196 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure 197 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure 198 */ 199 struct_group_tagged(cxl_component_regs, component, 200 void __iomem *hdm_decoder; 201 void __iomem *ras; 202 ); 203 /* 204 * Common set of CXL Device register block base pointers 205 * @status: CXL 2.0 8.2.8.3 Device Status Registers 206 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers 207 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers 208 */ 209 struct_group_tagged(cxl_device_regs, device_regs, 210 void __iomem *status, *mbox, *memdev; 211 ); 212 }; 213 214 struct cxl_reg_map { 215 bool valid; 216 int id; 217 unsigned long offset; 218 unsigned long size; 219 }; 220 221 struct cxl_component_reg_map { 222 struct cxl_reg_map hdm_decoder; 223 struct cxl_reg_map ras; 224 }; 225 226 struct cxl_device_reg_map { 227 struct cxl_reg_map status; 228 struct cxl_reg_map mbox; 229 struct cxl_reg_map memdev; 230 }; 231 232 /** 233 * struct cxl_register_map - DVSEC harvested register block mapping parameters 234 * @base: virtual base of the register-block-BAR + @block_offset 235 * @resource: physical resource base of the register block 236 * @max_size: maximum mapping size to perform register search 237 * @reg_type: see enum cxl_regloc_type 238 * @component_map: cxl_reg_map for component registers 239 * @device_map: cxl_reg_maps for device registers 240 */ 241 struct cxl_register_map { 242 void __iomem *base; 243 resource_size_t resource; 244 resource_size_t max_size; 245 u8 reg_type; 246 union { 247 struct cxl_component_reg_map component_map; 248 struct cxl_device_reg_map device_map; 249 }; 250 }; 251 252 void cxl_probe_component_regs(struct device *dev, void __iomem *base, 253 struct cxl_component_reg_map *map); 254 void cxl_probe_device_regs(struct device *dev, void __iomem *base, 255 struct cxl_device_reg_map *map); 256 int cxl_map_component_regs(struct device *dev, struct cxl_component_regs *regs, 257 struct cxl_register_map *map, 258 unsigned long map_mask); 259 int cxl_map_device_regs(struct device *dev, struct cxl_device_regs *regs, 260 struct cxl_register_map *map); 261 262 enum cxl_regloc_type; 263 int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, 264 struct cxl_register_map *map); 265 struct cxl_dport; 266 resource_size_t cxl_rcd_component_reg_phys(struct device *dev, 267 struct cxl_dport *dport); 268 269 #define CXL_RESOURCE_NONE ((resource_size_t) -1) 270 #define CXL_TARGET_STRLEN 20 271 272 /* 273 * cxl_decoder flags that define the type of memory / devices this 274 * decoder supports as well as configuration lock status See "CXL 2.0 275 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. 276 * Additionally indicate whether decoder settings were autodetected, 277 * user customized. 278 */ 279 #define CXL_DECODER_F_RAM BIT(0) 280 #define CXL_DECODER_F_PMEM BIT(1) 281 #define CXL_DECODER_F_TYPE2 BIT(2) 282 #define CXL_DECODER_F_TYPE3 BIT(3) 283 #define CXL_DECODER_F_LOCK BIT(4) 284 #define CXL_DECODER_F_ENABLE BIT(5) 285 #define CXL_DECODER_F_MASK GENMASK(5, 0) 286 287 enum cxl_decoder_type { 288 CXL_DECODER_ACCELERATOR = 2, 289 CXL_DECODER_EXPANDER = 3, 290 }; 291 292 /* 293 * Current specification goes up to 8, double that seems a reasonable 294 * software max for the foreseeable future 295 */ 296 #define CXL_DECODER_MAX_INTERLEAVE 16 297 298 299 /** 300 * struct cxl_decoder - Common CXL HDM Decoder Attributes 301 * @dev: this decoder's device 302 * @id: kernel device name id 303 * @hpa_range: Host physical address range mapped by this decoder 304 * @interleave_ways: number of cxl_dports in this decode 305 * @interleave_granularity: data stride per dport 306 * @target_type: accelerator vs expander (type2 vs type3) selector 307 * @region: currently assigned region for this decoder 308 * @flags: memory type capabilities and locking 309 * @commit: device/decoder-type specific callback to commit settings to hw 310 * @reset: device/decoder-type specific callback to reset hw settings 311 */ 312 struct cxl_decoder { 313 struct device dev; 314 int id; 315 struct range hpa_range; 316 int interleave_ways; 317 int interleave_granularity; 318 enum cxl_decoder_type target_type; 319 struct cxl_region *region; 320 unsigned long flags; 321 int (*commit)(struct cxl_decoder *cxld); 322 int (*reset)(struct cxl_decoder *cxld); 323 }; 324 325 /* 326 * CXL_DECODER_DEAD prevents endpoints from being reattached to regions 327 * while cxld_unregister() is running 328 */ 329 enum cxl_decoder_mode { 330 CXL_DECODER_NONE, 331 CXL_DECODER_RAM, 332 CXL_DECODER_PMEM, 333 CXL_DECODER_MIXED, 334 CXL_DECODER_DEAD, 335 }; 336 337 static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode) 338 { 339 static const char * const names[] = { 340 [CXL_DECODER_NONE] = "none", 341 [CXL_DECODER_RAM] = "ram", 342 [CXL_DECODER_PMEM] = "pmem", 343 [CXL_DECODER_MIXED] = "mixed", 344 }; 345 346 if (mode >= CXL_DECODER_NONE && mode <= CXL_DECODER_MIXED) 347 return names[mode]; 348 return "mixed"; 349 } 350 351 /* 352 * Track whether this decoder is reserved for region autodiscovery, or 353 * free for userspace provisioning. 354 */ 355 enum cxl_decoder_state { 356 CXL_DECODER_STATE_MANUAL, 357 CXL_DECODER_STATE_AUTO, 358 }; 359 360 /** 361 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder 362 * @cxld: base cxl_decoder_object 363 * @dpa_res: actively claimed DPA span of this decoder 364 * @skip: offset into @dpa_res where @cxld.hpa_range maps 365 * @mode: which memory type / access-mode-partition this decoder targets 366 * @state: autodiscovery state 367 * @pos: interleave position in @cxld.region 368 */ 369 struct cxl_endpoint_decoder { 370 struct cxl_decoder cxld; 371 struct resource *dpa_res; 372 resource_size_t skip; 373 enum cxl_decoder_mode mode; 374 enum cxl_decoder_state state; 375 int pos; 376 }; 377 378 /** 379 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder 380 * @cxld: base cxl_decoder object 381 * @target_lock: coordinate coherent reads of the target list 382 * @nr_targets: number of elements in @target 383 * @target: active ordered target list in current decoder configuration 384 * 385 * The 'switch' decoder type represents the decoder instances of cxl_port's that 386 * route from the root of a CXL memory decode topology to the endpoints. They 387 * come in two flavors, root-level decoders, statically defined by platform 388 * firmware, and mid-level decoders, where interleave-granularity, 389 * interleave-width, and the target list are mutable. 390 */ 391 struct cxl_switch_decoder { 392 struct cxl_decoder cxld; 393 seqlock_t target_lock; 394 int nr_targets; 395 struct cxl_dport *target[]; 396 }; 397 398 struct cxl_root_decoder; 399 typedef struct cxl_dport *(*cxl_calc_hb_fn)(struct cxl_root_decoder *cxlrd, 400 int pos); 401 402 /** 403 * struct cxl_root_decoder - Static platform CXL address decoder 404 * @res: host / parent resource for region allocations 405 * @region_id: region id for next region provisioning event 406 * @calc_hb: which host bridge covers the n'th position by granularity 407 * @platform_data: platform specific configuration data 408 * @range_lock: sync region autodiscovery by address range 409 * @cxlsd: base cxl switch decoder 410 */ 411 struct cxl_root_decoder { 412 struct resource *res; 413 atomic_t region_id; 414 cxl_calc_hb_fn calc_hb; 415 void *platform_data; 416 struct mutex range_lock; 417 struct cxl_switch_decoder cxlsd; 418 }; 419 420 /* 421 * enum cxl_config_state - State machine for region configuration 422 * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely 423 * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more 424 * changes to interleave_ways or interleave_granularity 425 * @CXL_CONFIG_ACTIVE: All targets have been added the region is now 426 * active 427 * @CXL_CONFIG_RESET_PENDING: see commit_store() 428 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware 429 */ 430 enum cxl_config_state { 431 CXL_CONFIG_IDLE, 432 CXL_CONFIG_INTERLEAVE_ACTIVE, 433 CXL_CONFIG_ACTIVE, 434 CXL_CONFIG_RESET_PENDING, 435 CXL_CONFIG_COMMIT, 436 }; 437 438 /** 439 * struct cxl_region_params - region settings 440 * @state: allow the driver to lockdown further parameter changes 441 * @uuid: unique id for persistent regions 442 * @interleave_ways: number of endpoints in the region 443 * @interleave_granularity: capacity each endpoint contributes to a stripe 444 * @res: allocated iomem capacity for this region 445 * @targets: active ordered targets in current decoder configuration 446 * @nr_targets: number of targets 447 * 448 * State transitions are protected by the cxl_region_rwsem 449 */ 450 struct cxl_region_params { 451 enum cxl_config_state state; 452 uuid_t uuid; 453 int interleave_ways; 454 int interleave_granularity; 455 struct resource *res; 456 struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; 457 int nr_targets; 458 }; 459 460 /* 461 * Flag whether this region needs to have its HPA span synchronized with 462 * CPU cache state at region activation time. 463 */ 464 #define CXL_REGION_F_INCOHERENT 0 465 466 /* 467 * Indicate whether this region has been assembled by autodetection or 468 * userspace assembly. Prevent endpoint decoders outside of automatic 469 * detection from being added to the region. 470 */ 471 #define CXL_REGION_F_AUTO 1 472 473 /** 474 * struct cxl_region - CXL region 475 * @dev: This region's device 476 * @id: This region's id. Id is globally unique across all regions 477 * @mode: Endpoint decoder allocation / access mode 478 * @type: Endpoint decoder target type 479 * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown 480 * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge 481 * @flags: Region state flags 482 * @params: active + config params for the region 483 */ 484 struct cxl_region { 485 struct device dev; 486 int id; 487 enum cxl_decoder_mode mode; 488 enum cxl_decoder_type type; 489 struct cxl_nvdimm_bridge *cxl_nvb; 490 struct cxl_pmem_region *cxlr_pmem; 491 unsigned long flags; 492 struct cxl_region_params params; 493 }; 494 495 struct cxl_nvdimm_bridge { 496 int id; 497 struct device dev; 498 struct cxl_port *port; 499 struct nvdimm_bus *nvdimm_bus; 500 struct nvdimm_bus_descriptor nd_desc; 501 }; 502 503 #define CXL_DEV_ID_LEN 19 504 505 struct cxl_nvdimm { 506 struct device dev; 507 struct cxl_memdev *cxlmd; 508 u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */ 509 }; 510 511 struct cxl_pmem_region_mapping { 512 struct cxl_memdev *cxlmd; 513 struct cxl_nvdimm *cxl_nvd; 514 u64 start; 515 u64 size; 516 int position; 517 }; 518 519 struct cxl_pmem_region { 520 struct device dev; 521 struct cxl_region *cxlr; 522 struct nd_region *nd_region; 523 struct range hpa_range; 524 int nr_mappings; 525 struct cxl_pmem_region_mapping mapping[]; 526 }; 527 528 struct cxl_dax_region { 529 struct device dev; 530 struct cxl_region *cxlr; 531 struct range hpa_range; 532 }; 533 534 /** 535 * struct cxl_port - logical collection of upstream port devices and 536 * downstream port devices to construct a CXL memory 537 * decode hierarchy. 538 * @dev: this port's device 539 * @uport: PCI or platform device implementing the upstream port capability 540 * @host_bridge: Shortcut to the platform attach point for this port 541 * @id: id for port device-name 542 * @dports: cxl_dport instances referenced by decoders 543 * @endpoints: cxl_ep instances, endpoints that are a descendant of this port 544 * @regions: cxl_region_ref instances, regions mapped by this port 545 * @parent_dport: dport that points to this port in the parent 546 * @decoder_ida: allocator for decoder ids 547 * @nr_dports: number of entries in @dports 548 * @hdm_end: track last allocated HDM decoder instance for allocation ordering 549 * @commit_end: cursor to track highest committed decoder for commit ordering 550 * @component_reg_phys: component register capability base address (optional) 551 * @dead: last ep has been removed, force port re-creation 552 * @depth: How deep this port is relative to the root. depth 0 is the root. 553 * @cdat: Cached CDAT data 554 * @cdat_available: Should a CDAT attribute be available in sysfs 555 */ 556 struct cxl_port { 557 struct device dev; 558 struct device *uport; 559 struct device *host_bridge; 560 int id; 561 struct xarray dports; 562 struct xarray endpoints; 563 struct xarray regions; 564 struct cxl_dport *parent_dport; 565 struct ida decoder_ida; 566 int nr_dports; 567 int hdm_end; 568 int commit_end; 569 resource_size_t component_reg_phys; 570 bool dead; 571 unsigned int depth; 572 struct cxl_cdat { 573 void *table; 574 size_t length; 575 } cdat; 576 bool cdat_available; 577 }; 578 579 static inline struct cxl_dport * 580 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) 581 { 582 return xa_load(&port->dports, (unsigned long)dport_dev); 583 } 584 585 /** 586 * struct cxl_dport - CXL downstream port 587 * @dport: PCI bridge or firmware device representing the downstream link 588 * @port_id: unique hardware identifier for dport in decoder target list 589 * @component_reg_phys: downstream port component registers 590 * @rcrb: base address for the Root Complex Register Block 591 * @rch: Indicate whether this dport was enumerated in RCH or VH mode 592 * @port: reference to cxl_port that contains this downstream port 593 */ 594 struct cxl_dport { 595 struct device *dport; 596 int port_id; 597 resource_size_t component_reg_phys; 598 resource_size_t rcrb; 599 bool rch; 600 struct cxl_port *port; 601 }; 602 603 /** 604 * struct cxl_ep - track an endpoint's interest in a port 605 * @ep: device that hosts a generic CXL endpoint (expander or accelerator) 606 * @dport: which dport routes to this endpoint on @port 607 * @next: cxl switch port across the link attached to @dport NULL if 608 * attached to an endpoint 609 */ 610 struct cxl_ep { 611 struct device *ep; 612 struct cxl_dport *dport; 613 struct cxl_port *next; 614 }; 615 616 /** 617 * struct cxl_region_ref - track a region's interest in a port 618 * @port: point in topology to install this reference 619 * @decoder: decoder assigned for @region in @port 620 * @region: region for this reference 621 * @endpoints: cxl_ep references for region members beneath @port 622 * @nr_targets_set: track how many targets have been programmed during setup 623 * @nr_eps: number of endpoints beneath @port 624 * @nr_targets: number of distinct targets needed to reach @nr_eps 625 */ 626 struct cxl_region_ref { 627 struct cxl_port *port; 628 struct cxl_decoder *decoder; 629 struct cxl_region *region; 630 struct xarray endpoints; 631 int nr_targets_set; 632 int nr_eps; 633 int nr_targets; 634 }; 635 636 /* 637 * The platform firmware device hosting the root is also the top of the 638 * CXL port topology. All other CXL ports have another CXL port as their 639 * parent and their ->uport / host device is out-of-line of the port 640 * ancestry. 641 */ 642 static inline bool is_cxl_root(struct cxl_port *port) 643 { 644 return port->uport == port->dev.parent; 645 } 646 647 bool is_cxl_port(const struct device *dev); 648 struct cxl_port *to_cxl_port(const struct device *dev); 649 struct pci_bus; 650 int devm_cxl_register_pci_bus(struct device *host, struct device *uport, 651 struct pci_bus *bus); 652 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); 653 struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport, 654 resource_size_t component_reg_phys, 655 struct cxl_dport *parent_dport); 656 struct cxl_port *find_cxl_root(struct cxl_port *port); 657 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); 658 void cxl_bus_rescan(void); 659 void cxl_bus_drain(void); 660 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, 661 struct cxl_dport **dport); 662 bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); 663 664 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, 665 struct device *dport, int port_id, 666 resource_size_t component_reg_phys); 667 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, 668 struct device *dport_dev, int port_id, 669 resource_size_t rcrb); 670 671 struct cxl_decoder *to_cxl_decoder(struct device *dev); 672 struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); 673 struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); 674 struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev); 675 bool is_root_decoder(struct device *dev); 676 bool is_switch_decoder(struct device *dev); 677 bool is_endpoint_decoder(struct device *dev); 678 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, 679 unsigned int nr_targets, 680 cxl_calc_hb_fn calc_hb); 681 struct cxl_dport *cxl_hb_modulo(struct cxl_root_decoder *cxlrd, int pos); 682 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, 683 unsigned int nr_targets); 684 int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map); 685 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port); 686 int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map); 687 int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld); 688 int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint); 689 690 /** 691 * struct cxl_endpoint_dvsec_info - Cached DVSEC info 692 * @mem_enabled: cached value of mem_enabled in the DVSEC at init time 693 * @ranges: Number of active HDM ranges this device uses. 694 * @port: endpoint port associated with this info instance 695 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE 696 */ 697 struct cxl_endpoint_dvsec_info { 698 bool mem_enabled; 699 int ranges; 700 struct cxl_port *port; 701 struct range dvsec_range[2]; 702 }; 703 704 struct cxl_hdm; 705 struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port, 706 struct cxl_endpoint_dvsec_info *info); 707 int devm_cxl_enable_hdm(struct cxl_port *port, struct cxl_hdm *cxlhdm); 708 int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, 709 struct cxl_endpoint_dvsec_info *info); 710 int devm_cxl_add_passthrough_decoder(struct cxl_port *port); 711 int cxl_dvsec_rr_decode(struct device *dev, int dvsec, 712 struct cxl_endpoint_dvsec_info *info); 713 714 bool is_cxl_region(struct device *dev); 715 716 extern struct bus_type cxl_bus_type; 717 718 struct cxl_driver { 719 const char *name; 720 int (*probe)(struct device *dev); 721 void (*remove)(struct device *dev); 722 struct device_driver drv; 723 int id; 724 }; 725 726 static inline struct cxl_driver *to_cxl_drv(struct device_driver *drv) 727 { 728 return container_of(drv, struct cxl_driver, drv); 729 } 730 731 int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, 732 const char *modname); 733 #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME) 734 void cxl_driver_unregister(struct cxl_driver *cxl_drv); 735 736 #define module_cxl_driver(__cxl_driver) \ 737 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister) 738 739 #define CXL_DEVICE_NVDIMM_BRIDGE 1 740 #define CXL_DEVICE_NVDIMM 2 741 #define CXL_DEVICE_PORT 3 742 #define CXL_DEVICE_ROOT 4 743 #define CXL_DEVICE_MEMORY_EXPANDER 5 744 #define CXL_DEVICE_REGION 6 745 #define CXL_DEVICE_PMEM_REGION 7 746 #define CXL_DEVICE_DAX_REGION 8 747 748 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") 749 #define CXL_MODALIAS_FMT "cxl:t%d" 750 751 struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev); 752 struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, 753 struct cxl_port *port); 754 struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); 755 bool is_cxl_nvdimm(struct device *dev); 756 bool is_cxl_nvdimm_bridge(struct device *dev); 757 int devm_cxl_add_nvdimm(struct cxl_memdev *cxlmd); 758 struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd); 759 760 #ifdef CONFIG_CXL_REGION 761 bool is_cxl_pmem_region(struct device *dev); 762 struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); 763 int cxl_add_to_region(struct cxl_port *root, 764 struct cxl_endpoint_decoder *cxled); 765 struct cxl_dax_region *to_cxl_dax_region(struct device *dev); 766 #else 767 static inline bool is_cxl_pmem_region(struct device *dev) 768 { 769 return false; 770 } 771 static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) 772 { 773 return NULL; 774 } 775 static inline int cxl_add_to_region(struct cxl_port *root, 776 struct cxl_endpoint_decoder *cxled) 777 { 778 return 0; 779 } 780 static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev) 781 { 782 return NULL; 783 } 784 #endif 785 786 /* 787 * Unit test builds overrides this to __weak, find the 'strong' version 788 * of these symbols in tools/testing/cxl/. 789 */ 790 #ifndef __mock 791 #define __mock static 792 #endif 793 794 #endif /* __CXL_H__ */ 795