1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020 Intel Corporation. */ 3 4 #ifndef __CXL_H__ 5 #define __CXL_H__ 6 7 #include <linux/libnvdimm.h> 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/log2.h> 11 #include <linux/io.h> 12 13 /** 14 * DOC: cxl objects 15 * 16 * The CXL core objects like ports, decoders, and regions are shared 17 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers 18 * (port-driver, region-driver, nvdimm object-drivers... etc). 19 */ 20 21 /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ 22 #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K 23 24 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/ 25 #define CXL_CM_OFFSET 0x1000 26 #define CXL_CM_CAP_HDR_OFFSET 0x0 27 #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0) 28 #define CM_CAP_HDR_CAP_ID 1 29 #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16) 30 #define CM_CAP_HDR_CAP_VERSION 1 31 #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20) 32 #define CM_CAP_HDR_CACHE_MEM_VERSION 1 33 #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24) 34 #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20) 35 36 #define CXL_CM_CAP_CAP_ID_RAS 0x2 37 #define CXL_CM_CAP_CAP_ID_HDM 0x5 38 #define CXL_CM_CAP_CAP_HDM_VERSION 1 39 40 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ 41 #define CXL_HDM_DECODER_CAP_OFFSET 0x0 42 #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0) 43 #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) 44 #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) 45 #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) 46 #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 47 #define CXL_HDM_DECODER_ENABLE BIT(1) 48 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) 49 #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14) 50 #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18) 51 #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c) 52 #define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) 53 #define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0) 54 #define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4) 55 #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8) 56 #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9) 57 #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10) 58 #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11) 59 #define CXL_HDM_DECODER0_CTRL_TYPE BIT(12) 60 #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24) 61 #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28) 62 #define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i) 63 #define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i) 64 65 /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */ 66 #define CXL_DECODER_MIN_GRANULARITY 256 67 #define CXL_DECODER_MAX_ENCODED_IG 6 68 69 static inline int cxl_hdm_decoder_count(u32 cap_hdr) 70 { 71 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr); 72 73 return val ? val * 2 : 1; 74 } 75 76 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ 77 static inline int eig_to_granularity(u16 eig, unsigned int *granularity) 78 { 79 if (eig > CXL_DECODER_MAX_ENCODED_IG) 80 return -EINVAL; 81 *granularity = CXL_DECODER_MIN_GRANULARITY << eig; 82 return 0; 83 } 84 85 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */ 86 static inline int eiw_to_ways(u8 eiw, unsigned int *ways) 87 { 88 switch (eiw) { 89 case 0 ... 4: 90 *ways = 1 << eiw; 91 break; 92 case 8 ... 10: 93 *ways = 3 << (eiw - 8); 94 break; 95 default: 96 return -EINVAL; 97 } 98 99 return 0; 100 } 101 102 static inline int granularity_to_eig(int granularity, u16 *eig) 103 { 104 if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY || 105 !is_power_of_2(granularity)) 106 return -EINVAL; 107 *eig = ilog2(granularity) - 8; 108 return 0; 109 } 110 111 static inline int ways_to_eiw(unsigned int ways, u8 *eiw) 112 { 113 if (ways > 16) 114 return -EINVAL; 115 if (is_power_of_2(ways)) { 116 *eiw = ilog2(ways); 117 return 0; 118 } 119 if (ways % 3) 120 return -EINVAL; 121 ways /= 3; 122 if (!is_power_of_2(ways)) 123 return -EINVAL; 124 *eiw = ilog2(ways) + 8; 125 return 0; 126 } 127 128 /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */ 129 #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0 130 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 131 #define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4 132 #define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 133 #define CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK BIT(8) 134 #define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8 135 #define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 136 #define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC 137 #define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0) 138 #define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10 139 #define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0) 140 #define CXL_RAS_CAP_CONTROL_OFFSET 0x14 141 #define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0) 142 #define CXL_RAS_HEADER_LOG_OFFSET 0x18 143 #define CXL_RAS_CAPABILITY_LENGTH 0x58 144 #define CXL_HEADERLOG_SIZE SZ_512 145 #define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32) 146 147 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ 148 #define CXLDEV_CAP_ARRAY_OFFSET 0x0 149 #define CXLDEV_CAP_ARRAY_CAP_ID 0 150 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) 151 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) 152 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ 153 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0) 154 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */ 155 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1 156 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2 157 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3 158 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000 159 160 /* CXL 3.0 8.2.8.3.1 Event Status Register */ 161 #define CXLDEV_DEV_EVENT_STATUS_OFFSET 0x00 162 #define CXLDEV_EVENT_STATUS_INFO BIT(0) 163 #define CXLDEV_EVENT_STATUS_WARN BIT(1) 164 #define CXLDEV_EVENT_STATUS_FAIL BIT(2) 165 #define CXLDEV_EVENT_STATUS_FATAL BIT(3) 166 167 #define CXLDEV_EVENT_STATUS_ALL (CXLDEV_EVENT_STATUS_INFO | \ 168 CXLDEV_EVENT_STATUS_WARN | \ 169 CXLDEV_EVENT_STATUS_FAIL | \ 170 CXLDEV_EVENT_STATUS_FATAL) 171 172 /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */ 173 #define CXLDEV_EVENT_INT_MODE_MASK GENMASK(1, 0) 174 #define CXLDEV_EVENT_INT_MSGNUM_MASK GENMASK(7, 4) 175 176 /* CXL 2.0 8.2.8.4 Mailbox Registers */ 177 #define CXLDEV_MBOX_CAPS_OFFSET 0x00 178 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) 179 #define CXLDEV_MBOX_CTRL_OFFSET 0x04 180 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) 181 #define CXLDEV_MBOX_CMD_OFFSET 0x08 182 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 183 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16) 184 #define CXLDEV_MBOX_STATUS_OFFSET 0x10 185 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32) 186 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 187 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 188 189 /* 190 * Using struct_group() allows for per register-block-type helper routines, 191 * without requiring block-type agnostic code to include the prefix. 192 */ 193 struct cxl_regs { 194 /* 195 * Common set of CXL Component register block base pointers 196 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure 197 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure 198 */ 199 struct_group_tagged(cxl_component_regs, component, 200 void __iomem *hdm_decoder; 201 void __iomem *ras; 202 ); 203 /* 204 * Common set of CXL Device register block base pointers 205 * @status: CXL 2.0 8.2.8.3 Device Status Registers 206 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers 207 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers 208 */ 209 struct_group_tagged(cxl_device_regs, device_regs, 210 void __iomem *status, *mbox, *memdev; 211 ); 212 }; 213 214 struct cxl_reg_map { 215 bool valid; 216 int id; 217 unsigned long offset; 218 unsigned long size; 219 }; 220 221 struct cxl_component_reg_map { 222 struct cxl_reg_map hdm_decoder; 223 struct cxl_reg_map ras; 224 }; 225 226 struct cxl_device_reg_map { 227 struct cxl_reg_map status; 228 struct cxl_reg_map mbox; 229 struct cxl_reg_map memdev; 230 }; 231 232 /** 233 * struct cxl_register_map - DVSEC harvested register block mapping parameters 234 * @base: virtual base of the register-block-BAR + @block_offset 235 * @resource: physical resource base of the register block 236 * @max_size: maximum mapping size to perform register search 237 * @reg_type: see enum cxl_regloc_type 238 * @component_map: cxl_reg_map for component registers 239 * @device_map: cxl_reg_maps for device registers 240 */ 241 struct cxl_register_map { 242 void __iomem *base; 243 resource_size_t resource; 244 resource_size_t max_size; 245 u8 reg_type; 246 union { 247 struct cxl_component_reg_map component_map; 248 struct cxl_device_reg_map device_map; 249 }; 250 }; 251 252 void cxl_probe_component_regs(struct device *dev, void __iomem *base, 253 struct cxl_component_reg_map *map); 254 void cxl_probe_device_regs(struct device *dev, void __iomem *base, 255 struct cxl_device_reg_map *map); 256 int cxl_map_component_regs(struct device *dev, struct cxl_component_regs *regs, 257 struct cxl_register_map *map, 258 unsigned long map_mask); 259 int cxl_map_device_regs(struct device *dev, struct cxl_device_regs *regs, 260 struct cxl_register_map *map); 261 262 enum cxl_regloc_type; 263 int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type); 264 int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type, 265 struct cxl_register_map *map, int index); 266 int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, 267 struct cxl_register_map *map); 268 269 enum cxl_rcrb { 270 CXL_RCRB_DOWNSTREAM, 271 CXL_RCRB_UPSTREAM, 272 }; 273 resource_size_t cxl_rcrb_to_component(struct device *dev, 274 resource_size_t rcrb, 275 enum cxl_rcrb which); 276 277 #define CXL_RESOURCE_NONE ((resource_size_t) -1) 278 #define CXL_TARGET_STRLEN 20 279 280 /* 281 * cxl_decoder flags that define the type of memory / devices this 282 * decoder supports as well as configuration lock status See "CXL 2.0 283 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. 284 * Additionally indicate whether decoder settings were autodetected, 285 * user customized. 286 */ 287 #define CXL_DECODER_F_RAM BIT(0) 288 #define CXL_DECODER_F_PMEM BIT(1) 289 #define CXL_DECODER_F_TYPE2 BIT(2) 290 #define CXL_DECODER_F_TYPE3 BIT(3) 291 #define CXL_DECODER_F_LOCK BIT(4) 292 #define CXL_DECODER_F_ENABLE BIT(5) 293 #define CXL_DECODER_F_MASK GENMASK(5, 0) 294 295 enum cxl_decoder_type { 296 CXL_DECODER_ACCELERATOR = 2, 297 CXL_DECODER_EXPANDER = 3, 298 }; 299 300 /* 301 * Current specification goes up to 8, double that seems a reasonable 302 * software max for the foreseeable future 303 */ 304 #define CXL_DECODER_MAX_INTERLEAVE 16 305 306 307 /** 308 * struct cxl_decoder - Common CXL HDM Decoder Attributes 309 * @dev: this decoder's device 310 * @id: kernel device name id 311 * @hpa_range: Host physical address range mapped by this decoder 312 * @interleave_ways: number of cxl_dports in this decode 313 * @interleave_granularity: data stride per dport 314 * @target_type: accelerator vs expander (type2 vs type3) selector 315 * @region: currently assigned region for this decoder 316 * @flags: memory type capabilities and locking 317 * @commit: device/decoder-type specific callback to commit settings to hw 318 * @reset: device/decoder-type specific callback to reset hw settings 319 */ 320 struct cxl_decoder { 321 struct device dev; 322 int id; 323 struct range hpa_range; 324 int interleave_ways; 325 int interleave_granularity; 326 enum cxl_decoder_type target_type; 327 struct cxl_region *region; 328 unsigned long flags; 329 int (*commit)(struct cxl_decoder *cxld); 330 int (*reset)(struct cxl_decoder *cxld); 331 }; 332 333 /* 334 * CXL_DECODER_DEAD prevents endpoints from being reattached to regions 335 * while cxld_unregister() is running 336 */ 337 enum cxl_decoder_mode { 338 CXL_DECODER_NONE, 339 CXL_DECODER_RAM, 340 CXL_DECODER_PMEM, 341 CXL_DECODER_MIXED, 342 CXL_DECODER_DEAD, 343 }; 344 345 static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode) 346 { 347 static const char * const names[] = { 348 [CXL_DECODER_NONE] = "none", 349 [CXL_DECODER_RAM] = "ram", 350 [CXL_DECODER_PMEM] = "pmem", 351 [CXL_DECODER_MIXED] = "mixed", 352 }; 353 354 if (mode >= CXL_DECODER_NONE && mode <= CXL_DECODER_MIXED) 355 return names[mode]; 356 return "mixed"; 357 } 358 359 /* 360 * Track whether this decoder is reserved for region autodiscovery, or 361 * free for userspace provisioning. 362 */ 363 enum cxl_decoder_state { 364 CXL_DECODER_STATE_MANUAL, 365 CXL_DECODER_STATE_AUTO, 366 }; 367 368 /** 369 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder 370 * @cxld: base cxl_decoder_object 371 * @dpa_res: actively claimed DPA span of this decoder 372 * @skip: offset into @dpa_res where @cxld.hpa_range maps 373 * @mode: which memory type / access-mode-partition this decoder targets 374 * @state: autodiscovery state 375 * @pos: interleave position in @cxld.region 376 */ 377 struct cxl_endpoint_decoder { 378 struct cxl_decoder cxld; 379 struct resource *dpa_res; 380 resource_size_t skip; 381 enum cxl_decoder_mode mode; 382 enum cxl_decoder_state state; 383 int pos; 384 }; 385 386 /** 387 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder 388 * @cxld: base cxl_decoder object 389 * @target_lock: coordinate coherent reads of the target list 390 * @nr_targets: number of elements in @target 391 * @target: active ordered target list in current decoder configuration 392 * 393 * The 'switch' decoder type represents the decoder instances of cxl_port's that 394 * route from the root of a CXL memory decode topology to the endpoints. They 395 * come in two flavors, root-level decoders, statically defined by platform 396 * firmware, and mid-level decoders, where interleave-granularity, 397 * interleave-width, and the target list are mutable. 398 */ 399 struct cxl_switch_decoder { 400 struct cxl_decoder cxld; 401 seqlock_t target_lock; 402 int nr_targets; 403 struct cxl_dport *target[]; 404 }; 405 406 struct cxl_root_decoder; 407 typedef struct cxl_dport *(*cxl_calc_hb_fn)(struct cxl_root_decoder *cxlrd, 408 int pos); 409 410 /** 411 * struct cxl_root_decoder - Static platform CXL address decoder 412 * @res: host / parent resource for region allocations 413 * @region_id: region id for next region provisioning event 414 * @calc_hb: which host bridge covers the n'th position by granularity 415 * @platform_data: platform specific configuration data 416 * @range_lock: sync region autodiscovery by address range 417 * @cxlsd: base cxl switch decoder 418 */ 419 struct cxl_root_decoder { 420 struct resource *res; 421 atomic_t region_id; 422 cxl_calc_hb_fn calc_hb; 423 void *platform_data; 424 struct mutex range_lock; 425 struct cxl_switch_decoder cxlsd; 426 }; 427 428 /* 429 * enum cxl_config_state - State machine for region configuration 430 * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely 431 * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more 432 * changes to interleave_ways or interleave_granularity 433 * @CXL_CONFIG_ACTIVE: All targets have been added the region is now 434 * active 435 * @CXL_CONFIG_RESET_PENDING: see commit_store() 436 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware 437 */ 438 enum cxl_config_state { 439 CXL_CONFIG_IDLE, 440 CXL_CONFIG_INTERLEAVE_ACTIVE, 441 CXL_CONFIG_ACTIVE, 442 CXL_CONFIG_RESET_PENDING, 443 CXL_CONFIG_COMMIT, 444 }; 445 446 /** 447 * struct cxl_region_params - region settings 448 * @state: allow the driver to lockdown further parameter changes 449 * @uuid: unique id for persistent regions 450 * @interleave_ways: number of endpoints in the region 451 * @interleave_granularity: capacity each endpoint contributes to a stripe 452 * @res: allocated iomem capacity for this region 453 * @targets: active ordered targets in current decoder configuration 454 * @nr_targets: number of targets 455 * 456 * State transitions are protected by the cxl_region_rwsem 457 */ 458 struct cxl_region_params { 459 enum cxl_config_state state; 460 uuid_t uuid; 461 int interleave_ways; 462 int interleave_granularity; 463 struct resource *res; 464 struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; 465 int nr_targets; 466 }; 467 468 /* 469 * Flag whether this region needs to have its HPA span synchronized with 470 * CPU cache state at region activation time. 471 */ 472 #define CXL_REGION_F_INCOHERENT 0 473 474 /* 475 * Indicate whether this region has been assembled by autodetection or 476 * userspace assembly. Prevent endpoint decoders outside of automatic 477 * detection from being added to the region. 478 */ 479 #define CXL_REGION_F_AUTO 1 480 481 /** 482 * struct cxl_region - CXL region 483 * @dev: This region's device 484 * @id: This region's id. Id is globally unique across all regions 485 * @mode: Endpoint decoder allocation / access mode 486 * @type: Endpoint decoder target type 487 * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown 488 * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge 489 * @flags: Region state flags 490 * @params: active + config params for the region 491 */ 492 struct cxl_region { 493 struct device dev; 494 int id; 495 enum cxl_decoder_mode mode; 496 enum cxl_decoder_type type; 497 struct cxl_nvdimm_bridge *cxl_nvb; 498 struct cxl_pmem_region *cxlr_pmem; 499 unsigned long flags; 500 struct cxl_region_params params; 501 }; 502 503 struct cxl_nvdimm_bridge { 504 int id; 505 struct device dev; 506 struct cxl_port *port; 507 struct nvdimm_bus *nvdimm_bus; 508 struct nvdimm_bus_descriptor nd_desc; 509 }; 510 511 #define CXL_DEV_ID_LEN 19 512 513 struct cxl_nvdimm { 514 struct device dev; 515 struct cxl_memdev *cxlmd; 516 u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */ 517 }; 518 519 struct cxl_pmem_region_mapping { 520 struct cxl_memdev *cxlmd; 521 struct cxl_nvdimm *cxl_nvd; 522 u64 start; 523 u64 size; 524 int position; 525 }; 526 527 struct cxl_pmem_region { 528 struct device dev; 529 struct cxl_region *cxlr; 530 struct nd_region *nd_region; 531 struct range hpa_range; 532 int nr_mappings; 533 struct cxl_pmem_region_mapping mapping[]; 534 }; 535 536 struct cxl_dax_region { 537 struct device dev; 538 struct cxl_region *cxlr; 539 struct range hpa_range; 540 }; 541 542 /** 543 * struct cxl_port - logical collection of upstream port devices and 544 * downstream port devices to construct a CXL memory 545 * decode hierarchy. 546 * @dev: this port's device 547 * @uport: PCI or platform device implementing the upstream port capability 548 * @host_bridge: Shortcut to the platform attach point for this port 549 * @id: id for port device-name 550 * @dports: cxl_dport instances referenced by decoders 551 * @endpoints: cxl_ep instances, endpoints that are a descendant of this port 552 * @regions: cxl_region_ref instances, regions mapped by this port 553 * @parent_dport: dport that points to this port in the parent 554 * @decoder_ida: allocator for decoder ids 555 * @nr_dports: number of entries in @dports 556 * @hdm_end: track last allocated HDM decoder instance for allocation ordering 557 * @commit_end: cursor to track highest committed decoder for commit ordering 558 * @component_reg_phys: component register capability base address (optional) 559 * @dead: last ep has been removed, force port re-creation 560 * @depth: How deep this port is relative to the root. depth 0 is the root. 561 * @cdat: Cached CDAT data 562 * @cdat_available: Should a CDAT attribute be available in sysfs 563 */ 564 struct cxl_port { 565 struct device dev; 566 struct device *uport; 567 struct device *host_bridge; 568 int id; 569 struct xarray dports; 570 struct xarray endpoints; 571 struct xarray regions; 572 struct cxl_dport *parent_dport; 573 struct ida decoder_ida; 574 int nr_dports; 575 int hdm_end; 576 int commit_end; 577 resource_size_t component_reg_phys; 578 bool dead; 579 unsigned int depth; 580 struct cxl_cdat { 581 void *table; 582 size_t length; 583 } cdat; 584 bool cdat_available; 585 }; 586 587 static inline struct cxl_dport * 588 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) 589 { 590 return xa_load(&port->dports, (unsigned long)dport_dev); 591 } 592 593 /** 594 * struct cxl_dport - CXL downstream port 595 * @dport: PCI bridge or firmware device representing the downstream link 596 * @port_id: unique hardware identifier for dport in decoder target list 597 * @component_reg_phys: downstream port component registers 598 * @rcrb: base address for the Root Complex Register Block 599 * @rch: Indicate whether this dport was enumerated in RCH or VH mode 600 * @port: reference to cxl_port that contains this downstream port 601 */ 602 struct cxl_dport { 603 struct device *dport; 604 int port_id; 605 resource_size_t component_reg_phys; 606 resource_size_t rcrb; 607 bool rch; 608 struct cxl_port *port; 609 }; 610 611 /** 612 * struct cxl_ep - track an endpoint's interest in a port 613 * @ep: device that hosts a generic CXL endpoint (expander or accelerator) 614 * @dport: which dport routes to this endpoint on @port 615 * @next: cxl switch port across the link attached to @dport NULL if 616 * attached to an endpoint 617 */ 618 struct cxl_ep { 619 struct device *ep; 620 struct cxl_dport *dport; 621 struct cxl_port *next; 622 }; 623 624 /** 625 * struct cxl_region_ref - track a region's interest in a port 626 * @port: point in topology to install this reference 627 * @decoder: decoder assigned for @region in @port 628 * @region: region for this reference 629 * @endpoints: cxl_ep references for region members beneath @port 630 * @nr_targets_set: track how many targets have been programmed during setup 631 * @nr_eps: number of endpoints beneath @port 632 * @nr_targets: number of distinct targets needed to reach @nr_eps 633 */ 634 struct cxl_region_ref { 635 struct cxl_port *port; 636 struct cxl_decoder *decoder; 637 struct cxl_region *region; 638 struct xarray endpoints; 639 int nr_targets_set; 640 int nr_eps; 641 int nr_targets; 642 }; 643 644 /* 645 * The platform firmware device hosting the root is also the top of the 646 * CXL port topology. All other CXL ports have another CXL port as their 647 * parent and their ->uport / host device is out-of-line of the port 648 * ancestry. 649 */ 650 static inline bool is_cxl_root(struct cxl_port *port) 651 { 652 return port->uport == port->dev.parent; 653 } 654 655 bool is_cxl_port(const struct device *dev); 656 struct cxl_port *to_cxl_port(const struct device *dev); 657 struct pci_bus; 658 int devm_cxl_register_pci_bus(struct device *host, struct device *uport, 659 struct pci_bus *bus); 660 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); 661 struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport, 662 resource_size_t component_reg_phys, 663 struct cxl_dport *parent_dport); 664 struct cxl_port *find_cxl_root(struct cxl_port *port); 665 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); 666 void cxl_bus_rescan(void); 667 void cxl_bus_drain(void); 668 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, 669 struct cxl_dport **dport); 670 bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); 671 672 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, 673 struct device *dport, int port_id, 674 resource_size_t component_reg_phys); 675 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, 676 struct device *dport_dev, int port_id, 677 resource_size_t component_reg_phys, 678 resource_size_t rcrb); 679 680 struct cxl_decoder *to_cxl_decoder(struct device *dev); 681 struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); 682 struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); 683 struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev); 684 bool is_root_decoder(struct device *dev); 685 bool is_switch_decoder(struct device *dev); 686 bool is_endpoint_decoder(struct device *dev); 687 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, 688 unsigned int nr_targets, 689 cxl_calc_hb_fn calc_hb); 690 struct cxl_dport *cxl_hb_modulo(struct cxl_root_decoder *cxlrd, int pos); 691 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, 692 unsigned int nr_targets); 693 int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map); 694 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port); 695 int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map); 696 int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld); 697 int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint); 698 699 /** 700 * struct cxl_endpoint_dvsec_info - Cached DVSEC info 701 * @mem_enabled: cached value of mem_enabled in the DVSEC at init time 702 * @ranges: Number of active HDM ranges this device uses. 703 * @port: endpoint port associated with this info instance 704 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE 705 */ 706 struct cxl_endpoint_dvsec_info { 707 bool mem_enabled; 708 int ranges; 709 struct cxl_port *port; 710 struct range dvsec_range[2]; 711 }; 712 713 struct cxl_hdm; 714 struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port, 715 struct cxl_endpoint_dvsec_info *info); 716 int devm_cxl_enable_hdm(struct cxl_port *port, struct cxl_hdm *cxlhdm); 717 int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, 718 struct cxl_endpoint_dvsec_info *info); 719 int devm_cxl_add_passthrough_decoder(struct cxl_port *port); 720 int cxl_dvsec_rr_decode(struct device *dev, int dvsec, 721 struct cxl_endpoint_dvsec_info *info); 722 723 bool is_cxl_region(struct device *dev); 724 725 extern struct bus_type cxl_bus_type; 726 727 struct cxl_driver { 728 const char *name; 729 int (*probe)(struct device *dev); 730 void (*remove)(struct device *dev); 731 struct device_driver drv; 732 int id; 733 }; 734 735 static inline struct cxl_driver *to_cxl_drv(struct device_driver *drv) 736 { 737 return container_of(drv, struct cxl_driver, drv); 738 } 739 740 int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, 741 const char *modname); 742 #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME) 743 void cxl_driver_unregister(struct cxl_driver *cxl_drv); 744 745 #define module_cxl_driver(__cxl_driver) \ 746 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister) 747 748 #define CXL_DEVICE_NVDIMM_BRIDGE 1 749 #define CXL_DEVICE_NVDIMM 2 750 #define CXL_DEVICE_PORT 3 751 #define CXL_DEVICE_ROOT 4 752 #define CXL_DEVICE_MEMORY_EXPANDER 5 753 #define CXL_DEVICE_REGION 6 754 #define CXL_DEVICE_PMEM_REGION 7 755 #define CXL_DEVICE_DAX_REGION 8 756 757 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") 758 #define CXL_MODALIAS_FMT "cxl:t%d" 759 760 struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev); 761 struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, 762 struct cxl_port *port); 763 struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); 764 bool is_cxl_nvdimm(struct device *dev); 765 bool is_cxl_nvdimm_bridge(struct device *dev); 766 int devm_cxl_add_nvdimm(struct cxl_memdev *cxlmd); 767 struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd); 768 769 #ifdef CONFIG_CXL_REGION 770 bool is_cxl_pmem_region(struct device *dev); 771 struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); 772 int cxl_add_to_region(struct cxl_port *root, 773 struct cxl_endpoint_decoder *cxled); 774 struct cxl_dax_region *to_cxl_dax_region(struct device *dev); 775 #else 776 static inline bool is_cxl_pmem_region(struct device *dev) 777 { 778 return false; 779 } 780 static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) 781 { 782 return NULL; 783 } 784 static inline int cxl_add_to_region(struct cxl_port *root, 785 struct cxl_endpoint_decoder *cxled) 786 { 787 return 0; 788 } 789 static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev) 790 { 791 return NULL; 792 } 793 #endif 794 795 /* 796 * Unit test builds overrides this to __weak, find the 'strong' version 797 * of these symbols in tools/testing/cxl/. 798 */ 799 #ifndef __mock 800 #define __mock static 801 #endif 802 803 #endif /* __CXL_H__ */ 804