1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020 Intel Corporation. */ 3 4 #ifndef __CXL_H__ 5 #define __CXL_H__ 6 7 #include <linux/libnvdimm.h> 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/log2.h> 11 #include <linux/io.h> 12 13 /** 14 * DOC: cxl objects 15 * 16 * The CXL core objects like ports, decoders, and regions are shared 17 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers 18 * (port-driver, region-driver, nvdimm object-drivers... etc). 19 */ 20 21 /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ 22 #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K 23 24 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/ 25 #define CXL_CM_OFFSET 0x1000 26 #define CXL_CM_CAP_HDR_OFFSET 0x0 27 #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0) 28 #define CM_CAP_HDR_CAP_ID 1 29 #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16) 30 #define CM_CAP_HDR_CAP_VERSION 1 31 #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20) 32 #define CM_CAP_HDR_CACHE_MEM_VERSION 1 33 #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24) 34 #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20) 35 36 #define CXL_CM_CAP_CAP_ID_RAS 0x2 37 #define CXL_CM_CAP_CAP_ID_HDM 0x5 38 #define CXL_CM_CAP_CAP_HDM_VERSION 1 39 40 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ 41 #define CXL_HDM_DECODER_CAP_OFFSET 0x0 42 #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0) 43 #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) 44 #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) 45 #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) 46 #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 47 #define CXL_HDM_DECODER_ENABLE BIT(1) 48 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) 49 #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14) 50 #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18) 51 #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c) 52 #define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) 53 #define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0) 54 #define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4) 55 #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8) 56 #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9) 57 #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10) 58 #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11) 59 #define CXL_HDM_DECODER0_CTRL_TYPE BIT(12) 60 #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24) 61 #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28) 62 #define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i) 63 #define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i) 64 65 /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */ 66 #define CXL_DECODER_MIN_GRANULARITY 256 67 #define CXL_DECODER_MAX_ENCODED_IG 6 68 69 static inline int cxl_hdm_decoder_count(u32 cap_hdr) 70 { 71 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr); 72 73 return val ? val * 2 : 1; 74 } 75 76 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ 77 static inline int eig_to_granularity(u16 eig, unsigned int *granularity) 78 { 79 if (eig > CXL_DECODER_MAX_ENCODED_IG) 80 return -EINVAL; 81 *granularity = CXL_DECODER_MIN_GRANULARITY << eig; 82 return 0; 83 } 84 85 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */ 86 static inline int eiw_to_ways(u8 eiw, unsigned int *ways) 87 { 88 switch (eiw) { 89 case 0 ... 4: 90 *ways = 1 << eiw; 91 break; 92 case 8 ... 10: 93 *ways = 3 << (eiw - 8); 94 break; 95 default: 96 return -EINVAL; 97 } 98 99 return 0; 100 } 101 102 static inline int granularity_to_eig(int granularity, u16 *eig) 103 { 104 if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY || 105 !is_power_of_2(granularity)) 106 return -EINVAL; 107 *eig = ilog2(granularity) - 8; 108 return 0; 109 } 110 111 static inline int ways_to_eiw(unsigned int ways, u8 *eiw) 112 { 113 if (ways > 16) 114 return -EINVAL; 115 if (is_power_of_2(ways)) { 116 *eiw = ilog2(ways); 117 return 0; 118 } 119 if (ways % 3) 120 return -EINVAL; 121 ways /= 3; 122 if (!is_power_of_2(ways)) 123 return -EINVAL; 124 *eiw = ilog2(ways) + 8; 125 return 0; 126 } 127 128 /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */ 129 #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0 130 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 131 #define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4 132 #define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 133 #define CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK BIT(8) 134 #define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8 135 #define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 136 #define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC 137 #define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0) 138 #define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10 139 #define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0) 140 #define CXL_RAS_CAP_CONTROL_OFFSET 0x14 141 #define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0) 142 #define CXL_RAS_HEADER_LOG_OFFSET 0x18 143 #define CXL_RAS_CAPABILITY_LENGTH 0x58 144 #define CXL_HEADERLOG_SIZE SZ_512 145 #define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32) 146 147 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ 148 #define CXLDEV_CAP_ARRAY_OFFSET 0x0 149 #define CXLDEV_CAP_ARRAY_CAP_ID 0 150 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) 151 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) 152 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ 153 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0) 154 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */ 155 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1 156 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2 157 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3 158 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000 159 160 /* CXL 3.0 8.2.8.3.1 Event Status Register */ 161 #define CXLDEV_DEV_EVENT_STATUS_OFFSET 0x00 162 #define CXLDEV_EVENT_STATUS_INFO BIT(0) 163 #define CXLDEV_EVENT_STATUS_WARN BIT(1) 164 #define CXLDEV_EVENT_STATUS_FAIL BIT(2) 165 #define CXLDEV_EVENT_STATUS_FATAL BIT(3) 166 167 #define CXLDEV_EVENT_STATUS_ALL (CXLDEV_EVENT_STATUS_INFO | \ 168 CXLDEV_EVENT_STATUS_WARN | \ 169 CXLDEV_EVENT_STATUS_FAIL | \ 170 CXLDEV_EVENT_STATUS_FATAL) 171 172 /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */ 173 #define CXLDEV_EVENT_INT_MODE_MASK GENMASK(1, 0) 174 #define CXLDEV_EVENT_INT_MSGNUM_MASK GENMASK(7, 4) 175 176 /* CXL 2.0 8.2.8.4 Mailbox Registers */ 177 #define CXLDEV_MBOX_CAPS_OFFSET 0x00 178 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) 179 #define CXLDEV_MBOX_CAP_BG_CMD_IRQ BIT(6) 180 #define CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK GENMASK(10, 7) 181 #define CXLDEV_MBOX_CTRL_OFFSET 0x04 182 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) 183 #define CXLDEV_MBOX_CTRL_BG_CMD_IRQ BIT(2) 184 #define CXLDEV_MBOX_CMD_OFFSET 0x08 185 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 186 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16) 187 #define CXLDEV_MBOX_STATUS_OFFSET 0x10 188 #define CXLDEV_MBOX_STATUS_BG_CMD BIT(0) 189 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32) 190 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 191 #define CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 192 #define CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK GENMASK_ULL(22, 16) 193 #define CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK GENMASK_ULL(47, 32) 194 #define CXLDEV_MBOX_BG_CMD_COMMAND_VENDOR_MASK GENMASK_ULL(63, 48) 195 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 196 197 /* 198 * Using struct_group() allows for per register-block-type helper routines, 199 * without requiring block-type agnostic code to include the prefix. 200 */ 201 struct cxl_regs { 202 /* 203 * Common set of CXL Component register block base pointers 204 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure 205 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure 206 */ 207 struct_group_tagged(cxl_component_regs, component, 208 void __iomem *hdm_decoder; 209 void __iomem *ras; 210 ); 211 /* 212 * Common set of CXL Device register block base pointers 213 * @status: CXL 2.0 8.2.8.3 Device Status Registers 214 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers 215 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers 216 */ 217 struct_group_tagged(cxl_device_regs, device_regs, 218 void __iomem *status, *mbox, *memdev; 219 ); 220 }; 221 222 struct cxl_reg_map { 223 bool valid; 224 int id; 225 unsigned long offset; 226 unsigned long size; 227 }; 228 229 struct cxl_component_reg_map { 230 struct cxl_reg_map hdm_decoder; 231 struct cxl_reg_map ras; 232 }; 233 234 struct cxl_device_reg_map { 235 struct cxl_reg_map status; 236 struct cxl_reg_map mbox; 237 struct cxl_reg_map memdev; 238 }; 239 240 /** 241 * struct cxl_register_map - DVSEC harvested register block mapping parameters 242 * @base: virtual base of the register-block-BAR + @block_offset 243 * @resource: physical resource base of the register block 244 * @max_size: maximum mapping size to perform register search 245 * @reg_type: see enum cxl_regloc_type 246 * @component_map: cxl_reg_map for component registers 247 * @device_map: cxl_reg_maps for device registers 248 */ 249 struct cxl_register_map { 250 void __iomem *base; 251 resource_size_t resource; 252 resource_size_t max_size; 253 u8 reg_type; 254 union { 255 struct cxl_component_reg_map component_map; 256 struct cxl_device_reg_map device_map; 257 }; 258 }; 259 260 void cxl_probe_component_regs(struct device *dev, void __iomem *base, 261 struct cxl_component_reg_map *map); 262 void cxl_probe_device_regs(struct device *dev, void __iomem *base, 263 struct cxl_device_reg_map *map); 264 int cxl_map_component_regs(struct device *dev, struct cxl_component_regs *regs, 265 struct cxl_register_map *map, 266 unsigned long map_mask); 267 int cxl_map_device_regs(struct device *dev, struct cxl_device_regs *regs, 268 struct cxl_register_map *map); 269 270 enum cxl_regloc_type; 271 int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, 272 struct cxl_register_map *map); 273 274 enum cxl_rcrb { 275 CXL_RCRB_DOWNSTREAM, 276 CXL_RCRB_UPSTREAM, 277 }; 278 resource_size_t cxl_rcrb_to_component(struct device *dev, 279 resource_size_t rcrb, 280 enum cxl_rcrb which); 281 282 #define CXL_RESOURCE_NONE ((resource_size_t) -1) 283 #define CXL_TARGET_STRLEN 20 284 285 /* 286 * cxl_decoder flags that define the type of memory / devices this 287 * decoder supports as well as configuration lock status See "CXL 2.0 288 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. 289 * Additionally indicate whether decoder settings were autodetected, 290 * user customized. 291 */ 292 #define CXL_DECODER_F_RAM BIT(0) 293 #define CXL_DECODER_F_PMEM BIT(1) 294 #define CXL_DECODER_F_TYPE2 BIT(2) 295 #define CXL_DECODER_F_TYPE3 BIT(3) 296 #define CXL_DECODER_F_LOCK BIT(4) 297 #define CXL_DECODER_F_ENABLE BIT(5) 298 #define CXL_DECODER_F_MASK GENMASK(5, 0) 299 300 enum cxl_decoder_type { 301 CXL_DECODER_ACCELERATOR = 2, 302 CXL_DECODER_EXPANDER = 3, 303 }; 304 305 /* 306 * Current specification goes up to 8, double that seems a reasonable 307 * software max for the foreseeable future 308 */ 309 #define CXL_DECODER_MAX_INTERLEAVE 16 310 311 312 /** 313 * struct cxl_decoder - Common CXL HDM Decoder Attributes 314 * @dev: this decoder's device 315 * @id: kernel device name id 316 * @hpa_range: Host physical address range mapped by this decoder 317 * @interleave_ways: number of cxl_dports in this decode 318 * @interleave_granularity: data stride per dport 319 * @target_type: accelerator vs expander (type2 vs type3) selector 320 * @region: currently assigned region for this decoder 321 * @flags: memory type capabilities and locking 322 * @commit: device/decoder-type specific callback to commit settings to hw 323 * @reset: device/decoder-type specific callback to reset hw settings 324 */ 325 struct cxl_decoder { 326 struct device dev; 327 int id; 328 struct range hpa_range; 329 int interleave_ways; 330 int interleave_granularity; 331 enum cxl_decoder_type target_type; 332 struct cxl_region *region; 333 unsigned long flags; 334 int (*commit)(struct cxl_decoder *cxld); 335 int (*reset)(struct cxl_decoder *cxld); 336 }; 337 338 /* 339 * CXL_DECODER_DEAD prevents endpoints from being reattached to regions 340 * while cxld_unregister() is running 341 */ 342 enum cxl_decoder_mode { 343 CXL_DECODER_NONE, 344 CXL_DECODER_RAM, 345 CXL_DECODER_PMEM, 346 CXL_DECODER_MIXED, 347 CXL_DECODER_DEAD, 348 }; 349 350 static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode) 351 { 352 static const char * const names[] = { 353 [CXL_DECODER_NONE] = "none", 354 [CXL_DECODER_RAM] = "ram", 355 [CXL_DECODER_PMEM] = "pmem", 356 [CXL_DECODER_MIXED] = "mixed", 357 }; 358 359 if (mode >= CXL_DECODER_NONE && mode <= CXL_DECODER_MIXED) 360 return names[mode]; 361 return "mixed"; 362 } 363 364 /* 365 * Track whether this decoder is reserved for region autodiscovery, or 366 * free for userspace provisioning. 367 */ 368 enum cxl_decoder_state { 369 CXL_DECODER_STATE_MANUAL, 370 CXL_DECODER_STATE_AUTO, 371 }; 372 373 /** 374 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder 375 * @cxld: base cxl_decoder_object 376 * @dpa_res: actively claimed DPA span of this decoder 377 * @skip: offset into @dpa_res where @cxld.hpa_range maps 378 * @mode: which memory type / access-mode-partition this decoder targets 379 * @state: autodiscovery state 380 * @pos: interleave position in @cxld.region 381 */ 382 struct cxl_endpoint_decoder { 383 struct cxl_decoder cxld; 384 struct resource *dpa_res; 385 resource_size_t skip; 386 enum cxl_decoder_mode mode; 387 enum cxl_decoder_state state; 388 int pos; 389 }; 390 391 /** 392 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder 393 * @cxld: base cxl_decoder object 394 * @target_lock: coordinate coherent reads of the target list 395 * @nr_targets: number of elements in @target 396 * @target: active ordered target list in current decoder configuration 397 * 398 * The 'switch' decoder type represents the decoder instances of cxl_port's that 399 * route from the root of a CXL memory decode topology to the endpoints. They 400 * come in two flavors, root-level decoders, statically defined by platform 401 * firmware, and mid-level decoders, where interleave-granularity, 402 * interleave-width, and the target list are mutable. 403 */ 404 struct cxl_switch_decoder { 405 struct cxl_decoder cxld; 406 seqlock_t target_lock; 407 int nr_targets; 408 struct cxl_dport *target[]; 409 }; 410 411 struct cxl_root_decoder; 412 typedef struct cxl_dport *(*cxl_calc_hb_fn)(struct cxl_root_decoder *cxlrd, 413 int pos); 414 415 /** 416 * struct cxl_root_decoder - Static platform CXL address decoder 417 * @res: host / parent resource for region allocations 418 * @region_id: region id for next region provisioning event 419 * @calc_hb: which host bridge covers the n'th position by granularity 420 * @platform_data: platform specific configuration data 421 * @range_lock: sync region autodiscovery by address range 422 * @cxlsd: base cxl switch decoder 423 */ 424 struct cxl_root_decoder { 425 struct resource *res; 426 atomic_t region_id; 427 cxl_calc_hb_fn calc_hb; 428 void *platform_data; 429 struct mutex range_lock; 430 struct cxl_switch_decoder cxlsd; 431 }; 432 433 /* 434 * enum cxl_config_state - State machine for region configuration 435 * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely 436 * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more 437 * changes to interleave_ways or interleave_granularity 438 * @CXL_CONFIG_ACTIVE: All targets have been added the region is now 439 * active 440 * @CXL_CONFIG_RESET_PENDING: see commit_store() 441 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware 442 */ 443 enum cxl_config_state { 444 CXL_CONFIG_IDLE, 445 CXL_CONFIG_INTERLEAVE_ACTIVE, 446 CXL_CONFIG_ACTIVE, 447 CXL_CONFIG_RESET_PENDING, 448 CXL_CONFIG_COMMIT, 449 }; 450 451 /** 452 * struct cxl_region_params - region settings 453 * @state: allow the driver to lockdown further parameter changes 454 * @uuid: unique id for persistent regions 455 * @interleave_ways: number of endpoints in the region 456 * @interleave_granularity: capacity each endpoint contributes to a stripe 457 * @res: allocated iomem capacity for this region 458 * @targets: active ordered targets in current decoder configuration 459 * @nr_targets: number of targets 460 * 461 * State transitions are protected by the cxl_region_rwsem 462 */ 463 struct cxl_region_params { 464 enum cxl_config_state state; 465 uuid_t uuid; 466 int interleave_ways; 467 int interleave_granularity; 468 struct resource *res; 469 struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; 470 int nr_targets; 471 }; 472 473 /* 474 * Flag whether this region needs to have its HPA span synchronized with 475 * CPU cache state at region activation time. 476 */ 477 #define CXL_REGION_F_INCOHERENT 0 478 479 /* 480 * Indicate whether this region has been assembled by autodetection or 481 * userspace assembly. Prevent endpoint decoders outside of automatic 482 * detection from being added to the region. 483 */ 484 #define CXL_REGION_F_AUTO 1 485 486 /** 487 * struct cxl_region - CXL region 488 * @dev: This region's device 489 * @id: This region's id. Id is globally unique across all regions 490 * @mode: Endpoint decoder allocation / access mode 491 * @type: Endpoint decoder target type 492 * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown 493 * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge 494 * @flags: Region state flags 495 * @params: active + config params for the region 496 */ 497 struct cxl_region { 498 struct device dev; 499 int id; 500 enum cxl_decoder_mode mode; 501 enum cxl_decoder_type type; 502 struct cxl_nvdimm_bridge *cxl_nvb; 503 struct cxl_pmem_region *cxlr_pmem; 504 unsigned long flags; 505 struct cxl_region_params params; 506 }; 507 508 struct cxl_nvdimm_bridge { 509 int id; 510 struct device dev; 511 struct cxl_port *port; 512 struct nvdimm_bus *nvdimm_bus; 513 struct nvdimm_bus_descriptor nd_desc; 514 }; 515 516 #define CXL_DEV_ID_LEN 19 517 518 struct cxl_nvdimm { 519 struct device dev; 520 struct cxl_memdev *cxlmd; 521 u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */ 522 }; 523 524 struct cxl_pmem_region_mapping { 525 struct cxl_memdev *cxlmd; 526 struct cxl_nvdimm *cxl_nvd; 527 u64 start; 528 u64 size; 529 int position; 530 }; 531 532 struct cxl_pmem_region { 533 struct device dev; 534 struct cxl_region *cxlr; 535 struct nd_region *nd_region; 536 struct range hpa_range; 537 int nr_mappings; 538 struct cxl_pmem_region_mapping mapping[]; 539 }; 540 541 struct cxl_dax_region { 542 struct device dev; 543 struct cxl_region *cxlr; 544 struct range hpa_range; 545 }; 546 547 /** 548 * struct cxl_port - logical collection of upstream port devices and 549 * downstream port devices to construct a CXL memory 550 * decode hierarchy. 551 * @dev: this port's device 552 * @uport: PCI or platform device implementing the upstream port capability 553 * @host_bridge: Shortcut to the platform attach point for this port 554 * @id: id for port device-name 555 * @dports: cxl_dport instances referenced by decoders 556 * @endpoints: cxl_ep instances, endpoints that are a descendant of this port 557 * @regions: cxl_region_ref instances, regions mapped by this port 558 * @parent_dport: dport that points to this port in the parent 559 * @decoder_ida: allocator for decoder ids 560 * @nr_dports: number of entries in @dports 561 * @hdm_end: track last allocated HDM decoder instance for allocation ordering 562 * @commit_end: cursor to track highest committed decoder for commit ordering 563 * @component_reg_phys: component register capability base address (optional) 564 * @dead: last ep has been removed, force port re-creation 565 * @depth: How deep this port is relative to the root. depth 0 is the root. 566 * @cdat: Cached CDAT data 567 * @cdat_available: Should a CDAT attribute be available in sysfs 568 */ 569 struct cxl_port { 570 struct device dev; 571 struct device *uport; 572 struct device *host_bridge; 573 int id; 574 struct xarray dports; 575 struct xarray endpoints; 576 struct xarray regions; 577 struct cxl_dport *parent_dport; 578 struct ida decoder_ida; 579 int nr_dports; 580 int hdm_end; 581 int commit_end; 582 resource_size_t component_reg_phys; 583 bool dead; 584 unsigned int depth; 585 struct cxl_cdat { 586 void *table; 587 size_t length; 588 } cdat; 589 bool cdat_available; 590 }; 591 592 static inline struct cxl_dport * 593 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) 594 { 595 return xa_load(&port->dports, (unsigned long)dport_dev); 596 } 597 598 /** 599 * struct cxl_dport - CXL downstream port 600 * @dport: PCI bridge or firmware device representing the downstream link 601 * @port_id: unique hardware identifier for dport in decoder target list 602 * @component_reg_phys: downstream port component registers 603 * @rcrb: base address for the Root Complex Register Block 604 * @rch: Indicate whether this dport was enumerated in RCH or VH mode 605 * @port: reference to cxl_port that contains this downstream port 606 */ 607 struct cxl_dport { 608 struct device *dport; 609 int port_id; 610 resource_size_t component_reg_phys; 611 resource_size_t rcrb; 612 bool rch; 613 struct cxl_port *port; 614 }; 615 616 /** 617 * struct cxl_ep - track an endpoint's interest in a port 618 * @ep: device that hosts a generic CXL endpoint (expander or accelerator) 619 * @dport: which dport routes to this endpoint on @port 620 * @next: cxl switch port across the link attached to @dport NULL if 621 * attached to an endpoint 622 */ 623 struct cxl_ep { 624 struct device *ep; 625 struct cxl_dport *dport; 626 struct cxl_port *next; 627 }; 628 629 /** 630 * struct cxl_region_ref - track a region's interest in a port 631 * @port: point in topology to install this reference 632 * @decoder: decoder assigned for @region in @port 633 * @region: region for this reference 634 * @endpoints: cxl_ep references for region members beneath @port 635 * @nr_targets_set: track how many targets have been programmed during setup 636 * @nr_eps: number of endpoints beneath @port 637 * @nr_targets: number of distinct targets needed to reach @nr_eps 638 */ 639 struct cxl_region_ref { 640 struct cxl_port *port; 641 struct cxl_decoder *decoder; 642 struct cxl_region *region; 643 struct xarray endpoints; 644 int nr_targets_set; 645 int nr_eps; 646 int nr_targets; 647 }; 648 649 /* 650 * The platform firmware device hosting the root is also the top of the 651 * CXL port topology. All other CXL ports have another CXL port as their 652 * parent and their ->uport / host device is out-of-line of the port 653 * ancestry. 654 */ 655 static inline bool is_cxl_root(struct cxl_port *port) 656 { 657 return port->uport == port->dev.parent; 658 } 659 660 bool is_cxl_port(const struct device *dev); 661 struct cxl_port *to_cxl_port(const struct device *dev); 662 struct pci_bus; 663 int devm_cxl_register_pci_bus(struct device *host, struct device *uport, 664 struct pci_bus *bus); 665 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); 666 struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport, 667 resource_size_t component_reg_phys, 668 struct cxl_dport *parent_dport); 669 struct cxl_port *find_cxl_root(struct cxl_port *port); 670 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); 671 void cxl_bus_rescan(void); 672 void cxl_bus_drain(void); 673 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, 674 struct cxl_dport **dport); 675 bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); 676 677 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, 678 struct device *dport, int port_id, 679 resource_size_t component_reg_phys); 680 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, 681 struct device *dport_dev, int port_id, 682 resource_size_t component_reg_phys, 683 resource_size_t rcrb); 684 685 struct cxl_decoder *to_cxl_decoder(struct device *dev); 686 struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); 687 struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); 688 struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev); 689 bool is_root_decoder(struct device *dev); 690 bool is_switch_decoder(struct device *dev); 691 bool is_endpoint_decoder(struct device *dev); 692 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, 693 unsigned int nr_targets, 694 cxl_calc_hb_fn calc_hb); 695 struct cxl_dport *cxl_hb_modulo(struct cxl_root_decoder *cxlrd, int pos); 696 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, 697 unsigned int nr_targets); 698 int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map); 699 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port); 700 int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map); 701 int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld); 702 int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint); 703 704 /** 705 * struct cxl_endpoint_dvsec_info - Cached DVSEC info 706 * @mem_enabled: cached value of mem_enabled in the DVSEC at init time 707 * @ranges: Number of active HDM ranges this device uses. 708 * @port: endpoint port associated with this info instance 709 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE 710 */ 711 struct cxl_endpoint_dvsec_info { 712 bool mem_enabled; 713 int ranges; 714 struct cxl_port *port; 715 struct range dvsec_range[2]; 716 }; 717 718 struct cxl_hdm; 719 struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port, 720 struct cxl_endpoint_dvsec_info *info); 721 int devm_cxl_enable_hdm(struct cxl_port *port, struct cxl_hdm *cxlhdm); 722 int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, 723 struct cxl_endpoint_dvsec_info *info); 724 int devm_cxl_add_passthrough_decoder(struct cxl_port *port); 725 int cxl_dvsec_rr_decode(struct device *dev, int dvsec, 726 struct cxl_endpoint_dvsec_info *info); 727 728 bool is_cxl_region(struct device *dev); 729 730 extern struct bus_type cxl_bus_type; 731 732 struct cxl_driver { 733 const char *name; 734 int (*probe)(struct device *dev); 735 void (*remove)(struct device *dev); 736 struct device_driver drv; 737 int id; 738 }; 739 740 static inline struct cxl_driver *to_cxl_drv(struct device_driver *drv) 741 { 742 return container_of(drv, struct cxl_driver, drv); 743 } 744 745 int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, 746 const char *modname); 747 #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME) 748 void cxl_driver_unregister(struct cxl_driver *cxl_drv); 749 750 #define module_cxl_driver(__cxl_driver) \ 751 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister) 752 753 #define CXL_DEVICE_NVDIMM_BRIDGE 1 754 #define CXL_DEVICE_NVDIMM 2 755 #define CXL_DEVICE_PORT 3 756 #define CXL_DEVICE_ROOT 4 757 #define CXL_DEVICE_MEMORY_EXPANDER 5 758 #define CXL_DEVICE_REGION 6 759 #define CXL_DEVICE_PMEM_REGION 7 760 #define CXL_DEVICE_DAX_REGION 8 761 762 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") 763 #define CXL_MODALIAS_FMT "cxl:t%d" 764 765 struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev); 766 struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, 767 struct cxl_port *port); 768 struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); 769 bool is_cxl_nvdimm(struct device *dev); 770 bool is_cxl_nvdimm_bridge(struct device *dev); 771 int devm_cxl_add_nvdimm(struct cxl_memdev *cxlmd); 772 struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd); 773 774 #ifdef CONFIG_CXL_REGION 775 bool is_cxl_pmem_region(struct device *dev); 776 struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); 777 int cxl_add_to_region(struct cxl_port *root, 778 struct cxl_endpoint_decoder *cxled); 779 struct cxl_dax_region *to_cxl_dax_region(struct device *dev); 780 #else 781 static inline bool is_cxl_pmem_region(struct device *dev) 782 { 783 return false; 784 } 785 static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) 786 { 787 return NULL; 788 } 789 static inline int cxl_add_to_region(struct cxl_port *root, 790 struct cxl_endpoint_decoder *cxled) 791 { 792 return 0; 793 } 794 static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev) 795 { 796 return NULL; 797 } 798 #endif 799 800 /* 801 * Unit test builds overrides this to __weak, find the 'strong' version 802 * of these symbols in tools/testing/cxl/. 803 */ 804 #ifndef __mock 805 #define __mock static 806 #endif 807 808 #endif /* __CXL_H__ */ 809