1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020 Intel Corporation. */ 3 4 #ifndef __CXL_H__ 5 #define __CXL_H__ 6 7 #include <linux/libnvdimm.h> 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/log2.h> 11 #include <linux/io.h> 12 13 /** 14 * DOC: cxl objects 15 * 16 * The CXL core objects like ports, decoders, and regions are shared 17 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers 18 * (port-driver, region-driver, nvdimm object-drivers... etc). 19 */ 20 21 /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ 22 #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K 23 24 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/ 25 #define CXL_CM_OFFSET 0x1000 26 #define CXL_CM_CAP_HDR_OFFSET 0x0 27 #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0) 28 #define CM_CAP_HDR_CAP_ID 1 29 #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16) 30 #define CM_CAP_HDR_CAP_VERSION 1 31 #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20) 32 #define CM_CAP_HDR_CACHE_MEM_VERSION 1 33 #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24) 34 #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20) 35 36 #define CXL_CM_CAP_CAP_ID_RAS 0x2 37 #define CXL_CM_CAP_CAP_ID_HDM 0x5 38 #define CXL_CM_CAP_CAP_HDM_VERSION 1 39 40 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ 41 #define CXL_HDM_DECODER_CAP_OFFSET 0x0 42 #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0) 43 #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) 44 #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) 45 #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) 46 #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 47 #define CXL_HDM_DECODER_ENABLE BIT(1) 48 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) 49 #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14) 50 #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18) 51 #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c) 52 #define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) 53 #define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0) 54 #define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4) 55 #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8) 56 #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9) 57 #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10) 58 #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11) 59 #define CXL_HDM_DECODER0_CTRL_TYPE BIT(12) 60 #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24) 61 #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28) 62 #define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i) 63 #define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i) 64 65 /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */ 66 #define CXL_DECODER_MIN_GRANULARITY 256 67 #define CXL_DECODER_MAX_ENCODED_IG 6 68 69 static inline int cxl_hdm_decoder_count(u32 cap_hdr) 70 { 71 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr); 72 73 return val ? val * 2 : 1; 74 } 75 76 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ 77 static inline int eig_to_granularity(u16 eig, unsigned int *granularity) 78 { 79 if (eig > CXL_DECODER_MAX_ENCODED_IG) 80 return -EINVAL; 81 *granularity = CXL_DECODER_MIN_GRANULARITY << eig; 82 return 0; 83 } 84 85 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */ 86 static inline int eiw_to_ways(u8 eiw, unsigned int *ways) 87 { 88 switch (eiw) { 89 case 0 ... 4: 90 *ways = 1 << eiw; 91 break; 92 case 8 ... 10: 93 *ways = 3 << (eiw - 8); 94 break; 95 default: 96 return -EINVAL; 97 } 98 99 return 0; 100 } 101 102 static inline int granularity_to_eig(int granularity, u16 *eig) 103 { 104 if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY || 105 !is_power_of_2(granularity)) 106 return -EINVAL; 107 *eig = ilog2(granularity) - 8; 108 return 0; 109 } 110 111 static inline int ways_to_eiw(unsigned int ways, u8 *eiw) 112 { 113 if (ways > 16) 114 return -EINVAL; 115 if (is_power_of_2(ways)) { 116 *eiw = ilog2(ways); 117 return 0; 118 } 119 if (ways % 3) 120 return -EINVAL; 121 ways /= 3; 122 if (!is_power_of_2(ways)) 123 return -EINVAL; 124 *eiw = ilog2(ways) + 8; 125 return 0; 126 } 127 128 /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */ 129 #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0 130 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 131 #define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4 132 #define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 133 #define CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK BIT(8) 134 #define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8 135 #define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 136 #define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC 137 #define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0) 138 #define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10 139 #define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0) 140 #define CXL_RAS_CAP_CONTROL_OFFSET 0x14 141 #define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0) 142 #define CXL_RAS_HEADER_LOG_OFFSET 0x18 143 #define CXL_RAS_CAPABILITY_LENGTH 0x58 144 #define CXL_HEADERLOG_SIZE SZ_512 145 #define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32) 146 147 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ 148 #define CXLDEV_CAP_ARRAY_OFFSET 0x0 149 #define CXLDEV_CAP_ARRAY_CAP_ID 0 150 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) 151 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) 152 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ 153 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0) 154 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */ 155 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1 156 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2 157 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3 158 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000 159 160 /* CXL 3.0 8.2.8.3.1 Event Status Register */ 161 #define CXLDEV_DEV_EVENT_STATUS_OFFSET 0x00 162 #define CXLDEV_EVENT_STATUS_INFO BIT(0) 163 #define CXLDEV_EVENT_STATUS_WARN BIT(1) 164 #define CXLDEV_EVENT_STATUS_FAIL BIT(2) 165 #define CXLDEV_EVENT_STATUS_FATAL BIT(3) 166 167 #define CXLDEV_EVENT_STATUS_ALL (CXLDEV_EVENT_STATUS_INFO | \ 168 CXLDEV_EVENT_STATUS_WARN | \ 169 CXLDEV_EVENT_STATUS_FAIL | \ 170 CXLDEV_EVENT_STATUS_FATAL) 171 172 /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */ 173 #define CXLDEV_EVENT_INT_MODE_MASK GENMASK(1, 0) 174 #define CXLDEV_EVENT_INT_MSGNUM_MASK GENMASK(7, 4) 175 176 /* CXL 2.0 8.2.8.4 Mailbox Registers */ 177 #define CXLDEV_MBOX_CAPS_OFFSET 0x00 178 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) 179 #define CXLDEV_MBOX_CTRL_OFFSET 0x04 180 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) 181 #define CXLDEV_MBOX_CMD_OFFSET 0x08 182 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 183 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16) 184 #define CXLDEV_MBOX_STATUS_OFFSET 0x10 185 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32) 186 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 187 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 188 189 /* 190 * Using struct_group() allows for per register-block-type helper routines, 191 * without requiring block-type agnostic code to include the prefix. 192 */ 193 struct cxl_regs { 194 /* 195 * Common set of CXL Component register block base pointers 196 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure 197 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure 198 */ 199 struct_group_tagged(cxl_component_regs, component, 200 void __iomem *hdm_decoder; 201 void __iomem *ras; 202 ); 203 /* 204 * Common set of CXL Device register block base pointers 205 * @status: CXL 2.0 8.2.8.3 Device Status Registers 206 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers 207 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers 208 */ 209 struct_group_tagged(cxl_device_regs, device_regs, 210 void __iomem *status, *mbox, *memdev; 211 ); 212 213 struct_group_tagged(cxl_pmu_regs, pmu_regs, 214 void __iomem *pmu; 215 ); 216 }; 217 218 struct cxl_reg_map { 219 bool valid; 220 int id; 221 unsigned long offset; 222 unsigned long size; 223 }; 224 225 struct cxl_component_reg_map { 226 struct cxl_reg_map hdm_decoder; 227 struct cxl_reg_map ras; 228 }; 229 230 struct cxl_device_reg_map { 231 struct cxl_reg_map status; 232 struct cxl_reg_map mbox; 233 struct cxl_reg_map memdev; 234 }; 235 236 struct cxl_pmu_reg_map { 237 struct cxl_reg_map pmu; 238 }; 239 240 /** 241 * struct cxl_register_map - DVSEC harvested register block mapping parameters 242 * @base: virtual base of the register-block-BAR + @block_offset 243 * @resource: physical resource base of the register block 244 * @max_size: maximum mapping size to perform register search 245 * @reg_type: see enum cxl_regloc_type 246 * @component_map: cxl_reg_map for component registers 247 * @device_map: cxl_reg_maps for device registers 248 * @pmu_map: cxl_reg_maps for CXL Performance Monitoring Units 249 */ 250 struct cxl_register_map { 251 void __iomem *base; 252 resource_size_t resource; 253 resource_size_t max_size; 254 u8 reg_type; 255 union { 256 struct cxl_component_reg_map component_map; 257 struct cxl_device_reg_map device_map; 258 struct cxl_pmu_reg_map pmu_map; 259 }; 260 }; 261 262 void cxl_probe_component_regs(struct device *dev, void __iomem *base, 263 struct cxl_component_reg_map *map); 264 void cxl_probe_device_regs(struct device *dev, void __iomem *base, 265 struct cxl_device_reg_map *map); 266 int cxl_map_component_regs(struct device *dev, struct cxl_component_regs *regs, 267 struct cxl_register_map *map, 268 unsigned long map_mask); 269 int cxl_map_device_regs(struct device *dev, struct cxl_device_regs *regs, 270 struct cxl_register_map *map); 271 int cxl_map_pmu_regs(struct pci_dev *pdev, struct cxl_pmu_regs *regs, 272 struct cxl_register_map *map); 273 274 enum cxl_regloc_type; 275 int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type); 276 int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type, 277 struct cxl_register_map *map, int index); 278 int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, 279 struct cxl_register_map *map); 280 281 enum cxl_rcrb { 282 CXL_RCRB_DOWNSTREAM, 283 CXL_RCRB_UPSTREAM, 284 }; 285 resource_size_t cxl_rcrb_to_component(struct device *dev, 286 resource_size_t rcrb, 287 enum cxl_rcrb which); 288 289 #define CXL_RESOURCE_NONE ((resource_size_t) -1) 290 #define CXL_TARGET_STRLEN 20 291 292 /* 293 * cxl_decoder flags that define the type of memory / devices this 294 * decoder supports as well as configuration lock status See "CXL 2.0 295 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. 296 * Additionally indicate whether decoder settings were autodetected, 297 * user customized. 298 */ 299 #define CXL_DECODER_F_RAM BIT(0) 300 #define CXL_DECODER_F_PMEM BIT(1) 301 #define CXL_DECODER_F_TYPE2 BIT(2) 302 #define CXL_DECODER_F_TYPE3 BIT(3) 303 #define CXL_DECODER_F_LOCK BIT(4) 304 #define CXL_DECODER_F_ENABLE BIT(5) 305 #define CXL_DECODER_F_MASK GENMASK(5, 0) 306 307 enum cxl_decoder_type { 308 CXL_DECODER_ACCELERATOR = 2, 309 CXL_DECODER_EXPANDER = 3, 310 }; 311 312 /* 313 * Current specification goes up to 8, double that seems a reasonable 314 * software max for the foreseeable future 315 */ 316 #define CXL_DECODER_MAX_INTERLEAVE 16 317 318 319 /** 320 * struct cxl_decoder - Common CXL HDM Decoder Attributes 321 * @dev: this decoder's device 322 * @id: kernel device name id 323 * @hpa_range: Host physical address range mapped by this decoder 324 * @interleave_ways: number of cxl_dports in this decode 325 * @interleave_granularity: data stride per dport 326 * @target_type: accelerator vs expander (type2 vs type3) selector 327 * @region: currently assigned region for this decoder 328 * @flags: memory type capabilities and locking 329 * @commit: device/decoder-type specific callback to commit settings to hw 330 * @reset: device/decoder-type specific callback to reset hw settings 331 */ 332 struct cxl_decoder { 333 struct device dev; 334 int id; 335 struct range hpa_range; 336 int interleave_ways; 337 int interleave_granularity; 338 enum cxl_decoder_type target_type; 339 struct cxl_region *region; 340 unsigned long flags; 341 int (*commit)(struct cxl_decoder *cxld); 342 int (*reset)(struct cxl_decoder *cxld); 343 }; 344 345 /* 346 * CXL_DECODER_DEAD prevents endpoints from being reattached to regions 347 * while cxld_unregister() is running 348 */ 349 enum cxl_decoder_mode { 350 CXL_DECODER_NONE, 351 CXL_DECODER_RAM, 352 CXL_DECODER_PMEM, 353 CXL_DECODER_MIXED, 354 CXL_DECODER_DEAD, 355 }; 356 357 static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode) 358 { 359 static const char * const names[] = { 360 [CXL_DECODER_NONE] = "none", 361 [CXL_DECODER_RAM] = "ram", 362 [CXL_DECODER_PMEM] = "pmem", 363 [CXL_DECODER_MIXED] = "mixed", 364 }; 365 366 if (mode >= CXL_DECODER_NONE && mode <= CXL_DECODER_MIXED) 367 return names[mode]; 368 return "mixed"; 369 } 370 371 /* 372 * Track whether this decoder is reserved for region autodiscovery, or 373 * free for userspace provisioning. 374 */ 375 enum cxl_decoder_state { 376 CXL_DECODER_STATE_MANUAL, 377 CXL_DECODER_STATE_AUTO, 378 }; 379 380 /** 381 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder 382 * @cxld: base cxl_decoder_object 383 * @dpa_res: actively claimed DPA span of this decoder 384 * @skip: offset into @dpa_res where @cxld.hpa_range maps 385 * @mode: which memory type / access-mode-partition this decoder targets 386 * @state: autodiscovery state 387 * @pos: interleave position in @cxld.region 388 */ 389 struct cxl_endpoint_decoder { 390 struct cxl_decoder cxld; 391 struct resource *dpa_res; 392 resource_size_t skip; 393 enum cxl_decoder_mode mode; 394 enum cxl_decoder_state state; 395 int pos; 396 }; 397 398 /** 399 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder 400 * @cxld: base cxl_decoder object 401 * @target_lock: coordinate coherent reads of the target list 402 * @nr_targets: number of elements in @target 403 * @target: active ordered target list in current decoder configuration 404 * 405 * The 'switch' decoder type represents the decoder instances of cxl_port's that 406 * route from the root of a CXL memory decode topology to the endpoints. They 407 * come in two flavors, root-level decoders, statically defined by platform 408 * firmware, and mid-level decoders, where interleave-granularity, 409 * interleave-width, and the target list are mutable. 410 */ 411 struct cxl_switch_decoder { 412 struct cxl_decoder cxld; 413 seqlock_t target_lock; 414 int nr_targets; 415 struct cxl_dport *target[]; 416 }; 417 418 struct cxl_root_decoder; 419 typedef struct cxl_dport *(*cxl_calc_hb_fn)(struct cxl_root_decoder *cxlrd, 420 int pos); 421 422 /** 423 * struct cxl_root_decoder - Static platform CXL address decoder 424 * @res: host / parent resource for region allocations 425 * @region_id: region id for next region provisioning event 426 * @calc_hb: which host bridge covers the n'th position by granularity 427 * @platform_data: platform specific configuration data 428 * @range_lock: sync region autodiscovery by address range 429 * @cxlsd: base cxl switch decoder 430 */ 431 struct cxl_root_decoder { 432 struct resource *res; 433 atomic_t region_id; 434 cxl_calc_hb_fn calc_hb; 435 void *platform_data; 436 struct mutex range_lock; 437 struct cxl_switch_decoder cxlsd; 438 }; 439 440 /* 441 * enum cxl_config_state - State machine for region configuration 442 * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely 443 * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more 444 * changes to interleave_ways or interleave_granularity 445 * @CXL_CONFIG_ACTIVE: All targets have been added the region is now 446 * active 447 * @CXL_CONFIG_RESET_PENDING: see commit_store() 448 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware 449 */ 450 enum cxl_config_state { 451 CXL_CONFIG_IDLE, 452 CXL_CONFIG_INTERLEAVE_ACTIVE, 453 CXL_CONFIG_ACTIVE, 454 CXL_CONFIG_RESET_PENDING, 455 CXL_CONFIG_COMMIT, 456 }; 457 458 /** 459 * struct cxl_region_params - region settings 460 * @state: allow the driver to lockdown further parameter changes 461 * @uuid: unique id for persistent regions 462 * @interleave_ways: number of endpoints in the region 463 * @interleave_granularity: capacity each endpoint contributes to a stripe 464 * @res: allocated iomem capacity for this region 465 * @targets: active ordered targets in current decoder configuration 466 * @nr_targets: number of targets 467 * 468 * State transitions are protected by the cxl_region_rwsem 469 */ 470 struct cxl_region_params { 471 enum cxl_config_state state; 472 uuid_t uuid; 473 int interleave_ways; 474 int interleave_granularity; 475 struct resource *res; 476 struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; 477 int nr_targets; 478 }; 479 480 /* 481 * Flag whether this region needs to have its HPA span synchronized with 482 * CPU cache state at region activation time. 483 */ 484 #define CXL_REGION_F_INCOHERENT 0 485 486 /* 487 * Indicate whether this region has been assembled by autodetection or 488 * userspace assembly. Prevent endpoint decoders outside of automatic 489 * detection from being added to the region. 490 */ 491 #define CXL_REGION_F_AUTO 1 492 493 /** 494 * struct cxl_region - CXL region 495 * @dev: This region's device 496 * @id: This region's id. Id is globally unique across all regions 497 * @mode: Endpoint decoder allocation / access mode 498 * @type: Endpoint decoder target type 499 * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown 500 * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge 501 * @flags: Region state flags 502 * @params: active + config params for the region 503 */ 504 struct cxl_region { 505 struct device dev; 506 int id; 507 enum cxl_decoder_mode mode; 508 enum cxl_decoder_type type; 509 struct cxl_nvdimm_bridge *cxl_nvb; 510 struct cxl_pmem_region *cxlr_pmem; 511 unsigned long flags; 512 struct cxl_region_params params; 513 }; 514 515 struct cxl_nvdimm_bridge { 516 int id; 517 struct device dev; 518 struct cxl_port *port; 519 struct nvdimm_bus *nvdimm_bus; 520 struct nvdimm_bus_descriptor nd_desc; 521 }; 522 523 #define CXL_DEV_ID_LEN 19 524 525 struct cxl_nvdimm { 526 struct device dev; 527 struct cxl_memdev *cxlmd; 528 u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */ 529 }; 530 531 struct cxl_pmem_region_mapping { 532 struct cxl_memdev *cxlmd; 533 struct cxl_nvdimm *cxl_nvd; 534 u64 start; 535 u64 size; 536 int position; 537 }; 538 539 struct cxl_pmem_region { 540 struct device dev; 541 struct cxl_region *cxlr; 542 struct nd_region *nd_region; 543 struct range hpa_range; 544 int nr_mappings; 545 struct cxl_pmem_region_mapping mapping[]; 546 }; 547 548 struct cxl_dax_region { 549 struct device dev; 550 struct cxl_region *cxlr; 551 struct range hpa_range; 552 }; 553 554 /** 555 * struct cxl_port - logical collection of upstream port devices and 556 * downstream port devices to construct a CXL memory 557 * decode hierarchy. 558 * @dev: this port's device 559 * @uport: PCI or platform device implementing the upstream port capability 560 * @host_bridge: Shortcut to the platform attach point for this port 561 * @id: id for port device-name 562 * @dports: cxl_dport instances referenced by decoders 563 * @endpoints: cxl_ep instances, endpoints that are a descendant of this port 564 * @regions: cxl_region_ref instances, regions mapped by this port 565 * @parent_dport: dport that points to this port in the parent 566 * @decoder_ida: allocator for decoder ids 567 * @nr_dports: number of entries in @dports 568 * @hdm_end: track last allocated HDM decoder instance for allocation ordering 569 * @commit_end: cursor to track highest committed decoder for commit ordering 570 * @component_reg_phys: component register capability base address (optional) 571 * @dead: last ep has been removed, force port re-creation 572 * @depth: How deep this port is relative to the root. depth 0 is the root. 573 * @cdat: Cached CDAT data 574 * @cdat_available: Should a CDAT attribute be available in sysfs 575 */ 576 struct cxl_port { 577 struct device dev; 578 struct device *uport; 579 struct device *host_bridge; 580 int id; 581 struct xarray dports; 582 struct xarray endpoints; 583 struct xarray regions; 584 struct cxl_dport *parent_dport; 585 struct ida decoder_ida; 586 int nr_dports; 587 int hdm_end; 588 int commit_end; 589 resource_size_t component_reg_phys; 590 bool dead; 591 unsigned int depth; 592 struct cxl_cdat { 593 void *table; 594 size_t length; 595 } cdat; 596 bool cdat_available; 597 }; 598 599 static inline struct cxl_dport * 600 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) 601 { 602 return xa_load(&port->dports, (unsigned long)dport_dev); 603 } 604 605 /** 606 * struct cxl_dport - CXL downstream port 607 * @dport: PCI bridge or firmware device representing the downstream link 608 * @port_id: unique hardware identifier for dport in decoder target list 609 * @component_reg_phys: downstream port component registers 610 * @rcrb: base address for the Root Complex Register Block 611 * @rch: Indicate whether this dport was enumerated in RCH or VH mode 612 * @port: reference to cxl_port that contains this downstream port 613 */ 614 struct cxl_dport { 615 struct device *dport; 616 int port_id; 617 resource_size_t component_reg_phys; 618 resource_size_t rcrb; 619 bool rch; 620 struct cxl_port *port; 621 }; 622 623 /** 624 * struct cxl_ep - track an endpoint's interest in a port 625 * @ep: device that hosts a generic CXL endpoint (expander or accelerator) 626 * @dport: which dport routes to this endpoint on @port 627 * @next: cxl switch port across the link attached to @dport NULL if 628 * attached to an endpoint 629 */ 630 struct cxl_ep { 631 struct device *ep; 632 struct cxl_dport *dport; 633 struct cxl_port *next; 634 }; 635 636 /** 637 * struct cxl_region_ref - track a region's interest in a port 638 * @port: point in topology to install this reference 639 * @decoder: decoder assigned for @region in @port 640 * @region: region for this reference 641 * @endpoints: cxl_ep references for region members beneath @port 642 * @nr_targets_set: track how many targets have been programmed during setup 643 * @nr_eps: number of endpoints beneath @port 644 * @nr_targets: number of distinct targets needed to reach @nr_eps 645 */ 646 struct cxl_region_ref { 647 struct cxl_port *port; 648 struct cxl_decoder *decoder; 649 struct cxl_region *region; 650 struct xarray endpoints; 651 int nr_targets_set; 652 int nr_eps; 653 int nr_targets; 654 }; 655 656 /* 657 * The platform firmware device hosting the root is also the top of the 658 * CXL port topology. All other CXL ports have another CXL port as their 659 * parent and their ->uport / host device is out-of-line of the port 660 * ancestry. 661 */ 662 static inline bool is_cxl_root(struct cxl_port *port) 663 { 664 return port->uport == port->dev.parent; 665 } 666 667 bool is_cxl_port(const struct device *dev); 668 struct cxl_port *to_cxl_port(const struct device *dev); 669 struct pci_bus; 670 int devm_cxl_register_pci_bus(struct device *host, struct device *uport, 671 struct pci_bus *bus); 672 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); 673 struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport, 674 resource_size_t component_reg_phys, 675 struct cxl_dport *parent_dport); 676 struct cxl_port *find_cxl_root(struct cxl_port *port); 677 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); 678 void cxl_bus_rescan(void); 679 void cxl_bus_drain(void); 680 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, 681 struct cxl_dport **dport); 682 bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); 683 684 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, 685 struct device *dport, int port_id, 686 resource_size_t component_reg_phys); 687 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, 688 struct device *dport_dev, int port_id, 689 resource_size_t component_reg_phys, 690 resource_size_t rcrb); 691 692 struct cxl_decoder *to_cxl_decoder(struct device *dev); 693 struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); 694 struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); 695 struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev); 696 bool is_root_decoder(struct device *dev); 697 bool is_switch_decoder(struct device *dev); 698 bool is_endpoint_decoder(struct device *dev); 699 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, 700 unsigned int nr_targets, 701 cxl_calc_hb_fn calc_hb); 702 struct cxl_dport *cxl_hb_modulo(struct cxl_root_decoder *cxlrd, int pos); 703 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, 704 unsigned int nr_targets); 705 int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map); 706 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port); 707 int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map); 708 int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld); 709 int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint); 710 711 /** 712 * struct cxl_endpoint_dvsec_info - Cached DVSEC info 713 * @mem_enabled: cached value of mem_enabled in the DVSEC at init time 714 * @ranges: Number of active HDM ranges this device uses. 715 * @port: endpoint port associated with this info instance 716 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE 717 */ 718 struct cxl_endpoint_dvsec_info { 719 bool mem_enabled; 720 int ranges; 721 struct cxl_port *port; 722 struct range dvsec_range[2]; 723 }; 724 725 struct cxl_hdm; 726 struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port, 727 struct cxl_endpoint_dvsec_info *info); 728 int devm_cxl_enable_hdm(struct cxl_port *port, struct cxl_hdm *cxlhdm); 729 int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, 730 struct cxl_endpoint_dvsec_info *info); 731 int devm_cxl_add_passthrough_decoder(struct cxl_port *port); 732 int cxl_dvsec_rr_decode(struct device *dev, int dvsec, 733 struct cxl_endpoint_dvsec_info *info); 734 735 bool is_cxl_region(struct device *dev); 736 737 extern struct bus_type cxl_bus_type; 738 739 struct cxl_driver { 740 const char *name; 741 int (*probe)(struct device *dev); 742 void (*remove)(struct device *dev); 743 struct device_driver drv; 744 int id; 745 }; 746 747 static inline struct cxl_driver *to_cxl_drv(struct device_driver *drv) 748 { 749 return container_of(drv, struct cxl_driver, drv); 750 } 751 752 int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, 753 const char *modname); 754 #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME) 755 void cxl_driver_unregister(struct cxl_driver *cxl_drv); 756 757 #define module_cxl_driver(__cxl_driver) \ 758 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister) 759 760 #define CXL_DEVICE_NVDIMM_BRIDGE 1 761 #define CXL_DEVICE_NVDIMM 2 762 #define CXL_DEVICE_PORT 3 763 #define CXL_DEVICE_ROOT 4 764 #define CXL_DEVICE_MEMORY_EXPANDER 5 765 #define CXL_DEVICE_REGION 6 766 #define CXL_DEVICE_PMEM_REGION 7 767 #define CXL_DEVICE_DAX_REGION 8 768 #define CXL_DEVICE_PMU 9 769 770 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") 771 #define CXL_MODALIAS_FMT "cxl:t%d" 772 773 struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev); 774 struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, 775 struct cxl_port *port); 776 struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); 777 bool is_cxl_nvdimm(struct device *dev); 778 bool is_cxl_nvdimm_bridge(struct device *dev); 779 int devm_cxl_add_nvdimm(struct cxl_memdev *cxlmd); 780 struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd); 781 782 #ifdef CONFIG_CXL_REGION 783 bool is_cxl_pmem_region(struct device *dev); 784 struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); 785 int cxl_add_to_region(struct cxl_port *root, 786 struct cxl_endpoint_decoder *cxled); 787 struct cxl_dax_region *to_cxl_dax_region(struct device *dev); 788 #else 789 static inline bool is_cxl_pmem_region(struct device *dev) 790 { 791 return false; 792 } 793 static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) 794 { 795 return NULL; 796 } 797 static inline int cxl_add_to_region(struct cxl_port *root, 798 struct cxl_endpoint_decoder *cxled) 799 { 800 return 0; 801 } 802 static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev) 803 { 804 return NULL; 805 } 806 #endif 807 808 /* 809 * Unit test builds overrides this to __weak, find the 'strong' version 810 * of these symbols in tools/testing/cxl/. 811 */ 812 #ifndef __mock 813 #define __mock static 814 #endif 815 816 #endif /* __CXL_H__ */ 817