1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Cryptographic API. 4 * 5 * Support for OMAP AES HW acceleration. 6 * 7 * Copyright (c) 2010 Nokia Corporation 8 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> 9 * Copyright (c) 2011 Texas Instruments Incorporated 10 */ 11 12 #define pr_fmt(fmt) "%20s: " fmt, __func__ 13 #define prn(num) pr_debug(#num "=%d\n", num) 14 #define prx(num) pr_debug(#num "=%x\n", num) 15 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/errno.h> 20 #include <linux/kernel.h> 21 #include <linux/platform_device.h> 22 #include <linux/scatterlist.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/dmaengine.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include <linux/of_address.h> 29 #include <linux/io.h> 30 #include <linux/crypto.h> 31 #include <linux/interrupt.h> 32 #include <crypto/scatterwalk.h> 33 #include <crypto/aes.h> 34 #include <crypto/gcm.h> 35 #include <crypto/engine.h> 36 #include <crypto/internal/skcipher.h> 37 #include <crypto/internal/aead.h> 38 39 #include "omap-crypto.h" 40 #include "omap-aes.h" 41 42 /* keep registered devices data here */ 43 static LIST_HEAD(dev_list); 44 static DEFINE_SPINLOCK(list_lock); 45 46 static int aes_fallback_sz = 200; 47 48 #ifdef DEBUG 49 #define omap_aes_read(dd, offset) \ 50 ({ \ 51 int _read_ret; \ 52 _read_ret = __raw_readl(dd->io_base + offset); \ 53 pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \ 54 offset, _read_ret); \ 55 _read_ret; \ 56 }) 57 #else 58 inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset) 59 { 60 return __raw_readl(dd->io_base + offset); 61 } 62 #endif 63 64 #ifdef DEBUG 65 #define omap_aes_write(dd, offset, value) \ 66 do { \ 67 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \ 68 offset, value); \ 69 __raw_writel(value, dd->io_base + offset); \ 70 } while (0) 71 #else 72 inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset, 73 u32 value) 74 { 75 __raw_writel(value, dd->io_base + offset); 76 } 77 #endif 78 79 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset, 80 u32 value, u32 mask) 81 { 82 u32 val; 83 84 val = omap_aes_read(dd, offset); 85 val &= ~mask; 86 val |= value; 87 omap_aes_write(dd, offset, val); 88 } 89 90 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset, 91 u32 *value, int count) 92 { 93 for (; count--; value++, offset += 4) 94 omap_aes_write(dd, offset, *value); 95 } 96 97 static int omap_aes_hw_init(struct omap_aes_dev *dd) 98 { 99 int err; 100 101 if (!(dd->flags & FLAGS_INIT)) { 102 dd->flags |= FLAGS_INIT; 103 dd->err = 0; 104 } 105 106 err = pm_runtime_resume_and_get(dd->dev); 107 if (err < 0) { 108 dev_err(dd->dev, "failed to get sync: %d\n", err); 109 return err; 110 } 111 112 return 0; 113 } 114 115 void omap_aes_clear_copy_flags(struct omap_aes_dev *dd) 116 { 117 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_IN_DATA_ST_SHIFT); 118 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_OUT_DATA_ST_SHIFT); 119 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_ASSOC_DATA_ST_SHIFT); 120 } 121 122 int omap_aes_write_ctrl(struct omap_aes_dev *dd) 123 { 124 struct omap_aes_reqctx *rctx; 125 unsigned int key32; 126 int i, err; 127 u32 val; 128 129 err = omap_aes_hw_init(dd); 130 if (err) 131 return err; 132 133 key32 = dd->ctx->keylen / sizeof(u32); 134 135 /* RESET the key as previous HASH keys should not get affected*/ 136 if (dd->flags & FLAGS_GCM) 137 for (i = 0; i < 0x40; i = i + 4) 138 omap_aes_write(dd, i, 0x0); 139 140 for (i = 0; i < key32; i++) { 141 omap_aes_write(dd, AES_REG_KEY(dd, i), 142 (__force u32)cpu_to_le32(dd->ctx->key[i])); 143 } 144 145 if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->iv) 146 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (void *)dd->req->iv, 4); 147 148 if ((dd->flags & (FLAGS_GCM)) && dd->aead_req->iv) { 149 rctx = aead_request_ctx(dd->aead_req); 150 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (u32 *)rctx->iv, 4); 151 } 152 153 val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3); 154 if (dd->flags & FLAGS_CBC) 155 val |= AES_REG_CTRL_CBC; 156 157 if (dd->flags & (FLAGS_CTR | FLAGS_GCM)) 158 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128; 159 160 if (dd->flags & FLAGS_GCM) 161 val |= AES_REG_CTRL_GCM; 162 163 if (dd->flags & FLAGS_ENCRYPT) 164 val |= AES_REG_CTRL_DIRECTION; 165 166 omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK); 167 168 return 0; 169 } 170 171 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length) 172 { 173 u32 mask, val; 174 175 val = dd->pdata->dma_start; 176 177 if (dd->dma_lch_out != NULL) 178 val |= dd->pdata->dma_enable_out; 179 if (dd->dma_lch_in != NULL) 180 val |= dd->pdata->dma_enable_in; 181 182 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 183 dd->pdata->dma_start; 184 185 omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask); 186 187 } 188 189 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length) 190 { 191 omap_aes_write(dd, AES_REG_LENGTH_N(0), length); 192 omap_aes_write(dd, AES_REG_LENGTH_N(1), 0); 193 if (dd->flags & FLAGS_GCM) 194 omap_aes_write(dd, AES_REG_A_LEN, dd->assoc_len); 195 196 omap_aes_dma_trigger_omap2(dd, length); 197 } 198 199 static void omap_aes_dma_stop(struct omap_aes_dev *dd) 200 { 201 u32 mask; 202 203 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 204 dd->pdata->dma_start; 205 206 omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask); 207 } 208 209 struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx) 210 { 211 struct omap_aes_dev *dd; 212 213 spin_lock_bh(&list_lock); 214 dd = list_first_entry(&dev_list, struct omap_aes_dev, list); 215 list_move_tail(&dd->list, &dev_list); 216 rctx->dd = dd; 217 spin_unlock_bh(&list_lock); 218 219 return dd; 220 } 221 222 static void omap_aes_dma_out_callback(void *data) 223 { 224 struct omap_aes_dev *dd = data; 225 226 /* dma_lch_out - completed */ 227 tasklet_schedule(&dd->done_task); 228 } 229 230 static int omap_aes_dma_init(struct omap_aes_dev *dd) 231 { 232 int err; 233 234 dd->dma_lch_out = NULL; 235 dd->dma_lch_in = NULL; 236 237 dd->dma_lch_in = dma_request_chan(dd->dev, "rx"); 238 if (IS_ERR(dd->dma_lch_in)) { 239 dev_err(dd->dev, "Unable to request in DMA channel\n"); 240 return PTR_ERR(dd->dma_lch_in); 241 } 242 243 dd->dma_lch_out = dma_request_chan(dd->dev, "tx"); 244 if (IS_ERR(dd->dma_lch_out)) { 245 dev_err(dd->dev, "Unable to request out DMA channel\n"); 246 err = PTR_ERR(dd->dma_lch_out); 247 goto err_dma_out; 248 } 249 250 return 0; 251 252 err_dma_out: 253 dma_release_channel(dd->dma_lch_in); 254 255 return err; 256 } 257 258 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd) 259 { 260 if (dd->pio_only) 261 return; 262 263 dma_release_channel(dd->dma_lch_out); 264 dma_release_channel(dd->dma_lch_in); 265 } 266 267 static int omap_aes_crypt_dma(struct omap_aes_dev *dd, 268 struct scatterlist *in_sg, 269 struct scatterlist *out_sg, 270 int in_sg_len, int out_sg_len) 271 { 272 struct dma_async_tx_descriptor *tx_in, *tx_out = NULL, *cb_desc; 273 struct dma_slave_config cfg; 274 int ret; 275 276 if (dd->pio_only) { 277 scatterwalk_start(&dd->in_walk, dd->in_sg); 278 if (out_sg_len) 279 scatterwalk_start(&dd->out_walk, dd->out_sg); 280 281 /* Enable DATAIN interrupt and let it take 282 care of the rest */ 283 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2); 284 return 0; 285 } 286 287 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE); 288 289 memset(&cfg, 0, sizeof(cfg)); 290 291 cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); 292 cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); 293 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 294 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 295 cfg.src_maxburst = DST_MAXBURST; 296 cfg.dst_maxburst = DST_MAXBURST; 297 298 /* IN */ 299 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg); 300 if (ret) { 301 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n", 302 ret); 303 return ret; 304 } 305 306 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len, 307 DMA_MEM_TO_DEV, 308 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 309 if (!tx_in) { 310 dev_err(dd->dev, "IN prep_slave_sg() failed\n"); 311 return -EINVAL; 312 } 313 314 /* No callback necessary */ 315 tx_in->callback_param = dd; 316 tx_in->callback = NULL; 317 318 /* OUT */ 319 if (out_sg_len) { 320 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg); 321 if (ret) { 322 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n", 323 ret); 324 return ret; 325 } 326 327 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, 328 out_sg_len, 329 DMA_DEV_TO_MEM, 330 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 331 if (!tx_out) { 332 dev_err(dd->dev, "OUT prep_slave_sg() failed\n"); 333 return -EINVAL; 334 } 335 336 cb_desc = tx_out; 337 } else { 338 cb_desc = tx_in; 339 } 340 341 if (dd->flags & FLAGS_GCM) 342 cb_desc->callback = omap_aes_gcm_dma_out_callback; 343 else 344 cb_desc->callback = omap_aes_dma_out_callback; 345 cb_desc->callback_param = dd; 346 347 348 dmaengine_submit(tx_in); 349 if (tx_out) 350 dmaengine_submit(tx_out); 351 352 dma_async_issue_pending(dd->dma_lch_in); 353 if (out_sg_len) 354 dma_async_issue_pending(dd->dma_lch_out); 355 356 /* start DMA */ 357 dd->pdata->trigger(dd, dd->total); 358 359 return 0; 360 } 361 362 int omap_aes_crypt_dma_start(struct omap_aes_dev *dd) 363 { 364 int err; 365 366 pr_debug("total: %zu\n", dd->total); 367 368 if (!dd->pio_only) { 369 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len, 370 DMA_TO_DEVICE); 371 if (!err) { 372 dev_err(dd->dev, "dma_map_sg() error\n"); 373 return -EINVAL; 374 } 375 376 if (dd->out_sg_len) { 377 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len, 378 DMA_FROM_DEVICE); 379 if (!err) { 380 dev_err(dd->dev, "dma_map_sg() error\n"); 381 return -EINVAL; 382 } 383 } 384 } 385 386 err = omap_aes_crypt_dma(dd, dd->in_sg, dd->out_sg, dd->in_sg_len, 387 dd->out_sg_len); 388 if (err && !dd->pio_only) { 389 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 390 if (dd->out_sg_len) 391 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 392 DMA_FROM_DEVICE); 393 } 394 395 return err; 396 } 397 398 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err) 399 { 400 struct skcipher_request *req = dd->req; 401 402 pr_debug("err: %d\n", err); 403 404 crypto_finalize_skcipher_request(dd->engine, req, err); 405 406 pm_runtime_mark_last_busy(dd->dev); 407 pm_runtime_put_autosuspend(dd->dev); 408 } 409 410 int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd) 411 { 412 pr_debug("total: %zu\n", dd->total); 413 414 omap_aes_dma_stop(dd); 415 416 417 return 0; 418 } 419 420 static int omap_aes_handle_queue(struct omap_aes_dev *dd, 421 struct skcipher_request *req) 422 { 423 if (req) 424 return crypto_transfer_skcipher_request_to_engine(dd->engine, req); 425 426 return 0; 427 } 428 429 static int omap_aes_prepare_req(struct skcipher_request *req, 430 struct omap_aes_dev *dd) 431 { 432 struct omap_aes_ctx *ctx = crypto_skcipher_ctx( 433 crypto_skcipher_reqtfm(req)); 434 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req); 435 int ret; 436 u16 flags; 437 438 /* assign new request to device */ 439 dd->req = req; 440 dd->total = req->cryptlen; 441 dd->total_save = req->cryptlen; 442 dd->in_sg = req->src; 443 dd->out_sg = req->dst; 444 dd->orig_out = req->dst; 445 446 flags = OMAP_CRYPTO_COPY_DATA; 447 if (req->src == req->dst) 448 flags |= OMAP_CRYPTO_FORCE_COPY; 449 450 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, AES_BLOCK_SIZE, 451 dd->in_sgl, flags, 452 FLAGS_IN_DATA_ST_SHIFT, &dd->flags); 453 if (ret) 454 return ret; 455 456 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, AES_BLOCK_SIZE, 457 &dd->out_sgl, 0, 458 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags); 459 if (ret) 460 return ret; 461 462 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total); 463 if (dd->in_sg_len < 0) 464 return dd->in_sg_len; 465 466 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total); 467 if (dd->out_sg_len < 0) 468 return dd->out_sg_len; 469 470 rctx->mode &= FLAGS_MODE_MASK; 471 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode; 472 473 dd->ctx = ctx; 474 rctx->dd = dd; 475 476 return omap_aes_write_ctrl(dd); 477 } 478 479 static int omap_aes_crypt_req(struct crypto_engine *engine, 480 void *areq) 481 { 482 struct skcipher_request *req = container_of(areq, struct skcipher_request, base); 483 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req); 484 struct omap_aes_dev *dd = rctx->dd; 485 486 if (!dd) 487 return -ENODEV; 488 489 return omap_aes_prepare_req(req, dd) ?: 490 omap_aes_crypt_dma_start(dd); 491 } 492 493 static void omap_aes_copy_ivout(struct omap_aes_dev *dd, u8 *ivbuf) 494 { 495 int i; 496 497 for (i = 0; i < 4; i++) 498 ((u32 *)ivbuf)[i] = omap_aes_read(dd, AES_REG_IV(dd, i)); 499 } 500 501 static void omap_aes_done_task(unsigned long data) 502 { 503 struct omap_aes_dev *dd = (struct omap_aes_dev *)data; 504 505 pr_debug("enter done_task\n"); 506 507 if (!dd->pio_only) { 508 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len, 509 DMA_FROM_DEVICE); 510 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 511 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 512 DMA_FROM_DEVICE); 513 omap_aes_crypt_dma_stop(dd); 514 } 515 516 omap_crypto_cleanup(dd->in_sg, NULL, 0, dd->total_save, 517 FLAGS_IN_DATA_ST_SHIFT, dd->flags); 518 519 omap_crypto_cleanup(dd->out_sg, dd->orig_out, 0, dd->total_save, 520 FLAGS_OUT_DATA_ST_SHIFT, dd->flags); 521 522 /* Update IV output */ 523 if (dd->flags & (FLAGS_CBC | FLAGS_CTR)) 524 omap_aes_copy_ivout(dd, dd->req->iv); 525 526 omap_aes_finish_req(dd, 0); 527 528 pr_debug("exit\n"); 529 } 530 531 static int omap_aes_crypt(struct skcipher_request *req, unsigned long mode) 532 { 533 struct omap_aes_ctx *ctx = crypto_skcipher_ctx( 534 crypto_skcipher_reqtfm(req)); 535 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req); 536 struct omap_aes_dev *dd; 537 int ret; 538 539 if ((req->cryptlen % AES_BLOCK_SIZE) && !(mode & FLAGS_CTR)) 540 return -EINVAL; 541 542 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen, 543 !!(mode & FLAGS_ENCRYPT), 544 !!(mode & FLAGS_CBC)); 545 546 if (req->cryptlen < aes_fallback_sz) { 547 skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback); 548 skcipher_request_set_callback(&rctx->fallback_req, 549 req->base.flags, 550 req->base.complete, 551 req->base.data); 552 skcipher_request_set_crypt(&rctx->fallback_req, req->src, 553 req->dst, req->cryptlen, req->iv); 554 555 if (mode & FLAGS_ENCRYPT) 556 ret = crypto_skcipher_encrypt(&rctx->fallback_req); 557 else 558 ret = crypto_skcipher_decrypt(&rctx->fallback_req); 559 return ret; 560 } 561 dd = omap_aes_find_dev(rctx); 562 if (!dd) 563 return -ENODEV; 564 565 rctx->mode = mode; 566 567 return omap_aes_handle_queue(dd, req); 568 } 569 570 /* ********************** ALG API ************************************ */ 571 572 static int omap_aes_setkey(struct crypto_skcipher *tfm, const u8 *key, 573 unsigned int keylen) 574 { 575 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 576 int ret; 577 578 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && 579 keylen != AES_KEYSIZE_256) 580 return -EINVAL; 581 582 pr_debug("enter, keylen: %d\n", keylen); 583 584 memcpy(ctx->key, key, keylen); 585 ctx->keylen = keylen; 586 587 crypto_skcipher_clear_flags(ctx->fallback, CRYPTO_TFM_REQ_MASK); 588 crypto_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags & 589 CRYPTO_TFM_REQ_MASK); 590 591 ret = crypto_skcipher_setkey(ctx->fallback, key, keylen); 592 if (!ret) 593 return 0; 594 595 return 0; 596 } 597 598 static int omap_aes_ecb_encrypt(struct skcipher_request *req) 599 { 600 return omap_aes_crypt(req, FLAGS_ENCRYPT); 601 } 602 603 static int omap_aes_ecb_decrypt(struct skcipher_request *req) 604 { 605 return omap_aes_crypt(req, 0); 606 } 607 608 static int omap_aes_cbc_encrypt(struct skcipher_request *req) 609 { 610 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC); 611 } 612 613 static int omap_aes_cbc_decrypt(struct skcipher_request *req) 614 { 615 return omap_aes_crypt(req, FLAGS_CBC); 616 } 617 618 static int omap_aes_ctr_encrypt(struct skcipher_request *req) 619 { 620 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR); 621 } 622 623 static int omap_aes_ctr_decrypt(struct skcipher_request *req) 624 { 625 return omap_aes_crypt(req, FLAGS_CTR); 626 } 627 628 static int omap_aes_init_tfm(struct crypto_skcipher *tfm) 629 { 630 const char *name = crypto_tfm_alg_name(&tfm->base); 631 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 632 struct crypto_skcipher *blk; 633 634 blk = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK); 635 if (IS_ERR(blk)) 636 return PTR_ERR(blk); 637 638 ctx->fallback = blk; 639 640 crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_aes_reqctx) + 641 crypto_skcipher_reqsize(blk)); 642 643 ctx->enginectx.op.do_one_request = omap_aes_crypt_req; 644 645 return 0; 646 } 647 648 static void omap_aes_exit_tfm(struct crypto_skcipher *tfm) 649 { 650 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 651 652 if (ctx->fallback) 653 crypto_free_skcipher(ctx->fallback); 654 655 ctx->fallback = NULL; 656 } 657 658 /* ********************** ALGS ************************************ */ 659 660 static struct skcipher_alg algs_ecb_cbc[] = { 661 { 662 .base.cra_name = "ecb(aes)", 663 .base.cra_driver_name = "ecb-aes-omap", 664 .base.cra_priority = 300, 665 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 666 CRYPTO_ALG_ASYNC | 667 CRYPTO_ALG_NEED_FALLBACK, 668 .base.cra_blocksize = AES_BLOCK_SIZE, 669 .base.cra_ctxsize = sizeof(struct omap_aes_ctx), 670 .base.cra_module = THIS_MODULE, 671 672 .min_keysize = AES_MIN_KEY_SIZE, 673 .max_keysize = AES_MAX_KEY_SIZE, 674 .setkey = omap_aes_setkey, 675 .encrypt = omap_aes_ecb_encrypt, 676 .decrypt = omap_aes_ecb_decrypt, 677 .init = omap_aes_init_tfm, 678 .exit = omap_aes_exit_tfm, 679 }, 680 { 681 .base.cra_name = "cbc(aes)", 682 .base.cra_driver_name = "cbc-aes-omap", 683 .base.cra_priority = 300, 684 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 685 CRYPTO_ALG_ASYNC | 686 CRYPTO_ALG_NEED_FALLBACK, 687 .base.cra_blocksize = AES_BLOCK_SIZE, 688 .base.cra_ctxsize = sizeof(struct omap_aes_ctx), 689 .base.cra_module = THIS_MODULE, 690 691 .min_keysize = AES_MIN_KEY_SIZE, 692 .max_keysize = AES_MAX_KEY_SIZE, 693 .ivsize = AES_BLOCK_SIZE, 694 .setkey = omap_aes_setkey, 695 .encrypt = omap_aes_cbc_encrypt, 696 .decrypt = omap_aes_cbc_decrypt, 697 .init = omap_aes_init_tfm, 698 .exit = omap_aes_exit_tfm, 699 } 700 }; 701 702 static struct skcipher_alg algs_ctr[] = { 703 { 704 .base.cra_name = "ctr(aes)", 705 .base.cra_driver_name = "ctr-aes-omap", 706 .base.cra_priority = 300, 707 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 708 CRYPTO_ALG_ASYNC | 709 CRYPTO_ALG_NEED_FALLBACK, 710 .base.cra_blocksize = 1, 711 .base.cra_ctxsize = sizeof(struct omap_aes_ctx), 712 .base.cra_module = THIS_MODULE, 713 714 .min_keysize = AES_MIN_KEY_SIZE, 715 .max_keysize = AES_MAX_KEY_SIZE, 716 .ivsize = AES_BLOCK_SIZE, 717 .setkey = omap_aes_setkey, 718 .encrypt = omap_aes_ctr_encrypt, 719 .decrypt = omap_aes_ctr_decrypt, 720 .init = omap_aes_init_tfm, 721 .exit = omap_aes_exit_tfm, 722 } 723 }; 724 725 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = { 726 { 727 .algs_list = algs_ecb_cbc, 728 .size = ARRAY_SIZE(algs_ecb_cbc), 729 }, 730 }; 731 732 static struct aead_alg algs_aead_gcm[] = { 733 { 734 .base = { 735 .cra_name = "gcm(aes)", 736 .cra_driver_name = "gcm-aes-omap", 737 .cra_priority = 300, 738 .cra_flags = CRYPTO_ALG_ASYNC | 739 CRYPTO_ALG_KERN_DRIVER_ONLY, 740 .cra_blocksize = 1, 741 .cra_ctxsize = sizeof(struct omap_aes_gcm_ctx), 742 .cra_alignmask = 0xf, 743 .cra_module = THIS_MODULE, 744 }, 745 .init = omap_aes_gcm_cra_init, 746 .ivsize = GCM_AES_IV_SIZE, 747 .maxauthsize = AES_BLOCK_SIZE, 748 .setkey = omap_aes_gcm_setkey, 749 .setauthsize = omap_aes_gcm_setauthsize, 750 .encrypt = omap_aes_gcm_encrypt, 751 .decrypt = omap_aes_gcm_decrypt, 752 }, 753 { 754 .base = { 755 .cra_name = "rfc4106(gcm(aes))", 756 .cra_driver_name = "rfc4106-gcm-aes-omap", 757 .cra_priority = 300, 758 .cra_flags = CRYPTO_ALG_ASYNC | 759 CRYPTO_ALG_KERN_DRIVER_ONLY, 760 .cra_blocksize = 1, 761 .cra_ctxsize = sizeof(struct omap_aes_gcm_ctx), 762 .cra_alignmask = 0xf, 763 .cra_module = THIS_MODULE, 764 }, 765 .init = omap_aes_gcm_cra_init, 766 .maxauthsize = AES_BLOCK_SIZE, 767 .ivsize = GCM_RFC4106_IV_SIZE, 768 .setkey = omap_aes_4106gcm_setkey, 769 .setauthsize = omap_aes_4106gcm_setauthsize, 770 .encrypt = omap_aes_4106gcm_encrypt, 771 .decrypt = omap_aes_4106gcm_decrypt, 772 }, 773 }; 774 775 static struct omap_aes_aead_algs omap_aes_aead_info = { 776 .algs_list = algs_aead_gcm, 777 .size = ARRAY_SIZE(algs_aead_gcm), 778 }; 779 780 static const struct omap_aes_pdata omap_aes_pdata_omap2 = { 781 .algs_info = omap_aes_algs_info_ecb_cbc, 782 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc), 783 .trigger = omap_aes_dma_trigger_omap2, 784 .key_ofs = 0x1c, 785 .iv_ofs = 0x20, 786 .ctrl_ofs = 0x30, 787 .data_ofs = 0x34, 788 .rev_ofs = 0x44, 789 .mask_ofs = 0x48, 790 .dma_enable_in = BIT(2), 791 .dma_enable_out = BIT(3), 792 .dma_start = BIT(5), 793 .major_mask = 0xf0, 794 .major_shift = 4, 795 .minor_mask = 0x0f, 796 .minor_shift = 0, 797 }; 798 799 #ifdef CONFIG_OF 800 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = { 801 { 802 .algs_list = algs_ecb_cbc, 803 .size = ARRAY_SIZE(algs_ecb_cbc), 804 }, 805 { 806 .algs_list = algs_ctr, 807 .size = ARRAY_SIZE(algs_ctr), 808 }, 809 }; 810 811 static const struct omap_aes_pdata omap_aes_pdata_omap3 = { 812 .algs_info = omap_aes_algs_info_ecb_cbc_ctr, 813 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), 814 .trigger = omap_aes_dma_trigger_omap2, 815 .key_ofs = 0x1c, 816 .iv_ofs = 0x20, 817 .ctrl_ofs = 0x30, 818 .data_ofs = 0x34, 819 .rev_ofs = 0x44, 820 .mask_ofs = 0x48, 821 .dma_enable_in = BIT(2), 822 .dma_enable_out = BIT(3), 823 .dma_start = BIT(5), 824 .major_mask = 0xf0, 825 .major_shift = 4, 826 .minor_mask = 0x0f, 827 .minor_shift = 0, 828 }; 829 830 static const struct omap_aes_pdata omap_aes_pdata_omap4 = { 831 .algs_info = omap_aes_algs_info_ecb_cbc_ctr, 832 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), 833 .aead_algs_info = &omap_aes_aead_info, 834 .trigger = omap_aes_dma_trigger_omap4, 835 .key_ofs = 0x3c, 836 .iv_ofs = 0x40, 837 .ctrl_ofs = 0x50, 838 .data_ofs = 0x60, 839 .rev_ofs = 0x80, 840 .mask_ofs = 0x84, 841 .irq_status_ofs = 0x8c, 842 .irq_enable_ofs = 0x90, 843 .dma_enable_in = BIT(5), 844 .dma_enable_out = BIT(6), 845 .major_mask = 0x0700, 846 .major_shift = 8, 847 .minor_mask = 0x003f, 848 .minor_shift = 0, 849 }; 850 851 static irqreturn_t omap_aes_irq(int irq, void *dev_id) 852 { 853 struct omap_aes_dev *dd = dev_id; 854 u32 status, i; 855 u32 *src, *dst; 856 857 status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd)); 858 if (status & AES_REG_IRQ_DATA_IN) { 859 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0); 860 861 BUG_ON(!dd->in_sg); 862 863 BUG_ON(_calc_walked(in) > dd->in_sg->length); 864 865 src = sg_virt(dd->in_sg) + _calc_walked(in); 866 867 for (i = 0; i < AES_BLOCK_WORDS; i++) { 868 omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src); 869 870 scatterwalk_advance(&dd->in_walk, 4); 871 if (dd->in_sg->length == _calc_walked(in)) { 872 dd->in_sg = sg_next(dd->in_sg); 873 if (dd->in_sg) { 874 scatterwalk_start(&dd->in_walk, 875 dd->in_sg); 876 src = sg_virt(dd->in_sg) + 877 _calc_walked(in); 878 } 879 } else { 880 src++; 881 } 882 } 883 884 /* Clear IRQ status */ 885 status &= ~AES_REG_IRQ_DATA_IN; 886 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status); 887 888 /* Enable DATA_OUT interrupt */ 889 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4); 890 891 } else if (status & AES_REG_IRQ_DATA_OUT) { 892 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0); 893 894 BUG_ON(!dd->out_sg); 895 896 BUG_ON(_calc_walked(out) > dd->out_sg->length); 897 898 dst = sg_virt(dd->out_sg) + _calc_walked(out); 899 900 for (i = 0; i < AES_BLOCK_WORDS; i++) { 901 *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i)); 902 scatterwalk_advance(&dd->out_walk, 4); 903 if (dd->out_sg->length == _calc_walked(out)) { 904 dd->out_sg = sg_next(dd->out_sg); 905 if (dd->out_sg) { 906 scatterwalk_start(&dd->out_walk, 907 dd->out_sg); 908 dst = sg_virt(dd->out_sg) + 909 _calc_walked(out); 910 } 911 } else { 912 dst++; 913 } 914 } 915 916 dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total); 917 918 /* Clear IRQ status */ 919 status &= ~AES_REG_IRQ_DATA_OUT; 920 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status); 921 922 if (!dd->total) 923 /* All bytes read! */ 924 tasklet_schedule(&dd->done_task); 925 else 926 /* Enable DATA_IN interrupt for next block */ 927 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2); 928 } 929 930 return IRQ_HANDLED; 931 } 932 933 static const struct of_device_id omap_aes_of_match[] = { 934 { 935 .compatible = "ti,omap2-aes", 936 .data = &omap_aes_pdata_omap2, 937 }, 938 { 939 .compatible = "ti,omap3-aes", 940 .data = &omap_aes_pdata_omap3, 941 }, 942 { 943 .compatible = "ti,omap4-aes", 944 .data = &omap_aes_pdata_omap4, 945 }, 946 {}, 947 }; 948 MODULE_DEVICE_TABLE(of, omap_aes_of_match); 949 950 static int omap_aes_get_res_of(struct omap_aes_dev *dd, 951 struct device *dev, struct resource *res) 952 { 953 struct device_node *node = dev->of_node; 954 int err = 0; 955 956 dd->pdata = of_device_get_match_data(dev); 957 if (!dd->pdata) { 958 dev_err(dev, "no compatible OF match\n"); 959 err = -EINVAL; 960 goto err; 961 } 962 963 err = of_address_to_resource(node, 0, res); 964 if (err < 0) { 965 dev_err(dev, "can't translate OF node address\n"); 966 err = -EINVAL; 967 goto err; 968 } 969 970 err: 971 return err; 972 } 973 #else 974 static const struct of_device_id omap_aes_of_match[] = { 975 {}, 976 }; 977 978 static int omap_aes_get_res_of(struct omap_aes_dev *dd, 979 struct device *dev, struct resource *res) 980 { 981 return -EINVAL; 982 } 983 #endif 984 985 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd, 986 struct platform_device *pdev, struct resource *res) 987 { 988 struct device *dev = &pdev->dev; 989 struct resource *r; 990 int err = 0; 991 992 /* Get the base address */ 993 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 994 if (!r) { 995 dev_err(dev, "no MEM resource info\n"); 996 err = -ENODEV; 997 goto err; 998 } 999 memcpy(res, r, sizeof(*res)); 1000 1001 /* Only OMAP2/3 can be non-DT */ 1002 dd->pdata = &omap_aes_pdata_omap2; 1003 1004 err: 1005 return err; 1006 } 1007 1008 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr, 1009 char *buf) 1010 { 1011 return sprintf(buf, "%d\n", aes_fallback_sz); 1012 } 1013 1014 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr, 1015 const char *buf, size_t size) 1016 { 1017 ssize_t status; 1018 long value; 1019 1020 status = kstrtol(buf, 0, &value); 1021 if (status) 1022 return status; 1023 1024 /* HW accelerator only works with buffers > 9 */ 1025 if (value < 9) { 1026 dev_err(dev, "minimum fallback size 9\n"); 1027 return -EINVAL; 1028 } 1029 1030 aes_fallback_sz = value; 1031 1032 return size; 1033 } 1034 1035 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr, 1036 char *buf) 1037 { 1038 struct omap_aes_dev *dd = dev_get_drvdata(dev); 1039 1040 return sprintf(buf, "%d\n", dd->engine->queue.max_qlen); 1041 } 1042 1043 static ssize_t queue_len_store(struct device *dev, 1044 struct device_attribute *attr, const char *buf, 1045 size_t size) 1046 { 1047 struct omap_aes_dev *dd; 1048 ssize_t status; 1049 long value; 1050 unsigned long flags; 1051 1052 status = kstrtol(buf, 0, &value); 1053 if (status) 1054 return status; 1055 1056 if (value < 1) 1057 return -EINVAL; 1058 1059 /* 1060 * Changing the queue size in fly is safe, if size becomes smaller 1061 * than current size, it will just not accept new entries until 1062 * it has shrank enough. 1063 */ 1064 spin_lock_bh(&list_lock); 1065 list_for_each_entry(dd, &dev_list, list) { 1066 spin_lock_irqsave(&dd->lock, flags); 1067 dd->engine->queue.max_qlen = value; 1068 dd->aead_queue.base.max_qlen = value; 1069 spin_unlock_irqrestore(&dd->lock, flags); 1070 } 1071 spin_unlock_bh(&list_lock); 1072 1073 return size; 1074 } 1075 1076 static DEVICE_ATTR_RW(queue_len); 1077 static DEVICE_ATTR_RW(fallback); 1078 1079 static struct attribute *omap_aes_attrs[] = { 1080 &dev_attr_queue_len.attr, 1081 &dev_attr_fallback.attr, 1082 NULL, 1083 }; 1084 1085 static const struct attribute_group omap_aes_attr_group = { 1086 .attrs = omap_aes_attrs, 1087 }; 1088 1089 static int omap_aes_probe(struct platform_device *pdev) 1090 { 1091 struct device *dev = &pdev->dev; 1092 struct omap_aes_dev *dd; 1093 struct skcipher_alg *algp; 1094 struct aead_alg *aalg; 1095 struct resource res; 1096 int err = -ENOMEM, i, j, irq = -1; 1097 u32 reg; 1098 1099 dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL); 1100 if (dd == NULL) { 1101 dev_err(dev, "unable to alloc data struct.\n"); 1102 goto err_data; 1103 } 1104 dd->dev = dev; 1105 platform_set_drvdata(pdev, dd); 1106 1107 aead_init_queue(&dd->aead_queue, OMAP_AES_QUEUE_LENGTH); 1108 1109 err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) : 1110 omap_aes_get_res_pdev(dd, pdev, &res); 1111 if (err) 1112 goto err_res; 1113 1114 dd->io_base = devm_ioremap_resource(dev, &res); 1115 if (IS_ERR(dd->io_base)) { 1116 err = PTR_ERR(dd->io_base); 1117 goto err_res; 1118 } 1119 dd->phys_base = res.start; 1120 1121 pm_runtime_use_autosuspend(dev); 1122 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY); 1123 1124 pm_runtime_enable(dev); 1125 err = pm_runtime_resume_and_get(dev); 1126 if (err < 0) { 1127 dev_err(dev, "%s: failed to get_sync(%d)\n", 1128 __func__, err); 1129 goto err_pm_disable; 1130 } 1131 1132 omap_aes_dma_stop(dd); 1133 1134 reg = omap_aes_read(dd, AES_REG_REV(dd)); 1135 1136 pm_runtime_put_sync(dev); 1137 1138 dev_info(dev, "OMAP AES hw accel rev: %u.%u\n", 1139 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift, 1140 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift); 1141 1142 tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd); 1143 1144 err = omap_aes_dma_init(dd); 1145 if (err == -EPROBE_DEFER) { 1146 goto err_irq; 1147 } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) { 1148 dd->pio_only = 1; 1149 1150 irq = platform_get_irq(pdev, 0); 1151 if (irq < 0) { 1152 err = irq; 1153 goto err_irq; 1154 } 1155 1156 err = devm_request_irq(dev, irq, omap_aes_irq, 0, 1157 dev_name(dev), dd); 1158 if (err) { 1159 dev_err(dev, "Unable to grab omap-aes IRQ\n"); 1160 goto err_irq; 1161 } 1162 } 1163 1164 spin_lock_init(&dd->lock); 1165 1166 INIT_LIST_HEAD(&dd->list); 1167 spin_lock_bh(&list_lock); 1168 list_add_tail(&dd->list, &dev_list); 1169 spin_unlock_bh(&list_lock); 1170 1171 /* Initialize crypto engine */ 1172 dd->engine = crypto_engine_alloc_init(dev, 1); 1173 if (!dd->engine) { 1174 err = -ENOMEM; 1175 goto err_engine; 1176 } 1177 1178 err = crypto_engine_start(dd->engine); 1179 if (err) 1180 goto err_engine; 1181 1182 for (i = 0; i < dd->pdata->algs_info_size; i++) { 1183 if (!dd->pdata->algs_info[i].registered) { 1184 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 1185 algp = &dd->pdata->algs_info[i].algs_list[j]; 1186 1187 pr_debug("reg alg: %s\n", algp->base.cra_name); 1188 1189 err = crypto_register_skcipher(algp); 1190 if (err) 1191 goto err_algs; 1192 1193 dd->pdata->algs_info[i].registered++; 1194 } 1195 } 1196 } 1197 1198 if (dd->pdata->aead_algs_info && 1199 !dd->pdata->aead_algs_info->registered) { 1200 for (i = 0; i < dd->pdata->aead_algs_info->size; i++) { 1201 aalg = &dd->pdata->aead_algs_info->algs_list[i]; 1202 1203 pr_debug("reg alg: %s\n", aalg->base.cra_name); 1204 1205 err = crypto_register_aead(aalg); 1206 if (err) 1207 goto err_aead_algs; 1208 1209 dd->pdata->aead_algs_info->registered++; 1210 } 1211 } 1212 1213 err = sysfs_create_group(&dev->kobj, &omap_aes_attr_group); 1214 if (err) { 1215 dev_err(dev, "could not create sysfs device attrs\n"); 1216 goto err_aead_algs; 1217 } 1218 1219 return 0; 1220 err_aead_algs: 1221 for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) { 1222 aalg = &dd->pdata->aead_algs_info->algs_list[i]; 1223 crypto_unregister_aead(aalg); 1224 } 1225 err_algs: 1226 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1227 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1228 crypto_unregister_skcipher( 1229 &dd->pdata->algs_info[i].algs_list[j]); 1230 1231 err_engine: 1232 if (dd->engine) 1233 crypto_engine_exit(dd->engine); 1234 1235 omap_aes_dma_cleanup(dd); 1236 err_irq: 1237 tasklet_kill(&dd->done_task); 1238 err_pm_disable: 1239 pm_runtime_disable(dev); 1240 err_res: 1241 dd = NULL; 1242 err_data: 1243 dev_err(dev, "initialization failed.\n"); 1244 return err; 1245 } 1246 1247 static int omap_aes_remove(struct platform_device *pdev) 1248 { 1249 struct omap_aes_dev *dd = platform_get_drvdata(pdev); 1250 struct aead_alg *aalg; 1251 int i, j; 1252 1253 spin_lock_bh(&list_lock); 1254 list_del(&dd->list); 1255 spin_unlock_bh(&list_lock); 1256 1257 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1258 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) { 1259 crypto_unregister_skcipher( 1260 &dd->pdata->algs_info[i].algs_list[j]); 1261 dd->pdata->algs_info[i].registered--; 1262 } 1263 1264 for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) { 1265 aalg = &dd->pdata->aead_algs_info->algs_list[i]; 1266 crypto_unregister_aead(aalg); 1267 dd->pdata->aead_algs_info->registered--; 1268 } 1269 1270 crypto_engine_exit(dd->engine); 1271 1272 tasklet_kill(&dd->done_task); 1273 omap_aes_dma_cleanup(dd); 1274 pm_runtime_disable(dd->dev); 1275 1276 sysfs_remove_group(&dd->dev->kobj, &omap_aes_attr_group); 1277 1278 return 0; 1279 } 1280 1281 #ifdef CONFIG_PM_SLEEP 1282 static int omap_aes_suspend(struct device *dev) 1283 { 1284 pm_runtime_put_sync(dev); 1285 return 0; 1286 } 1287 1288 static int omap_aes_resume(struct device *dev) 1289 { 1290 pm_runtime_get_sync(dev); 1291 return 0; 1292 } 1293 #endif 1294 1295 static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume); 1296 1297 static struct platform_driver omap_aes_driver = { 1298 .probe = omap_aes_probe, 1299 .remove = omap_aes_remove, 1300 .driver = { 1301 .name = "omap-aes", 1302 .pm = &omap_aes_pm_ops, 1303 .of_match_table = omap_aes_of_match, 1304 }, 1305 }; 1306 1307 module_platform_driver(omap_aes_driver); 1308 1309 MODULE_DESCRIPTION("OMAP AES hw acceleration support."); 1310 MODULE_LICENSE("GPL v2"); 1311 MODULE_AUTHOR("Dmitry Kasatkin"); 1312 1313