15e8ce833SSrujana Challa /* SPDX-License-Identifier: GPL-2.0-only 25e8ce833SSrujana Challa * Copyright (C) 2020 Marvell. 35e8ce833SSrujana Challa */ 45e8ce833SSrujana Challa 55e8ce833SSrujana Challa #ifndef __OTX2_CPTPF_H 65e8ce833SSrujana Challa #define __OTX2_CPTPF_H 75e8ce833SSrujana Challa 883ffcf78SSrujana Challa #include "otx2_cpt_common.h" 943ac0b82SSrujana Challa #include "otx2_cptpf_ucode.h" 1064506017SSrujana Challa #include "otx2_cptlf.h" 1183ffcf78SSrujana Challa 12fe16eceaSSrujana Challa struct otx2_cptpf_dev; 13fe16eceaSSrujana Challa struct otx2_cptvf_info { 14fe16eceaSSrujana Challa struct otx2_cptpf_dev *cptpf; /* PF pointer this VF belongs to */ 15fe16eceaSSrujana Challa struct work_struct vfpf_mbox_work; 16fe16eceaSSrujana Challa struct pci_dev *vf_dev; 17fe16eceaSSrujana Challa int vf_id; 18fe16eceaSSrujana Challa int intr_idx; 19fe16eceaSSrujana Challa }; 20fe16eceaSSrujana Challa 21fe16eceaSSrujana Challa struct cptpf_flr_work { 22fe16eceaSSrujana Challa struct work_struct work; 23fe16eceaSSrujana Challa struct otx2_cptpf_dev *pf; 24fe16eceaSSrujana Challa }; 25fe16eceaSSrujana Challa 265e8ce833SSrujana Challa struct otx2_cptpf_dev { 275e8ce833SSrujana Challa void __iomem *reg_base; /* CPT PF registers start address */ 2883ffcf78SSrujana Challa void __iomem *afpf_mbox_base; /* PF-AF mbox start address */ 29fe16eceaSSrujana Challa void __iomem *vfpf_mbox_base; /* VF-PF mbox start address */ 305e8ce833SSrujana Challa struct pci_dev *pdev; /* PCI device handle */ 31fe16eceaSSrujana Challa struct otx2_cptvf_info vf[OTX2_CPT_MAX_VFS_NUM]; 3243ac0b82SSrujana Challa struct otx2_cpt_eng_grps eng_grps;/* Engine groups information */ 3364506017SSrujana Challa struct otx2_cptlfs_info lfs; /* CPT LFs attached to this PF */ 34*a4855a8cSSrujana Challa struct otx2_cptlfs_info cpt1_lfs; /* CPT1 LFs attached to this PF */ 3578506c2aSSrujana Challa /* HW capabilities for each engine type */ 3678506c2aSSrujana Challa union otx2_cpt_eng_caps eng_caps[OTX2_CPT_MAX_ENG_TYPES]; 3778506c2aSSrujana Challa bool is_eng_caps_discovered; 3843ac0b82SSrujana Challa 3983ffcf78SSrujana Challa /* AF <=> PF mbox */ 4083ffcf78SSrujana Challa struct otx2_mbox afpf_mbox; 4183ffcf78SSrujana Challa struct work_struct afpf_mbox_work; 4283ffcf78SSrujana Challa struct workqueue_struct *afpf_mbox_wq; 4383ffcf78SSrujana Challa 445c553114SSrujana Challa struct otx2_mbox afpf_mbox_up; 455c553114SSrujana Challa struct work_struct afpf_mbox_up_work; 465c553114SSrujana Challa 47fe16eceaSSrujana Challa /* VF <=> PF mbox */ 48fe16eceaSSrujana Challa struct otx2_mbox vfpf_mbox; 49fe16eceaSSrujana Challa struct workqueue_struct *vfpf_mbox_wq; 50fe16eceaSSrujana Challa 51fe16eceaSSrujana Challa struct workqueue_struct *flr_wq; 52fe16eceaSSrujana Challa struct cptpf_flr_work *flr_work; 534363f3d3SHarman Kalra struct mutex lock; /* serialize mailbox access */ 54fe16eceaSSrujana Challa 554cd8c315SSrujana Challa unsigned long cap_flag; 5683ffcf78SSrujana Challa u8 pf_id; /* RVU PF number */ 57fe16eceaSSrujana Challa u8 max_vfs; /* Maximum number of VFs supported by CPT */ 58fe16eceaSSrujana Challa u8 enabled_vfs; /* Number of enabled VFs */ 59*a4855a8cSSrujana Challa u8 sso_pf_func_ovrd; /* SSO PF_FUNC override bit */ 608ec8015aSSrujana Challa u8 kvf_limits; /* Kernel crypto limits */ 61b2d17df3SSrujana Challa bool has_cpt1; 62*a4855a8cSSrujana Challa u8 rsrc_req_blkaddr; 63fed8f4d5SSrujana Challa 64fed8f4d5SSrujana Challa /* Devlink */ 65fed8f4d5SSrujana Challa struct devlink *dl; 665e8ce833SSrujana Challa }; 675e8ce833SSrujana Challa 6883ffcf78SSrujana Challa irqreturn_t otx2_cptpf_afpf_mbox_intr(int irq, void *arg); 6983ffcf78SSrujana Challa void otx2_cptpf_afpf_mbox_handler(struct work_struct *work); 705c553114SSrujana Challa void otx2_cptpf_afpf_mbox_up_handler(struct work_struct *work); 71fe16eceaSSrujana Challa irqreturn_t otx2_cptpf_vfpf_mbox_intr(int irq, void *arg); 72fe16eceaSSrujana Challa void otx2_cptpf_vfpf_mbox_handler(struct work_struct *work); 7383ffcf78SSrujana Challa 745e8ce833SSrujana Challa #endif /* __OTX2_CPTPF_H */ 75