1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/bitops.h> 5 #include <linux/debugfs.h> 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/seq_file.h> 13 #include <linux/topology.h> 14 #include <linux/uacce.h> 15 #include "zip.h" 16 17 #define PCI_DEVICE_ID_HUAWEI_ZIP_PF 0xa250 18 19 #define HZIP_QUEUE_NUM_V1 4096 20 21 #define HZIP_CLOCK_GATE_CTRL 0x301004 22 #define HZIP_DECOMP_CHECK_ENABLE BIT(16) 23 #define HZIP_FSM_MAX_CNT 0x301008 24 25 #define HZIP_PORT_ARCA_CHE_0 0x301040 26 #define HZIP_PORT_ARCA_CHE_1 0x301044 27 #define HZIP_PORT_AWCA_CHE_0 0x301060 28 #define HZIP_PORT_AWCA_CHE_1 0x301064 29 #define HZIP_CACHE_ALL_EN 0xffffffff 30 31 #define HZIP_BD_RUSER_32_63 0x301110 32 #define HZIP_SGL_RUSER_32_63 0x30111c 33 #define HZIP_DATA_RUSER_32_63 0x301128 34 #define HZIP_DATA_WUSER_32_63 0x301134 35 #define HZIP_BD_WUSER_32_63 0x301140 36 37 #define HZIP_QM_IDEL_STATUS 0x3040e4 38 39 #define HZIP_CORE_DFX_BASE 0x301000 40 #define HZIP_CLOCK_GATED_CONTL 0X301004 41 #define HZIP_CORE_DFX_COMP_0 0x302000 42 #define HZIP_CORE_DFX_COMP_1 0x303000 43 #define HZIP_CORE_DFX_DECOMP_0 0x304000 44 #define HZIP_CORE_DFX_DECOMP_1 0x305000 45 #define HZIP_CORE_DFX_DECOMP_2 0x306000 46 #define HZIP_CORE_DFX_DECOMP_3 0x307000 47 #define HZIP_CORE_DFX_DECOMP_4 0x308000 48 #define HZIP_CORE_DFX_DECOMP_5 0x309000 49 #define HZIP_CORE_REGS_BASE_LEN 0xB0 50 #define HZIP_CORE_REGS_DFX_LEN 0x28 51 52 #define HZIP_CORE_INT_SOURCE 0x3010A0 53 #define HZIP_CORE_INT_MASK_REG 0x3010A4 54 #define HZIP_CORE_INT_SET 0x3010A8 55 #define HZIP_CORE_INT_STATUS 0x3010AC 56 #define HZIP_CORE_INT_STATUS_M_ECC BIT(1) 57 #define HZIP_CORE_SRAM_ECC_ERR_INFO 0x301148 58 #define HZIP_CORE_INT_RAS_CE_ENB 0x301160 59 #define HZIP_CORE_INT_RAS_NFE_ENB 0x301164 60 #define HZIP_CORE_INT_RAS_FE_ENB 0x301168 61 #define HZIP_CORE_INT_RAS_FE_ENB_MASK 0x0 62 #define HZIP_OOO_SHUTDOWN_SEL 0x30120C 63 #define HZIP_SRAM_ECC_ERR_NUM_SHIFT 16 64 #define HZIP_SRAM_ECC_ERR_ADDR_SHIFT 24 65 #define HZIP_CORE_INT_MASK_ALL GENMASK(12, 0) 66 #define HZIP_SQE_SIZE 128 67 #define HZIP_PF_DEF_Q_NUM 64 68 #define HZIP_PF_DEF_Q_BASE 0 69 70 #define HZIP_SOFT_CTRL_CNT_CLR_CE 0x301000 71 #define HZIP_SOFT_CTRL_CNT_CLR_CE_BIT BIT(0) 72 #define HZIP_SOFT_CTRL_ZIP_CONTROL 0x30100C 73 #define HZIP_AXI_SHUTDOWN_ENABLE BIT(14) 74 #define HZIP_WR_PORT BIT(11) 75 76 #define HZIP_DEV_ALG_MAX_LEN 256 77 #define HZIP_ALG_ZLIB_BIT GENMASK(1, 0) 78 #define HZIP_ALG_GZIP_BIT GENMASK(3, 2) 79 #define HZIP_ALG_DEFLATE_BIT GENMASK(5, 4) 80 #define HZIP_ALG_LZ77_BIT GENMASK(7, 6) 81 82 #define HZIP_BUF_SIZE 22 83 #define HZIP_SQE_MASK_OFFSET 64 84 #define HZIP_SQE_MASK_LEN 48 85 86 #define HZIP_CNT_CLR_CE_EN BIT(0) 87 #define HZIP_RO_CNT_CLR_CE_EN BIT(2) 88 #define HZIP_RD_CNT_CLR_CE_EN (HZIP_CNT_CLR_CE_EN | \ 89 HZIP_RO_CNT_CLR_CE_EN) 90 91 #define HZIP_PREFETCH_CFG 0x3011B0 92 #define HZIP_SVA_TRANS 0x3011C4 93 #define HZIP_PREFETCH_ENABLE (~(BIT(26) | BIT(17) | BIT(0))) 94 #define HZIP_SVA_PREFETCH_DISABLE BIT(26) 95 #define HZIP_SVA_DISABLE_READY (BIT(26) | BIT(30)) 96 #define HZIP_SHAPER_RATE_COMPRESS 750 97 #define HZIP_SHAPER_RATE_DECOMPRESS 140 98 #define HZIP_DELAY_1_US 1 99 #define HZIP_POLL_TIMEOUT_US 1000 100 101 /* clock gating */ 102 #define HZIP_PEH_CFG_AUTO_GATE 0x3011A8 103 #define HZIP_PEH_CFG_AUTO_GATE_EN BIT(0) 104 #define HZIP_CORE_GATED_EN GENMASK(15, 8) 105 #define HZIP_CORE_GATED_OOO_EN BIT(29) 106 #define HZIP_CLOCK_GATED_EN (HZIP_CORE_GATED_EN | \ 107 HZIP_CORE_GATED_OOO_EN) 108 109 /* zip comp high performance */ 110 #define HZIP_HIGH_PERF_OFFSET 0x301208 111 112 enum { 113 HZIP_HIGH_COMP_RATE, 114 HZIP_HIGH_COMP_PERF, 115 }; 116 117 static const char hisi_zip_name[] = "hisi_zip"; 118 static struct dentry *hzip_debugfs_root; 119 120 struct hisi_zip_hw_error { 121 u32 int_msk; 122 const char *msg; 123 }; 124 125 struct zip_dfx_item { 126 const char *name; 127 u32 offset; 128 }; 129 130 struct zip_dev_alg { 131 u32 alg_msk; 132 const char *algs; 133 }; 134 135 static const struct zip_dev_alg zip_dev_algs[] = { { 136 .alg_msk = HZIP_ALG_ZLIB_BIT, 137 .algs = "zlib\n", 138 }, { 139 .alg_msk = HZIP_ALG_GZIP_BIT, 140 .algs = "gzip\n", 141 }, { 142 .alg_msk = HZIP_ALG_DEFLATE_BIT, 143 .algs = "deflate\n", 144 }, { 145 .alg_msk = HZIP_ALG_LZ77_BIT, 146 .algs = "lz77_zstd\n", 147 }, 148 }; 149 150 static struct hisi_qm_list zip_devices = { 151 .register_to_crypto = hisi_zip_register_to_crypto, 152 .unregister_from_crypto = hisi_zip_unregister_from_crypto, 153 }; 154 155 static struct zip_dfx_item zip_dfx_files[] = { 156 {"send_cnt", offsetof(struct hisi_zip_dfx, send_cnt)}, 157 {"recv_cnt", offsetof(struct hisi_zip_dfx, recv_cnt)}, 158 {"send_busy_cnt", offsetof(struct hisi_zip_dfx, send_busy_cnt)}, 159 {"err_bd_cnt", offsetof(struct hisi_zip_dfx, err_bd_cnt)}, 160 }; 161 162 static const struct hisi_zip_hw_error zip_hw_error[] = { 163 { .int_msk = BIT(0), .msg = "zip_ecc_1bitt_err" }, 164 { .int_msk = BIT(1), .msg = "zip_ecc_2bit_err" }, 165 { .int_msk = BIT(2), .msg = "zip_axi_rresp_err" }, 166 { .int_msk = BIT(3), .msg = "zip_axi_bresp_err" }, 167 { .int_msk = BIT(4), .msg = "zip_src_addr_parse_err" }, 168 { .int_msk = BIT(5), .msg = "zip_dst_addr_parse_err" }, 169 { .int_msk = BIT(6), .msg = "zip_pre_in_addr_err" }, 170 { .int_msk = BIT(7), .msg = "zip_pre_in_data_err" }, 171 { .int_msk = BIT(8), .msg = "zip_com_inf_err" }, 172 { .int_msk = BIT(9), .msg = "zip_enc_inf_err" }, 173 { .int_msk = BIT(10), .msg = "zip_pre_out_err" }, 174 { .int_msk = BIT(11), .msg = "zip_axi_poison_err" }, 175 { .int_msk = BIT(12), .msg = "zip_sva_err" }, 176 { /* sentinel */ } 177 }; 178 179 enum ctrl_debug_file_index { 180 HZIP_CLEAR_ENABLE, 181 HZIP_DEBUG_FILE_NUM, 182 }; 183 184 static const char * const ctrl_debug_file_name[] = { 185 [HZIP_CLEAR_ENABLE] = "clear_enable", 186 }; 187 188 struct ctrl_debug_file { 189 enum ctrl_debug_file_index index; 190 spinlock_t lock; 191 struct hisi_zip_ctrl *ctrl; 192 }; 193 194 /* 195 * One ZIP controller has one PF and multiple VFs, some global configurations 196 * which PF has need this structure. 197 * 198 * Just relevant for PF. 199 */ 200 struct hisi_zip_ctrl { 201 struct hisi_zip *hisi_zip; 202 struct ctrl_debug_file files[HZIP_DEBUG_FILE_NUM]; 203 }; 204 205 enum zip_cap_type { 206 ZIP_QM_NFE_MASK_CAP = 0x0, 207 ZIP_QM_RESET_MASK_CAP, 208 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, 209 ZIP_QM_CE_MASK_CAP, 210 ZIP_NFE_MASK_CAP, 211 ZIP_RESET_MASK_CAP, 212 ZIP_OOO_SHUTDOWN_MASK_CAP, 213 ZIP_CE_MASK_CAP, 214 ZIP_CLUSTER_NUM_CAP, 215 ZIP_CORE_TYPE_NUM_CAP, 216 ZIP_CORE_NUM_CAP, 217 ZIP_CLUSTER_COMP_NUM_CAP, 218 ZIP_CLUSTER_DECOMP_NUM_CAP, 219 ZIP_DECOMP_ENABLE_BITMAP, 220 ZIP_COMP_ENABLE_BITMAP, 221 ZIP_DRV_ALG_BITMAP, 222 ZIP_DEV_ALG_BITMAP, 223 ZIP_CORE1_ALG_BITMAP, 224 ZIP_CORE2_ALG_BITMAP, 225 ZIP_CORE3_ALG_BITMAP, 226 ZIP_CORE4_ALG_BITMAP, 227 ZIP_CORE5_ALG_BITMAP, 228 ZIP_CAP_MAX 229 }; 230 231 static struct hisi_qm_cap_info zip_basic_cap_info[] = { 232 {ZIP_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C57, 0x7C77}, 233 {ZIP_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC57, 0x6C77}, 234 {ZIP_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C77}, 235 {ZIP_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8}, 236 {ZIP_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x1FFE}, 237 {ZIP_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x7FE}, 238 {ZIP_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x2, 0x7FE}, 239 {ZIP_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1}, 240 {ZIP_CLUSTER_NUM_CAP, 0x313C, 28, GENMASK(3, 0), 0x1, 0x1, 0x1}, 241 {ZIP_CORE_TYPE_NUM_CAP, 0x313C, 24, GENMASK(3, 0), 0x2, 0x2, 0x2}, 242 {ZIP_CORE_NUM_CAP, 0x313C, 16, GENMASK(7, 0), 0x8, 0x8, 0x5}, 243 {ZIP_CLUSTER_COMP_NUM_CAP, 0x313C, 8, GENMASK(7, 0), 0x2, 0x2, 0x2}, 244 {ZIP_CLUSTER_DECOMP_NUM_CAP, 0x313C, 0, GENMASK(7, 0), 0x6, 0x6, 0x3}, 245 {ZIP_DECOMP_ENABLE_BITMAP, 0x3140, 16, GENMASK(15, 0), 0xFC, 0xFC, 0x1C}, 246 {ZIP_COMP_ENABLE_BITMAP, 0x3140, 0, GENMASK(15, 0), 0x3, 0x3, 0x3}, 247 {ZIP_DRV_ALG_BITMAP, 0x3144, 0, GENMASK(31, 0), 0xF, 0xF, 0xF}, 248 {ZIP_DEV_ALG_BITMAP, 0x3148, 0, GENMASK(31, 0), 0xF, 0xF, 0xFF}, 249 {ZIP_CORE1_ALG_BITMAP, 0x314C, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5}, 250 {ZIP_CORE2_ALG_BITMAP, 0x3150, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5}, 251 {ZIP_CORE3_ALG_BITMAP, 0x3154, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 252 {ZIP_CORE4_ALG_BITMAP, 0x3158, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 253 {ZIP_CORE5_ALG_BITMAP, 0x315C, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 254 {ZIP_CAP_MAX, 0x317c, 0, GENMASK(0, 0), 0x0, 0x0, 0x0} 255 }; 256 257 enum { 258 HZIP_COMP_CORE0, 259 HZIP_COMP_CORE1, 260 HZIP_DECOMP_CORE0, 261 HZIP_DECOMP_CORE1, 262 HZIP_DECOMP_CORE2, 263 HZIP_DECOMP_CORE3, 264 HZIP_DECOMP_CORE4, 265 HZIP_DECOMP_CORE5, 266 }; 267 268 static const u64 core_offsets[] = { 269 [HZIP_COMP_CORE0] = 0x302000, 270 [HZIP_COMP_CORE1] = 0x303000, 271 [HZIP_DECOMP_CORE0] = 0x304000, 272 [HZIP_DECOMP_CORE1] = 0x305000, 273 [HZIP_DECOMP_CORE2] = 0x306000, 274 [HZIP_DECOMP_CORE3] = 0x307000, 275 [HZIP_DECOMP_CORE4] = 0x308000, 276 [HZIP_DECOMP_CORE5] = 0x309000, 277 }; 278 279 static const struct debugfs_reg32 hzip_dfx_regs[] = { 280 {"HZIP_GET_BD_NUM ", 0x00ull}, 281 {"HZIP_GET_RIGHT_BD ", 0x04ull}, 282 {"HZIP_GET_ERROR_BD ", 0x08ull}, 283 {"HZIP_DONE_BD_NUM ", 0x0cull}, 284 {"HZIP_WORK_CYCLE ", 0x10ull}, 285 {"HZIP_IDLE_CYCLE ", 0x18ull}, 286 {"HZIP_MAX_DELAY ", 0x20ull}, 287 {"HZIP_MIN_DELAY ", 0x24ull}, 288 {"HZIP_AVG_DELAY ", 0x28ull}, 289 {"HZIP_MEM_VISIBLE_DATA ", 0x30ull}, 290 {"HZIP_MEM_VISIBLE_ADDR ", 0x34ull}, 291 {"HZIP_CONSUMED_BYTE ", 0x38ull}, 292 {"HZIP_PRODUCED_BYTE ", 0x40ull}, 293 {"HZIP_COMP_INF ", 0x70ull}, 294 {"HZIP_PRE_OUT ", 0x78ull}, 295 {"HZIP_BD_RD ", 0x7cull}, 296 {"HZIP_BD_WR ", 0x80ull}, 297 {"HZIP_GET_BD_AXI_ERR_NUM ", 0x84ull}, 298 {"HZIP_GET_BD_PARSE_ERR_NUM ", 0x88ull}, 299 {"HZIP_ADD_BD_AXI_ERR_NUM ", 0x8cull}, 300 {"HZIP_DECOMP_STF_RELOAD_CURR_ST ", 0x94ull}, 301 {"HZIP_DECOMP_LZ77_CURR_ST ", 0x9cull}, 302 }; 303 304 static const struct debugfs_reg32 hzip_com_dfx_regs[] = { 305 {"HZIP_CLOCK_GATE_CTRL ", 0x301004}, 306 {"HZIP_CORE_INT_RAS_CE_ENB ", 0x301160}, 307 {"HZIP_CORE_INT_RAS_NFE_ENB ", 0x301164}, 308 {"HZIP_CORE_INT_RAS_FE_ENB ", 0x301168}, 309 {"HZIP_UNCOM_ERR_RAS_CTRL ", 0x30116C}, 310 }; 311 312 static const struct debugfs_reg32 hzip_dump_dfx_regs[] = { 313 {"HZIP_GET_BD_NUM ", 0x00ull}, 314 {"HZIP_GET_RIGHT_BD ", 0x04ull}, 315 {"HZIP_GET_ERROR_BD ", 0x08ull}, 316 {"HZIP_DONE_BD_NUM ", 0x0cull}, 317 {"HZIP_MAX_DELAY ", 0x20ull}, 318 }; 319 320 /* define the ZIP's dfx regs region and region length */ 321 static struct dfx_diff_registers hzip_diff_regs[] = { 322 { 323 .reg_offset = HZIP_CORE_DFX_BASE, 324 .reg_len = HZIP_CORE_REGS_BASE_LEN, 325 }, { 326 .reg_offset = HZIP_CORE_DFX_COMP_0, 327 .reg_len = HZIP_CORE_REGS_DFX_LEN, 328 }, { 329 .reg_offset = HZIP_CORE_DFX_COMP_1, 330 .reg_len = HZIP_CORE_REGS_DFX_LEN, 331 }, { 332 .reg_offset = HZIP_CORE_DFX_DECOMP_0, 333 .reg_len = HZIP_CORE_REGS_DFX_LEN, 334 }, { 335 .reg_offset = HZIP_CORE_DFX_DECOMP_1, 336 .reg_len = HZIP_CORE_REGS_DFX_LEN, 337 }, { 338 .reg_offset = HZIP_CORE_DFX_DECOMP_2, 339 .reg_len = HZIP_CORE_REGS_DFX_LEN, 340 }, { 341 .reg_offset = HZIP_CORE_DFX_DECOMP_3, 342 .reg_len = HZIP_CORE_REGS_DFX_LEN, 343 }, { 344 .reg_offset = HZIP_CORE_DFX_DECOMP_4, 345 .reg_len = HZIP_CORE_REGS_DFX_LEN, 346 }, { 347 .reg_offset = HZIP_CORE_DFX_DECOMP_5, 348 .reg_len = HZIP_CORE_REGS_DFX_LEN, 349 }, 350 }; 351 352 static int hzip_diff_regs_show(struct seq_file *s, void *unused) 353 { 354 struct hisi_qm *qm = s->private; 355 356 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, 357 ARRAY_SIZE(hzip_diff_regs)); 358 359 return 0; 360 } 361 DEFINE_SHOW_ATTRIBUTE(hzip_diff_regs); 362 363 static int perf_mode_set(const char *val, const struct kernel_param *kp) 364 { 365 int ret; 366 u32 n; 367 368 if (!val) 369 return -EINVAL; 370 371 ret = kstrtou32(val, 10, &n); 372 if (ret != 0 || (n != HZIP_HIGH_COMP_PERF && 373 n != HZIP_HIGH_COMP_RATE)) 374 return -EINVAL; 375 376 return param_set_int(val, kp); 377 } 378 379 static const struct kernel_param_ops zip_com_perf_ops = { 380 .set = perf_mode_set, 381 .get = param_get_int, 382 }; 383 384 /* 385 * perf_mode = 0 means enable high compression rate mode, 386 * perf_mode = 1 means enable high compression performance mode. 387 * These two modes only apply to the compression direction. 388 */ 389 static u32 perf_mode = HZIP_HIGH_COMP_RATE; 390 module_param_cb(perf_mode, &zip_com_perf_ops, &perf_mode, 0444); 391 MODULE_PARM_DESC(perf_mode, "ZIP high perf mode 0(default), 1(enable)"); 392 393 static const struct kernel_param_ops zip_uacce_mode_ops = { 394 .set = uacce_mode_set, 395 .get = param_get_int, 396 }; 397 398 /* 399 * uacce_mode = 0 means zip only register to crypto, 400 * uacce_mode = 1 means zip both register to crypto and uacce. 401 */ 402 static u32 uacce_mode = UACCE_MODE_NOUACCE; 403 module_param_cb(uacce_mode, &zip_uacce_mode_ops, &uacce_mode, 0444); 404 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 405 406 static bool pf_q_num_flag; 407 static int pf_q_num_set(const char *val, const struct kernel_param *kp) 408 { 409 pf_q_num_flag = true; 410 411 return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_ZIP_PF); 412 } 413 414 static const struct kernel_param_ops pf_q_num_ops = { 415 .set = pf_q_num_set, 416 .get = param_get_int, 417 }; 418 419 static u32 pf_q_num = HZIP_PF_DEF_Q_NUM; 420 module_param_cb(pf_q_num, &pf_q_num_ops, &pf_q_num, 0444); 421 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)"); 422 423 static const struct kernel_param_ops vfs_num_ops = { 424 .set = vfs_num_set, 425 .get = param_get_int, 426 }; 427 428 static u32 vfs_num; 429 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 430 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 431 432 static const struct pci_device_id hisi_zip_dev_ids[] = { 433 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_ZIP_PF) }, 434 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_ZIP_VF) }, 435 { 0, } 436 }; 437 MODULE_DEVICE_TABLE(pci, hisi_zip_dev_ids); 438 439 int zip_create_qps(struct hisi_qp **qps, int qp_num, int node) 440 { 441 if (node == NUMA_NO_NODE) 442 node = cpu_to_node(smp_processor_id()); 443 444 return hisi_qm_alloc_qps_node(&zip_devices, qp_num, 0, node, qps); 445 } 446 447 bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg) 448 { 449 u32 cap_val; 450 451 cap_val = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DRV_ALG_BITMAP, qm->cap_ver); 452 if ((alg & cap_val) == alg) 453 return true; 454 455 return false; 456 } 457 458 static int hisi_zip_set_high_perf(struct hisi_qm *qm) 459 { 460 u32 val; 461 int ret; 462 463 val = readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET); 464 if (perf_mode == HZIP_HIGH_COMP_PERF) 465 val |= HZIP_HIGH_COMP_PERF; 466 else 467 val &= ~HZIP_HIGH_COMP_PERF; 468 469 /* Set perf mode */ 470 writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET); 471 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_HIGH_PERF_OFFSET, 472 val, val == perf_mode, HZIP_DELAY_1_US, 473 HZIP_POLL_TIMEOUT_US); 474 if (ret) 475 pci_err(qm->pdev, "failed to set perf mode\n"); 476 477 return ret; 478 } 479 480 static int hisi_zip_set_qm_algs(struct hisi_qm *qm) 481 { 482 struct device *dev = &qm->pdev->dev; 483 char *algs, *ptr; 484 u32 alg_mask; 485 int i; 486 487 if (!qm->use_sva) 488 return 0; 489 490 algs = devm_kzalloc(dev, HZIP_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL); 491 if (!algs) 492 return -ENOMEM; 493 494 alg_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DEV_ALG_BITMAP, qm->cap_ver); 495 496 for (i = 0; i < ARRAY_SIZE(zip_dev_algs); i++) 497 if (alg_mask & zip_dev_algs[i].alg_msk) 498 strcat(algs, zip_dev_algs[i].algs); 499 500 ptr = strrchr(algs, '\n'); 501 if (ptr) 502 *ptr = '\0'; 503 504 qm->uacce->algs = algs; 505 506 return 0; 507 } 508 509 static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) 510 { 511 u32 val; 512 int ret; 513 514 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 515 return; 516 517 /* Enable prefetch */ 518 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); 519 val &= HZIP_PREFETCH_ENABLE; 520 writel(val, qm->io_base + HZIP_PREFETCH_CFG); 521 522 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG, 523 val, !(val & HZIP_SVA_PREFETCH_DISABLE), 524 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); 525 if (ret) 526 pci_err(qm->pdev, "failed to open sva prefetch\n"); 527 } 528 529 static void hisi_zip_close_sva_prefetch(struct hisi_qm *qm) 530 { 531 u32 val; 532 int ret; 533 534 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 535 return; 536 537 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); 538 val |= HZIP_SVA_PREFETCH_DISABLE; 539 writel(val, qm->io_base + HZIP_PREFETCH_CFG); 540 541 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS, 542 val, !(val & HZIP_SVA_DISABLE_READY), 543 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); 544 if (ret) 545 pci_err(qm->pdev, "failed to close sva prefetch\n"); 546 } 547 548 static void hisi_zip_enable_clock_gate(struct hisi_qm *qm) 549 { 550 u32 val; 551 552 if (qm->ver < QM_HW_V3) 553 return; 554 555 val = readl(qm->io_base + HZIP_CLOCK_GATE_CTRL); 556 val |= HZIP_CLOCK_GATED_EN; 557 writel(val, qm->io_base + HZIP_CLOCK_GATE_CTRL); 558 559 val = readl(qm->io_base + HZIP_PEH_CFG_AUTO_GATE); 560 val |= HZIP_PEH_CFG_AUTO_GATE_EN; 561 writel(val, qm->io_base + HZIP_PEH_CFG_AUTO_GATE); 562 } 563 564 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm) 565 { 566 void __iomem *base = qm->io_base; 567 u32 dcomp_bm, comp_bm; 568 569 /* qm user domain */ 570 writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1); 571 writel(ARUSER_M_CFG_ENABLE, base + QM_ARUSER_M_CFG_ENABLE); 572 writel(AXUSER_BASE, base + QM_AWUSER_M_CFG_1); 573 writel(AWUSER_M_CFG_ENABLE, base + QM_AWUSER_M_CFG_ENABLE); 574 writel(WUSER_M_CFG_ENABLE, base + QM_WUSER_M_CFG_ENABLE); 575 576 /* qm cache */ 577 writel(AXI_M_CFG, base + QM_AXI_M_CFG); 578 writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE); 579 580 /* disable FLR triggered by BME(bus master enable) */ 581 writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG); 582 writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE); 583 584 /* cache */ 585 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_0); 586 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_1); 587 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_0); 588 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_1); 589 590 /* user domain configurations */ 591 writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63); 592 writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63); 593 594 if (qm->use_sva && qm->ver == QM_HW_V2) { 595 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63); 596 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63); 597 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_SGL_RUSER_32_63); 598 } else { 599 writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63); 600 writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63); 601 writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63); 602 } 603 604 /* let's open all compression/decompression cores */ 605 dcomp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 606 ZIP_DECOMP_ENABLE_BITMAP, qm->cap_ver); 607 comp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 608 ZIP_COMP_ENABLE_BITMAP, qm->cap_ver); 609 writel(HZIP_DECOMP_CHECK_ENABLE | dcomp_bm | comp_bm, base + HZIP_CLOCK_GATE_CTRL); 610 611 /* enable sqc,cqc writeback */ 612 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE | 613 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) | 614 FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL); 615 616 hisi_zip_enable_clock_gate(qm); 617 618 return 0; 619 } 620 621 static void hisi_zip_master_ooo_ctrl(struct hisi_qm *qm, bool enable) 622 { 623 u32 val1, val2; 624 625 val1 = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 626 if (enable) { 627 val1 |= HZIP_AXI_SHUTDOWN_ENABLE; 628 val2 = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 629 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 630 } else { 631 val1 &= ~HZIP_AXI_SHUTDOWN_ENABLE; 632 val2 = 0x0; 633 } 634 635 if (qm->ver > QM_HW_V2) 636 writel(val2, qm->io_base + HZIP_OOO_SHUTDOWN_SEL); 637 638 writel(val1, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 639 } 640 641 static void hisi_zip_hw_error_enable(struct hisi_qm *qm) 642 { 643 u32 nfe, ce; 644 645 if (qm->ver == QM_HW_V1) { 646 writel(HZIP_CORE_INT_MASK_ALL, 647 qm->io_base + HZIP_CORE_INT_MASK_REG); 648 dev_info(&qm->pdev->dev, "Does not support hw error handle\n"); 649 return; 650 } 651 652 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 653 ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); 654 655 /* clear ZIP hw error source if having */ 656 writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_SOURCE); 657 658 /* configure error type */ 659 writel(ce, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); 660 writel(HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB); 661 writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 662 663 hisi_zip_master_ooo_ctrl(qm, true); 664 665 /* enable ZIP hw error interrupts */ 666 writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG); 667 } 668 669 static void hisi_zip_hw_error_disable(struct hisi_qm *qm) 670 { 671 u32 nfe, ce; 672 673 /* disable ZIP hw error interrupts */ 674 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 675 ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); 676 writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_MASK_REG); 677 678 hisi_zip_master_ooo_ctrl(qm, false); 679 } 680 681 static inline struct hisi_qm *file_to_qm(struct ctrl_debug_file *file) 682 { 683 struct hisi_zip *hisi_zip = file->ctrl->hisi_zip; 684 685 return &hisi_zip->qm; 686 } 687 688 static u32 clear_enable_read(struct hisi_qm *qm) 689 { 690 return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 691 HZIP_SOFT_CTRL_CNT_CLR_CE_BIT; 692 } 693 694 static int clear_enable_write(struct hisi_qm *qm, u32 val) 695 { 696 u32 tmp; 697 698 if (val != 1 && val != 0) 699 return -EINVAL; 700 701 tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 702 ~HZIP_SOFT_CTRL_CNT_CLR_CE_BIT) | val; 703 writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 704 705 return 0; 706 } 707 708 static ssize_t hisi_zip_ctrl_debug_read(struct file *filp, char __user *buf, 709 size_t count, loff_t *pos) 710 { 711 struct ctrl_debug_file *file = filp->private_data; 712 struct hisi_qm *qm = file_to_qm(file); 713 char tbuf[HZIP_BUF_SIZE]; 714 u32 val; 715 int ret; 716 717 ret = hisi_qm_get_dfx_access(qm); 718 if (ret) 719 return ret; 720 721 spin_lock_irq(&file->lock); 722 switch (file->index) { 723 case HZIP_CLEAR_ENABLE: 724 val = clear_enable_read(qm); 725 break; 726 default: 727 goto err_input; 728 } 729 spin_unlock_irq(&file->lock); 730 731 hisi_qm_put_dfx_access(qm); 732 ret = scnprintf(tbuf, sizeof(tbuf), "%u\n", val); 733 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 734 735 err_input: 736 spin_unlock_irq(&file->lock); 737 hisi_qm_put_dfx_access(qm); 738 return -EINVAL; 739 } 740 741 static ssize_t hisi_zip_ctrl_debug_write(struct file *filp, 742 const char __user *buf, 743 size_t count, loff_t *pos) 744 { 745 struct ctrl_debug_file *file = filp->private_data; 746 struct hisi_qm *qm = file_to_qm(file); 747 char tbuf[HZIP_BUF_SIZE]; 748 unsigned long val; 749 int len, ret; 750 751 if (*pos != 0) 752 return 0; 753 754 if (count >= HZIP_BUF_SIZE) 755 return -ENOSPC; 756 757 len = simple_write_to_buffer(tbuf, HZIP_BUF_SIZE - 1, pos, buf, count); 758 if (len < 0) 759 return len; 760 761 tbuf[len] = '\0'; 762 ret = kstrtoul(tbuf, 0, &val); 763 if (ret) 764 return ret; 765 766 ret = hisi_qm_get_dfx_access(qm); 767 if (ret) 768 return ret; 769 770 spin_lock_irq(&file->lock); 771 switch (file->index) { 772 case HZIP_CLEAR_ENABLE: 773 ret = clear_enable_write(qm, val); 774 if (ret) 775 goto err_input; 776 break; 777 default: 778 ret = -EINVAL; 779 goto err_input; 780 } 781 782 ret = count; 783 784 err_input: 785 spin_unlock_irq(&file->lock); 786 hisi_qm_put_dfx_access(qm); 787 return ret; 788 } 789 790 static const struct file_operations ctrl_debug_fops = { 791 .owner = THIS_MODULE, 792 .open = simple_open, 793 .read = hisi_zip_ctrl_debug_read, 794 .write = hisi_zip_ctrl_debug_write, 795 }; 796 797 static int zip_debugfs_atomic64_set(void *data, u64 val) 798 { 799 if (val) 800 return -EINVAL; 801 802 atomic64_set((atomic64_t *)data, 0); 803 804 return 0; 805 } 806 807 static int zip_debugfs_atomic64_get(void *data, u64 *val) 808 { 809 *val = atomic64_read((atomic64_t *)data); 810 811 return 0; 812 } 813 814 DEFINE_DEBUGFS_ATTRIBUTE(zip_atomic64_ops, zip_debugfs_atomic64_get, 815 zip_debugfs_atomic64_set, "%llu\n"); 816 817 static int hisi_zip_regs_show(struct seq_file *s, void *unused) 818 { 819 hisi_qm_regs_dump(s, s->private); 820 821 return 0; 822 } 823 824 DEFINE_SHOW_ATTRIBUTE(hisi_zip_regs); 825 826 static int hisi_zip_core_debug_init(struct hisi_qm *qm) 827 { 828 u32 zip_core_num, zip_comp_core_num; 829 struct device *dev = &qm->pdev->dev; 830 struct debugfs_regset32 *regset; 831 struct dentry *tmp_d; 832 char buf[HZIP_BUF_SIZE]; 833 int i; 834 835 zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); 836 zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP, 837 qm->cap_ver); 838 839 for (i = 0; i < zip_core_num; i++) { 840 if (i < zip_comp_core_num) 841 scnprintf(buf, sizeof(buf), "comp_core%d", i); 842 else 843 scnprintf(buf, sizeof(buf), "decomp_core%d", 844 i - zip_comp_core_num); 845 846 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 847 if (!regset) 848 return -ENOENT; 849 850 regset->regs = hzip_dfx_regs; 851 regset->nregs = ARRAY_SIZE(hzip_dfx_regs); 852 regset->base = qm->io_base + core_offsets[i]; 853 regset->dev = dev; 854 855 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); 856 debugfs_create_file("regs", 0444, tmp_d, regset, 857 &hisi_zip_regs_fops); 858 } 859 860 return 0; 861 } 862 863 static void hisi_zip_dfx_debug_init(struct hisi_qm *qm) 864 { 865 struct dfx_diff_registers *hzip_regs = qm->debug.acc_diff_regs; 866 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 867 struct hisi_zip_dfx *dfx = &zip->dfx; 868 struct dentry *tmp_dir; 869 void *data; 870 int i; 871 872 tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root); 873 for (i = 0; i < ARRAY_SIZE(zip_dfx_files); i++) { 874 data = (atomic64_t *)((uintptr_t)dfx + zip_dfx_files[i].offset); 875 debugfs_create_file(zip_dfx_files[i].name, 876 0644, tmp_dir, data, 877 &zip_atomic64_ops); 878 } 879 880 if (qm->fun_type == QM_HW_PF && hzip_regs) 881 debugfs_create_file("diff_regs", 0444, tmp_dir, 882 qm, &hzip_diff_regs_fops); 883 } 884 885 static int hisi_zip_ctrl_debug_init(struct hisi_qm *qm) 886 { 887 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 888 int i; 889 890 for (i = HZIP_CLEAR_ENABLE; i < HZIP_DEBUG_FILE_NUM; i++) { 891 spin_lock_init(&zip->ctrl->files[i].lock); 892 zip->ctrl->files[i].ctrl = zip->ctrl; 893 zip->ctrl->files[i].index = i; 894 895 debugfs_create_file(ctrl_debug_file_name[i], 0600, 896 qm->debug.debug_root, 897 zip->ctrl->files + i, 898 &ctrl_debug_fops); 899 } 900 901 return hisi_zip_core_debug_init(qm); 902 } 903 904 static int hisi_zip_debugfs_init(struct hisi_qm *qm) 905 { 906 struct device *dev = &qm->pdev->dev; 907 struct dentry *dev_d; 908 int ret; 909 910 dev_d = debugfs_create_dir(dev_name(dev), hzip_debugfs_root); 911 912 qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET; 913 qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN; 914 qm->debug.debug_root = dev_d; 915 ret = hisi_qm_regs_debugfs_init(qm, hzip_diff_regs, ARRAY_SIZE(hzip_diff_regs)); 916 if (ret) { 917 dev_warn(dev, "Failed to init ZIP diff regs!\n"); 918 goto debugfs_remove; 919 } 920 921 hisi_qm_debug_init(qm); 922 923 if (qm->fun_type == QM_HW_PF) { 924 ret = hisi_zip_ctrl_debug_init(qm); 925 if (ret) 926 goto failed_to_create; 927 } 928 929 hisi_zip_dfx_debug_init(qm); 930 931 return 0; 932 933 failed_to_create: 934 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs)); 935 debugfs_remove: 936 debugfs_remove_recursive(hzip_debugfs_root); 937 return ret; 938 } 939 940 /* hisi_zip_debug_regs_clear() - clear the zip debug regs */ 941 static void hisi_zip_debug_regs_clear(struct hisi_qm *qm) 942 { 943 int i, j; 944 945 /* enable register read_clear bit */ 946 writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 947 for (i = 0; i < ARRAY_SIZE(core_offsets); i++) 948 for (j = 0; j < ARRAY_SIZE(hzip_dfx_regs); j++) 949 readl(qm->io_base + core_offsets[i] + 950 hzip_dfx_regs[j].offset); 951 952 /* disable register read_clear bit */ 953 writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 954 955 hisi_qm_debug_regs_clear(qm); 956 } 957 958 static void hisi_zip_debugfs_exit(struct hisi_qm *qm) 959 { 960 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs)); 961 962 debugfs_remove_recursive(qm->debug.debug_root); 963 964 if (qm->fun_type == QM_HW_PF) { 965 hisi_zip_debug_regs_clear(qm); 966 qm->debug.curr_qm_qp_num = 0; 967 } 968 } 969 970 static int hisi_zip_show_last_regs_init(struct hisi_qm *qm) 971 { 972 int core_dfx_regs_num = ARRAY_SIZE(hzip_dump_dfx_regs); 973 int com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs); 974 struct qm_debug *debug = &qm->debug; 975 void __iomem *io_base; 976 u32 zip_core_num; 977 int i, j, idx; 978 979 zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); 980 981 debug->last_words = kcalloc(core_dfx_regs_num * zip_core_num + com_dfx_regs_num, 982 sizeof(unsigned int), GFP_KERNEL); 983 if (!debug->last_words) 984 return -ENOMEM; 985 986 for (i = 0; i < com_dfx_regs_num; i++) { 987 io_base = qm->io_base + hzip_com_dfx_regs[i].offset; 988 debug->last_words[i] = readl_relaxed(io_base); 989 } 990 991 for (i = 0; i < zip_core_num; i++) { 992 io_base = qm->io_base + core_offsets[i]; 993 for (j = 0; j < core_dfx_regs_num; j++) { 994 idx = com_dfx_regs_num + i * core_dfx_regs_num + j; 995 debug->last_words[idx] = readl_relaxed( 996 io_base + hzip_dump_dfx_regs[j].offset); 997 } 998 } 999 1000 return 0; 1001 } 1002 1003 static void hisi_zip_show_last_regs_uninit(struct hisi_qm *qm) 1004 { 1005 struct qm_debug *debug = &qm->debug; 1006 1007 if (qm->fun_type == QM_HW_VF || !debug->last_words) 1008 return; 1009 1010 kfree(debug->last_words); 1011 debug->last_words = NULL; 1012 } 1013 1014 static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm) 1015 { 1016 int core_dfx_regs_num = ARRAY_SIZE(hzip_dump_dfx_regs); 1017 int com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs); 1018 u32 zip_core_num, zip_comp_core_num; 1019 struct qm_debug *debug = &qm->debug; 1020 char buf[HZIP_BUF_SIZE]; 1021 void __iomem *base; 1022 int i, j, idx; 1023 u32 val; 1024 1025 if (qm->fun_type == QM_HW_VF || !debug->last_words) 1026 return; 1027 1028 for (i = 0; i < com_dfx_regs_num; i++) { 1029 val = readl_relaxed(qm->io_base + hzip_com_dfx_regs[i].offset); 1030 if (debug->last_words[i] != val) 1031 pci_info(qm->pdev, "com_dfx: %s \t= 0x%08x => 0x%08x\n", 1032 hzip_com_dfx_regs[i].name, debug->last_words[i], val); 1033 } 1034 1035 zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); 1036 zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP, 1037 qm->cap_ver); 1038 for (i = 0; i < zip_core_num; i++) { 1039 if (i < zip_comp_core_num) 1040 scnprintf(buf, sizeof(buf), "Comp_core-%d", i); 1041 else 1042 scnprintf(buf, sizeof(buf), "Decomp_core-%d", 1043 i - zip_comp_core_num); 1044 base = qm->io_base + core_offsets[i]; 1045 1046 pci_info(qm->pdev, "==>%s:\n", buf); 1047 /* dump last word for dfx regs during control resetting */ 1048 for (j = 0; j < core_dfx_regs_num; j++) { 1049 idx = com_dfx_regs_num + i * core_dfx_regs_num + j; 1050 val = readl_relaxed(base + hzip_dump_dfx_regs[j].offset); 1051 if (debug->last_words[idx] != val) 1052 pci_info(qm->pdev, "%s \t= 0x%08x => 0x%08x\n", 1053 hzip_dump_dfx_regs[j].name, 1054 debug->last_words[idx], val); 1055 } 1056 } 1057 } 1058 1059 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts) 1060 { 1061 const struct hisi_zip_hw_error *err = zip_hw_error; 1062 struct device *dev = &qm->pdev->dev; 1063 u32 err_val; 1064 1065 while (err->msg) { 1066 if (err->int_msk & err_sts) { 1067 dev_err(dev, "%s [error status=0x%x] found\n", 1068 err->msg, err->int_msk); 1069 1070 if (err->int_msk & HZIP_CORE_INT_STATUS_M_ECC) { 1071 err_val = readl(qm->io_base + 1072 HZIP_CORE_SRAM_ECC_ERR_INFO); 1073 dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n", 1074 ((err_val >> 1075 HZIP_SRAM_ECC_ERR_NUM_SHIFT) & 0xFF)); 1076 } 1077 } 1078 err++; 1079 } 1080 } 1081 1082 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm) 1083 { 1084 return readl(qm->io_base + HZIP_CORE_INT_STATUS); 1085 } 1086 1087 static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 1088 { 1089 u32 nfe; 1090 1091 writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE); 1092 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 1093 writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1094 } 1095 1096 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm) 1097 { 1098 u32 val; 1099 1100 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1101 1102 writel(val & ~HZIP_AXI_SHUTDOWN_ENABLE, 1103 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1104 1105 writel(val | HZIP_AXI_SHUTDOWN_ENABLE, 1106 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1107 } 1108 1109 static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm) 1110 { 1111 u32 nfe_enb; 1112 1113 /* Disable ECC Mbit error report. */ 1114 nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1115 writel(nfe_enb & ~HZIP_CORE_INT_STATUS_M_ECC, 1116 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1117 1118 /* Inject zip ECC Mbit error to block master ooo. */ 1119 writel(HZIP_CORE_INT_STATUS_M_ECC, 1120 qm->io_base + HZIP_CORE_INT_SET); 1121 } 1122 1123 static void hisi_zip_err_info_init(struct hisi_qm *qm) 1124 { 1125 struct hisi_qm_err_info *err_info = &qm->err_info; 1126 1127 err_info->fe = HZIP_CORE_INT_RAS_FE_ENB_MASK; 1128 err_info->ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_QM_CE_MASK_CAP, qm->cap_ver); 1129 err_info->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1130 ZIP_QM_NFE_MASK_CAP, qm->cap_ver); 1131 err_info->ecc_2bits_mask = HZIP_CORE_INT_STATUS_M_ECC; 1132 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1133 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1134 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1135 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1136 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1137 ZIP_QM_RESET_MASK_CAP, qm->cap_ver); 1138 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1139 ZIP_RESET_MASK_CAP, qm->cap_ver); 1140 err_info->msi_wr_port = HZIP_WR_PORT; 1141 err_info->acpi_rst = "ZRST"; 1142 } 1143 1144 static const struct hisi_qm_err_ini hisi_zip_err_ini = { 1145 .hw_init = hisi_zip_set_user_domain_and_cache, 1146 .hw_err_enable = hisi_zip_hw_error_enable, 1147 .hw_err_disable = hisi_zip_hw_error_disable, 1148 .get_dev_hw_err_status = hisi_zip_get_hw_err_status, 1149 .clear_dev_hw_err_status = hisi_zip_clear_hw_err_status, 1150 .log_dev_hw_err = hisi_zip_log_hw_error, 1151 .open_axi_master_ooo = hisi_zip_open_axi_master_ooo, 1152 .close_axi_master_ooo = hisi_zip_close_axi_master_ooo, 1153 .open_sva_prefetch = hisi_zip_open_sva_prefetch, 1154 .close_sva_prefetch = hisi_zip_close_sva_prefetch, 1155 .show_last_dfx_regs = hisi_zip_show_last_dfx_regs, 1156 .err_info_init = hisi_zip_err_info_init, 1157 }; 1158 1159 static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip) 1160 { 1161 struct hisi_qm *qm = &hisi_zip->qm; 1162 struct hisi_zip_ctrl *ctrl; 1163 int ret; 1164 1165 ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL); 1166 if (!ctrl) 1167 return -ENOMEM; 1168 1169 hisi_zip->ctrl = ctrl; 1170 ctrl->hisi_zip = hisi_zip; 1171 qm->err_ini = &hisi_zip_err_ini; 1172 qm->err_ini->err_info_init(qm); 1173 1174 ret = hisi_zip_set_user_domain_and_cache(qm); 1175 if (ret) 1176 return ret; 1177 1178 ret = hisi_zip_set_high_perf(qm); 1179 if (ret) 1180 return ret; 1181 1182 hisi_zip_open_sva_prefetch(qm); 1183 hisi_qm_dev_err_init(qm); 1184 hisi_zip_debug_regs_clear(qm); 1185 1186 ret = hisi_zip_show_last_regs_init(qm); 1187 if (ret) 1188 pci_err(qm->pdev, "Failed to init last word regs!\n"); 1189 1190 return ret; 1191 } 1192 1193 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1194 { 1195 int ret; 1196 1197 qm->pdev = pdev; 1198 qm->ver = pdev->revision; 1199 qm->mode = uacce_mode; 1200 qm->sqe_size = HZIP_SQE_SIZE; 1201 qm->dev_name = hisi_zip_name; 1202 1203 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_ZIP_PF) ? 1204 QM_HW_PF : QM_HW_VF; 1205 if (qm->fun_type == QM_HW_PF) { 1206 qm->qp_base = HZIP_PF_DEF_Q_BASE; 1207 qm->qp_num = pf_q_num; 1208 qm->debug.curr_qm_qp_num = pf_q_num; 1209 qm->qm_list = &zip_devices; 1210 if (pf_q_num_flag) 1211 set_bit(QM_MODULE_PARAM, &qm->misc_ctl); 1212 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { 1213 /* 1214 * have no way to get qm configure in VM in v1 hardware, 1215 * so currently force PF to uses HZIP_PF_DEF_Q_NUM, and force 1216 * to trigger only one VF in v1 hardware. 1217 * 1218 * v2 hardware has no such problem. 1219 */ 1220 qm->qp_base = HZIP_PF_DEF_Q_NUM; 1221 qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM; 1222 } 1223 1224 ret = hisi_qm_init(qm); 1225 if (ret) { 1226 pci_err(qm->pdev, "Failed to init zip qm configures!\n"); 1227 return ret; 1228 } 1229 1230 ret = hisi_zip_set_qm_algs(qm); 1231 if (ret) { 1232 pci_err(qm->pdev, "Failed to set zip algs!\n"); 1233 hisi_qm_uninit(qm); 1234 } 1235 1236 return ret; 1237 } 1238 1239 static void hisi_zip_qm_uninit(struct hisi_qm *qm) 1240 { 1241 hisi_qm_uninit(qm); 1242 } 1243 1244 static int hisi_zip_probe_init(struct hisi_zip *hisi_zip) 1245 { 1246 u32 type_rate = HZIP_SHAPER_RATE_COMPRESS; 1247 struct hisi_qm *qm = &hisi_zip->qm; 1248 int ret; 1249 1250 if (qm->fun_type == QM_HW_PF) { 1251 ret = hisi_zip_pf_probe_init(hisi_zip); 1252 if (ret) 1253 return ret; 1254 /* enable shaper type 0 */ 1255 if (qm->ver >= QM_HW_V3) { 1256 type_rate |= QM_SHAPER_ENABLE; 1257 1258 /* ZIP need to enable shaper type 1 */ 1259 type_rate |= HZIP_SHAPER_RATE_DECOMPRESS << QM_SHAPER_TYPE1_OFFSET; 1260 qm->type_rate = type_rate; 1261 } 1262 } 1263 1264 return 0; 1265 } 1266 1267 static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1268 { 1269 struct hisi_zip *hisi_zip; 1270 struct hisi_qm *qm; 1271 int ret; 1272 1273 hisi_zip = devm_kzalloc(&pdev->dev, sizeof(*hisi_zip), GFP_KERNEL); 1274 if (!hisi_zip) 1275 return -ENOMEM; 1276 1277 qm = &hisi_zip->qm; 1278 1279 ret = hisi_zip_qm_init(qm, pdev); 1280 if (ret) { 1281 pci_err(pdev, "Failed to init ZIP QM (%d)!\n", ret); 1282 return ret; 1283 } 1284 1285 ret = hisi_zip_probe_init(hisi_zip); 1286 if (ret) { 1287 pci_err(pdev, "Failed to probe (%d)!\n", ret); 1288 goto err_qm_uninit; 1289 } 1290 1291 ret = hisi_qm_start(qm); 1292 if (ret) 1293 goto err_dev_err_uninit; 1294 1295 ret = hisi_zip_debugfs_init(qm); 1296 if (ret) 1297 pci_err(pdev, "failed to init debugfs (%d)!\n", ret); 1298 1299 ret = hisi_qm_alg_register(qm, &zip_devices); 1300 if (ret < 0) { 1301 pci_err(pdev, "failed to register driver to crypto!\n"); 1302 goto err_qm_stop; 1303 } 1304 1305 if (qm->uacce) { 1306 ret = uacce_register(qm->uacce); 1307 if (ret) { 1308 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 1309 goto err_qm_alg_unregister; 1310 } 1311 } 1312 1313 if (qm->fun_type == QM_HW_PF && vfs_num > 0) { 1314 ret = hisi_qm_sriov_enable(pdev, vfs_num); 1315 if (ret < 0) 1316 goto err_qm_alg_unregister; 1317 } 1318 1319 hisi_qm_pm_init(qm); 1320 1321 return 0; 1322 1323 err_qm_alg_unregister: 1324 hisi_qm_alg_unregister(qm, &zip_devices); 1325 1326 err_qm_stop: 1327 hisi_zip_debugfs_exit(qm); 1328 hisi_qm_stop(qm, QM_NORMAL); 1329 1330 err_dev_err_uninit: 1331 hisi_zip_show_last_regs_uninit(qm); 1332 hisi_qm_dev_err_uninit(qm); 1333 1334 err_qm_uninit: 1335 hisi_zip_qm_uninit(qm); 1336 1337 return ret; 1338 } 1339 1340 static void hisi_zip_remove(struct pci_dev *pdev) 1341 { 1342 struct hisi_qm *qm = pci_get_drvdata(pdev); 1343 1344 hisi_qm_pm_uninit(qm); 1345 hisi_qm_wait_task_finish(qm, &zip_devices); 1346 hisi_qm_alg_unregister(qm, &zip_devices); 1347 1348 if (qm->fun_type == QM_HW_PF && qm->vfs_num) 1349 hisi_qm_sriov_disable(pdev, true); 1350 1351 hisi_zip_debugfs_exit(qm); 1352 hisi_qm_stop(qm, QM_NORMAL); 1353 hisi_zip_show_last_regs_uninit(qm); 1354 hisi_qm_dev_err_uninit(qm); 1355 hisi_zip_qm_uninit(qm); 1356 } 1357 1358 static const struct dev_pm_ops hisi_zip_pm_ops = { 1359 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL) 1360 }; 1361 1362 static const struct pci_error_handlers hisi_zip_err_handler = { 1363 .error_detected = hisi_qm_dev_err_detected, 1364 .slot_reset = hisi_qm_dev_slot_reset, 1365 .reset_prepare = hisi_qm_reset_prepare, 1366 .reset_done = hisi_qm_reset_done, 1367 }; 1368 1369 static struct pci_driver hisi_zip_pci_driver = { 1370 .name = "hisi_zip", 1371 .id_table = hisi_zip_dev_ids, 1372 .probe = hisi_zip_probe, 1373 .remove = hisi_zip_remove, 1374 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ? 1375 hisi_qm_sriov_configure : NULL, 1376 .err_handler = &hisi_zip_err_handler, 1377 .shutdown = hisi_qm_dev_shutdown, 1378 .driver.pm = &hisi_zip_pm_ops, 1379 }; 1380 1381 struct pci_driver *hisi_zip_get_pf_driver(void) 1382 { 1383 return &hisi_zip_pci_driver; 1384 } 1385 EXPORT_SYMBOL_GPL(hisi_zip_get_pf_driver); 1386 1387 static void hisi_zip_register_debugfs(void) 1388 { 1389 if (!debugfs_initialized()) 1390 return; 1391 1392 hzip_debugfs_root = debugfs_create_dir("hisi_zip", NULL); 1393 } 1394 1395 static void hisi_zip_unregister_debugfs(void) 1396 { 1397 debugfs_remove_recursive(hzip_debugfs_root); 1398 } 1399 1400 static int __init hisi_zip_init(void) 1401 { 1402 int ret; 1403 1404 hisi_qm_init_list(&zip_devices); 1405 hisi_zip_register_debugfs(); 1406 1407 ret = pci_register_driver(&hisi_zip_pci_driver); 1408 if (ret < 0) { 1409 hisi_zip_unregister_debugfs(); 1410 pr_err("Failed to register pci driver.\n"); 1411 } 1412 1413 return ret; 1414 } 1415 1416 static void __exit hisi_zip_exit(void) 1417 { 1418 pci_unregister_driver(&hisi_zip_pci_driver); 1419 hisi_zip_unregister_debugfs(); 1420 } 1421 1422 module_init(hisi_zip_init); 1423 module_exit(hisi_zip_exit); 1424 1425 MODULE_LICENSE("GPL v2"); 1426 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>"); 1427 MODULE_DESCRIPTION("Driver for HiSilicon ZIP accelerator"); 1428