1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/bitops.h> 5 #include <linux/debugfs.h> 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/seq_file.h> 13 #include <linux/topology.h> 14 #include <linux/uacce.h> 15 #include "zip.h" 16 17 #define PCI_DEVICE_ID_HUAWEI_ZIP_PF 0xa250 18 19 #define HZIP_QUEUE_NUM_V1 4096 20 21 #define HZIP_CLOCK_GATE_CTRL 0x301004 22 #define HZIP_DECOMP_CHECK_ENABLE BIT(16) 23 #define HZIP_FSM_MAX_CNT 0x301008 24 25 #define HZIP_PORT_ARCA_CHE_0 0x301040 26 #define HZIP_PORT_ARCA_CHE_1 0x301044 27 #define HZIP_PORT_AWCA_CHE_0 0x301060 28 #define HZIP_PORT_AWCA_CHE_1 0x301064 29 #define HZIP_CACHE_ALL_EN 0xffffffff 30 31 #define HZIP_BD_RUSER_32_63 0x301110 32 #define HZIP_SGL_RUSER_32_63 0x30111c 33 #define HZIP_DATA_RUSER_32_63 0x301128 34 #define HZIP_DATA_WUSER_32_63 0x301134 35 #define HZIP_BD_WUSER_32_63 0x301140 36 37 #define HZIP_QM_IDEL_STATUS 0x3040e4 38 39 #define HZIP_CORE_DFX_BASE 0x301000 40 #define HZIP_CLOCK_GATED_CONTL 0X301004 41 #define HZIP_CORE_DFX_COMP_0 0x302000 42 #define HZIP_CORE_DFX_COMP_1 0x303000 43 #define HZIP_CORE_DFX_DECOMP_0 0x304000 44 #define HZIP_CORE_DFX_DECOMP_1 0x305000 45 #define HZIP_CORE_DFX_DECOMP_2 0x306000 46 #define HZIP_CORE_DFX_DECOMP_3 0x307000 47 #define HZIP_CORE_DFX_DECOMP_4 0x308000 48 #define HZIP_CORE_DFX_DECOMP_5 0x309000 49 #define HZIP_CORE_REGS_BASE_LEN 0xB0 50 #define HZIP_CORE_REGS_DFX_LEN 0x28 51 52 #define HZIP_CORE_INT_SOURCE 0x3010A0 53 #define HZIP_CORE_INT_MASK_REG 0x3010A4 54 #define HZIP_CORE_INT_SET 0x3010A8 55 #define HZIP_CORE_INT_STATUS 0x3010AC 56 #define HZIP_CORE_INT_STATUS_M_ECC BIT(1) 57 #define HZIP_CORE_SRAM_ECC_ERR_INFO 0x301148 58 #define HZIP_CORE_INT_RAS_CE_ENB 0x301160 59 #define HZIP_CORE_INT_RAS_NFE_ENB 0x301164 60 #define HZIP_CORE_INT_RAS_FE_ENB 0x301168 61 #define HZIP_CORE_INT_RAS_FE_ENB_MASK 0x0 62 #define HZIP_OOO_SHUTDOWN_SEL 0x30120C 63 #define HZIP_SRAM_ECC_ERR_NUM_SHIFT 16 64 #define HZIP_SRAM_ECC_ERR_ADDR_SHIFT 24 65 #define HZIP_CORE_INT_MASK_ALL GENMASK(12, 0) 66 #define HZIP_SQE_SIZE 128 67 #define HZIP_PF_DEF_Q_NUM 64 68 #define HZIP_PF_DEF_Q_BASE 0 69 70 #define HZIP_SOFT_CTRL_CNT_CLR_CE 0x301000 71 #define HZIP_SOFT_CTRL_CNT_CLR_CE_BIT BIT(0) 72 #define HZIP_SOFT_CTRL_ZIP_CONTROL 0x30100C 73 #define HZIP_AXI_SHUTDOWN_ENABLE BIT(14) 74 #define HZIP_WR_PORT BIT(11) 75 76 #define HZIP_ALG_ZLIB_BIT GENMASK(1, 0) 77 #define HZIP_ALG_GZIP_BIT GENMASK(3, 2) 78 #define HZIP_ALG_DEFLATE_BIT GENMASK(5, 4) 79 #define HZIP_ALG_LZ77_BIT GENMASK(7, 6) 80 81 #define HZIP_BUF_SIZE 22 82 #define HZIP_SQE_MASK_OFFSET 64 83 #define HZIP_SQE_MASK_LEN 48 84 85 #define HZIP_CNT_CLR_CE_EN BIT(0) 86 #define HZIP_RO_CNT_CLR_CE_EN BIT(2) 87 #define HZIP_RD_CNT_CLR_CE_EN (HZIP_CNT_CLR_CE_EN | \ 88 HZIP_RO_CNT_CLR_CE_EN) 89 90 #define HZIP_PREFETCH_CFG 0x3011B0 91 #define HZIP_SVA_TRANS 0x3011C4 92 #define HZIP_PREFETCH_ENABLE (~(BIT(26) | BIT(17) | BIT(0))) 93 #define HZIP_SVA_PREFETCH_DISABLE BIT(26) 94 #define HZIP_SVA_DISABLE_READY (BIT(26) | BIT(30)) 95 #define HZIP_SHAPER_RATE_COMPRESS 750 96 #define HZIP_SHAPER_RATE_DECOMPRESS 140 97 #define HZIP_DELAY_1_US 1 98 #define HZIP_POLL_TIMEOUT_US 1000 99 100 /* clock gating */ 101 #define HZIP_PEH_CFG_AUTO_GATE 0x3011A8 102 #define HZIP_PEH_CFG_AUTO_GATE_EN BIT(0) 103 #define HZIP_CORE_GATED_EN GENMASK(15, 8) 104 #define HZIP_CORE_GATED_OOO_EN BIT(29) 105 #define HZIP_CLOCK_GATED_EN (HZIP_CORE_GATED_EN | \ 106 HZIP_CORE_GATED_OOO_EN) 107 108 /* zip comp high performance */ 109 #define HZIP_HIGH_PERF_OFFSET 0x301208 110 111 enum { 112 HZIP_HIGH_COMP_RATE, 113 HZIP_HIGH_COMP_PERF, 114 }; 115 116 static const char hisi_zip_name[] = "hisi_zip"; 117 static struct dentry *hzip_debugfs_root; 118 119 struct hisi_zip_hw_error { 120 u32 int_msk; 121 const char *msg; 122 }; 123 124 struct zip_dfx_item { 125 const char *name; 126 u32 offset; 127 }; 128 129 static const struct qm_dev_alg zip_dev_algs[] = { { 130 .alg_msk = HZIP_ALG_ZLIB_BIT, 131 .alg = "zlib\n", 132 }, { 133 .alg_msk = HZIP_ALG_GZIP_BIT, 134 .alg = "gzip\n", 135 }, { 136 .alg_msk = HZIP_ALG_DEFLATE_BIT, 137 .alg = "deflate\n", 138 }, { 139 .alg_msk = HZIP_ALG_LZ77_BIT, 140 .alg = "lz77_zstd\n", 141 }, 142 }; 143 144 static struct hisi_qm_list zip_devices = { 145 .register_to_crypto = hisi_zip_register_to_crypto, 146 .unregister_from_crypto = hisi_zip_unregister_from_crypto, 147 }; 148 149 static struct zip_dfx_item zip_dfx_files[] = { 150 {"send_cnt", offsetof(struct hisi_zip_dfx, send_cnt)}, 151 {"recv_cnt", offsetof(struct hisi_zip_dfx, recv_cnt)}, 152 {"send_busy_cnt", offsetof(struct hisi_zip_dfx, send_busy_cnt)}, 153 {"err_bd_cnt", offsetof(struct hisi_zip_dfx, err_bd_cnt)}, 154 }; 155 156 static const struct hisi_zip_hw_error zip_hw_error[] = { 157 { .int_msk = BIT(0), .msg = "zip_ecc_1bitt_err" }, 158 { .int_msk = BIT(1), .msg = "zip_ecc_2bit_err" }, 159 { .int_msk = BIT(2), .msg = "zip_axi_rresp_err" }, 160 { .int_msk = BIT(3), .msg = "zip_axi_bresp_err" }, 161 { .int_msk = BIT(4), .msg = "zip_src_addr_parse_err" }, 162 { .int_msk = BIT(5), .msg = "zip_dst_addr_parse_err" }, 163 { .int_msk = BIT(6), .msg = "zip_pre_in_addr_err" }, 164 { .int_msk = BIT(7), .msg = "zip_pre_in_data_err" }, 165 { .int_msk = BIT(8), .msg = "zip_com_inf_err" }, 166 { .int_msk = BIT(9), .msg = "zip_enc_inf_err" }, 167 { .int_msk = BIT(10), .msg = "zip_pre_out_err" }, 168 { .int_msk = BIT(11), .msg = "zip_axi_poison_err" }, 169 { .int_msk = BIT(12), .msg = "zip_sva_err" }, 170 { /* sentinel */ } 171 }; 172 173 enum ctrl_debug_file_index { 174 HZIP_CLEAR_ENABLE, 175 HZIP_DEBUG_FILE_NUM, 176 }; 177 178 static const char * const ctrl_debug_file_name[] = { 179 [HZIP_CLEAR_ENABLE] = "clear_enable", 180 }; 181 182 struct ctrl_debug_file { 183 enum ctrl_debug_file_index index; 184 spinlock_t lock; 185 struct hisi_zip_ctrl *ctrl; 186 }; 187 188 /* 189 * One ZIP controller has one PF and multiple VFs, some global configurations 190 * which PF has need this structure. 191 * 192 * Just relevant for PF. 193 */ 194 struct hisi_zip_ctrl { 195 struct hisi_zip *hisi_zip; 196 struct ctrl_debug_file files[HZIP_DEBUG_FILE_NUM]; 197 }; 198 199 enum zip_cap_type { 200 ZIP_QM_NFE_MASK_CAP = 0x0, 201 ZIP_QM_RESET_MASK_CAP, 202 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, 203 ZIP_QM_CE_MASK_CAP, 204 ZIP_NFE_MASK_CAP, 205 ZIP_RESET_MASK_CAP, 206 ZIP_OOO_SHUTDOWN_MASK_CAP, 207 ZIP_CE_MASK_CAP, 208 ZIP_CLUSTER_NUM_CAP, 209 ZIP_CORE_TYPE_NUM_CAP, 210 ZIP_CORE_NUM_CAP, 211 ZIP_CLUSTER_COMP_NUM_CAP, 212 ZIP_CLUSTER_DECOMP_NUM_CAP, 213 ZIP_DECOMP_ENABLE_BITMAP, 214 ZIP_COMP_ENABLE_BITMAP, 215 ZIP_DRV_ALG_BITMAP, 216 ZIP_DEV_ALG_BITMAP, 217 ZIP_CORE1_ALG_BITMAP, 218 ZIP_CORE2_ALG_BITMAP, 219 ZIP_CORE3_ALG_BITMAP, 220 ZIP_CORE4_ALG_BITMAP, 221 ZIP_CORE5_ALG_BITMAP, 222 ZIP_CAP_MAX 223 }; 224 225 static struct hisi_qm_cap_info zip_basic_cap_info[] = { 226 {ZIP_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C57, 0x7C77}, 227 {ZIP_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC57, 0x6C77}, 228 {ZIP_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C77}, 229 {ZIP_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8}, 230 {ZIP_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x1FFE}, 231 {ZIP_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x7FE}, 232 {ZIP_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x2, 0x7FE}, 233 {ZIP_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1}, 234 {ZIP_CLUSTER_NUM_CAP, 0x313C, 28, GENMASK(3, 0), 0x1, 0x1, 0x1}, 235 {ZIP_CORE_TYPE_NUM_CAP, 0x313C, 24, GENMASK(3, 0), 0x2, 0x2, 0x2}, 236 {ZIP_CORE_NUM_CAP, 0x313C, 16, GENMASK(7, 0), 0x8, 0x8, 0x5}, 237 {ZIP_CLUSTER_COMP_NUM_CAP, 0x313C, 8, GENMASK(7, 0), 0x2, 0x2, 0x2}, 238 {ZIP_CLUSTER_DECOMP_NUM_CAP, 0x313C, 0, GENMASK(7, 0), 0x6, 0x6, 0x3}, 239 {ZIP_DECOMP_ENABLE_BITMAP, 0x3140, 16, GENMASK(15, 0), 0xFC, 0xFC, 0x1C}, 240 {ZIP_COMP_ENABLE_BITMAP, 0x3140, 0, GENMASK(15, 0), 0x3, 0x3, 0x3}, 241 {ZIP_DRV_ALG_BITMAP, 0x3144, 0, GENMASK(31, 0), 0xF, 0xF, 0xF}, 242 {ZIP_DEV_ALG_BITMAP, 0x3148, 0, GENMASK(31, 0), 0xF, 0xF, 0xFF}, 243 {ZIP_CORE1_ALG_BITMAP, 0x314C, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5}, 244 {ZIP_CORE2_ALG_BITMAP, 0x3150, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5}, 245 {ZIP_CORE3_ALG_BITMAP, 0x3154, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 246 {ZIP_CORE4_ALG_BITMAP, 0x3158, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 247 {ZIP_CORE5_ALG_BITMAP, 0x315C, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 248 {ZIP_CAP_MAX, 0x317c, 0, GENMASK(0, 0), 0x0, 0x0, 0x0} 249 }; 250 251 enum { 252 HZIP_COMP_CORE0, 253 HZIP_COMP_CORE1, 254 HZIP_DECOMP_CORE0, 255 HZIP_DECOMP_CORE1, 256 HZIP_DECOMP_CORE2, 257 HZIP_DECOMP_CORE3, 258 HZIP_DECOMP_CORE4, 259 HZIP_DECOMP_CORE5, 260 }; 261 262 static const u64 core_offsets[] = { 263 [HZIP_COMP_CORE0] = 0x302000, 264 [HZIP_COMP_CORE1] = 0x303000, 265 [HZIP_DECOMP_CORE0] = 0x304000, 266 [HZIP_DECOMP_CORE1] = 0x305000, 267 [HZIP_DECOMP_CORE2] = 0x306000, 268 [HZIP_DECOMP_CORE3] = 0x307000, 269 [HZIP_DECOMP_CORE4] = 0x308000, 270 [HZIP_DECOMP_CORE5] = 0x309000, 271 }; 272 273 static const struct debugfs_reg32 hzip_dfx_regs[] = { 274 {"HZIP_GET_BD_NUM ", 0x00ull}, 275 {"HZIP_GET_RIGHT_BD ", 0x04ull}, 276 {"HZIP_GET_ERROR_BD ", 0x08ull}, 277 {"HZIP_DONE_BD_NUM ", 0x0cull}, 278 {"HZIP_WORK_CYCLE ", 0x10ull}, 279 {"HZIP_IDLE_CYCLE ", 0x18ull}, 280 {"HZIP_MAX_DELAY ", 0x20ull}, 281 {"HZIP_MIN_DELAY ", 0x24ull}, 282 {"HZIP_AVG_DELAY ", 0x28ull}, 283 {"HZIP_MEM_VISIBLE_DATA ", 0x30ull}, 284 {"HZIP_MEM_VISIBLE_ADDR ", 0x34ull}, 285 {"HZIP_CONSUMED_BYTE ", 0x38ull}, 286 {"HZIP_PRODUCED_BYTE ", 0x40ull}, 287 {"HZIP_COMP_INF ", 0x70ull}, 288 {"HZIP_PRE_OUT ", 0x78ull}, 289 {"HZIP_BD_RD ", 0x7cull}, 290 {"HZIP_BD_WR ", 0x80ull}, 291 {"HZIP_GET_BD_AXI_ERR_NUM ", 0x84ull}, 292 {"HZIP_GET_BD_PARSE_ERR_NUM ", 0x88ull}, 293 {"HZIP_ADD_BD_AXI_ERR_NUM ", 0x8cull}, 294 {"HZIP_DECOMP_STF_RELOAD_CURR_ST ", 0x94ull}, 295 {"HZIP_DECOMP_LZ77_CURR_ST ", 0x9cull}, 296 }; 297 298 static const struct debugfs_reg32 hzip_com_dfx_regs[] = { 299 {"HZIP_CLOCK_GATE_CTRL ", 0x301004}, 300 {"HZIP_CORE_INT_RAS_CE_ENB ", 0x301160}, 301 {"HZIP_CORE_INT_RAS_NFE_ENB ", 0x301164}, 302 {"HZIP_CORE_INT_RAS_FE_ENB ", 0x301168}, 303 {"HZIP_UNCOM_ERR_RAS_CTRL ", 0x30116C}, 304 }; 305 306 static const struct debugfs_reg32 hzip_dump_dfx_regs[] = { 307 {"HZIP_GET_BD_NUM ", 0x00ull}, 308 {"HZIP_GET_RIGHT_BD ", 0x04ull}, 309 {"HZIP_GET_ERROR_BD ", 0x08ull}, 310 {"HZIP_DONE_BD_NUM ", 0x0cull}, 311 {"HZIP_MAX_DELAY ", 0x20ull}, 312 }; 313 314 /* define the ZIP's dfx regs region and region length */ 315 static struct dfx_diff_registers hzip_diff_regs[] = { 316 { 317 .reg_offset = HZIP_CORE_DFX_BASE, 318 .reg_len = HZIP_CORE_REGS_BASE_LEN, 319 }, { 320 .reg_offset = HZIP_CORE_DFX_COMP_0, 321 .reg_len = HZIP_CORE_REGS_DFX_LEN, 322 }, { 323 .reg_offset = HZIP_CORE_DFX_COMP_1, 324 .reg_len = HZIP_CORE_REGS_DFX_LEN, 325 }, { 326 .reg_offset = HZIP_CORE_DFX_DECOMP_0, 327 .reg_len = HZIP_CORE_REGS_DFX_LEN, 328 }, { 329 .reg_offset = HZIP_CORE_DFX_DECOMP_1, 330 .reg_len = HZIP_CORE_REGS_DFX_LEN, 331 }, { 332 .reg_offset = HZIP_CORE_DFX_DECOMP_2, 333 .reg_len = HZIP_CORE_REGS_DFX_LEN, 334 }, { 335 .reg_offset = HZIP_CORE_DFX_DECOMP_3, 336 .reg_len = HZIP_CORE_REGS_DFX_LEN, 337 }, { 338 .reg_offset = HZIP_CORE_DFX_DECOMP_4, 339 .reg_len = HZIP_CORE_REGS_DFX_LEN, 340 }, { 341 .reg_offset = HZIP_CORE_DFX_DECOMP_5, 342 .reg_len = HZIP_CORE_REGS_DFX_LEN, 343 }, 344 }; 345 346 static int hzip_diff_regs_show(struct seq_file *s, void *unused) 347 { 348 struct hisi_qm *qm = s->private; 349 350 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, 351 ARRAY_SIZE(hzip_diff_regs)); 352 353 return 0; 354 } 355 DEFINE_SHOW_ATTRIBUTE(hzip_diff_regs); 356 357 static int perf_mode_set(const char *val, const struct kernel_param *kp) 358 { 359 int ret; 360 u32 n; 361 362 if (!val) 363 return -EINVAL; 364 365 ret = kstrtou32(val, 10, &n); 366 if (ret != 0 || (n != HZIP_HIGH_COMP_PERF && 367 n != HZIP_HIGH_COMP_RATE)) 368 return -EINVAL; 369 370 return param_set_int(val, kp); 371 } 372 373 static const struct kernel_param_ops zip_com_perf_ops = { 374 .set = perf_mode_set, 375 .get = param_get_int, 376 }; 377 378 /* 379 * perf_mode = 0 means enable high compression rate mode, 380 * perf_mode = 1 means enable high compression performance mode. 381 * These two modes only apply to the compression direction. 382 */ 383 static u32 perf_mode = HZIP_HIGH_COMP_RATE; 384 module_param_cb(perf_mode, &zip_com_perf_ops, &perf_mode, 0444); 385 MODULE_PARM_DESC(perf_mode, "ZIP high perf mode 0(default), 1(enable)"); 386 387 static const struct kernel_param_ops zip_uacce_mode_ops = { 388 .set = uacce_mode_set, 389 .get = param_get_int, 390 }; 391 392 /* 393 * uacce_mode = 0 means zip only register to crypto, 394 * uacce_mode = 1 means zip both register to crypto and uacce. 395 */ 396 static u32 uacce_mode = UACCE_MODE_NOUACCE; 397 module_param_cb(uacce_mode, &zip_uacce_mode_ops, &uacce_mode, 0444); 398 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 399 400 static bool pf_q_num_flag; 401 static int pf_q_num_set(const char *val, const struct kernel_param *kp) 402 { 403 pf_q_num_flag = true; 404 405 return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_ZIP_PF); 406 } 407 408 static const struct kernel_param_ops pf_q_num_ops = { 409 .set = pf_q_num_set, 410 .get = param_get_int, 411 }; 412 413 static u32 pf_q_num = HZIP_PF_DEF_Q_NUM; 414 module_param_cb(pf_q_num, &pf_q_num_ops, &pf_q_num, 0444); 415 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)"); 416 417 static const struct kernel_param_ops vfs_num_ops = { 418 .set = vfs_num_set, 419 .get = param_get_int, 420 }; 421 422 static u32 vfs_num; 423 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 424 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 425 426 static const struct pci_device_id hisi_zip_dev_ids[] = { 427 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_ZIP_PF) }, 428 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_ZIP_VF) }, 429 { 0, } 430 }; 431 MODULE_DEVICE_TABLE(pci, hisi_zip_dev_ids); 432 433 int zip_create_qps(struct hisi_qp **qps, int qp_num, int node) 434 { 435 if (node == NUMA_NO_NODE) 436 node = cpu_to_node(smp_processor_id()); 437 438 return hisi_qm_alloc_qps_node(&zip_devices, qp_num, 0, node, qps); 439 } 440 441 bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg) 442 { 443 u32 cap_val; 444 445 cap_val = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DRV_ALG_BITMAP, qm->cap_ver); 446 if ((alg & cap_val) == alg) 447 return true; 448 449 return false; 450 } 451 452 static int hisi_zip_set_high_perf(struct hisi_qm *qm) 453 { 454 u32 val; 455 int ret; 456 457 val = readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET); 458 if (perf_mode == HZIP_HIGH_COMP_PERF) 459 val |= HZIP_HIGH_COMP_PERF; 460 else 461 val &= ~HZIP_HIGH_COMP_PERF; 462 463 /* Set perf mode */ 464 writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET); 465 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_HIGH_PERF_OFFSET, 466 val, val == perf_mode, HZIP_DELAY_1_US, 467 HZIP_POLL_TIMEOUT_US); 468 if (ret) 469 pci_err(qm->pdev, "failed to set perf mode\n"); 470 471 return ret; 472 } 473 474 static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) 475 { 476 u32 val; 477 int ret; 478 479 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 480 return; 481 482 /* Enable prefetch */ 483 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); 484 val &= HZIP_PREFETCH_ENABLE; 485 writel(val, qm->io_base + HZIP_PREFETCH_CFG); 486 487 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG, 488 val, !(val & HZIP_SVA_PREFETCH_DISABLE), 489 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); 490 if (ret) 491 pci_err(qm->pdev, "failed to open sva prefetch\n"); 492 } 493 494 static void hisi_zip_close_sva_prefetch(struct hisi_qm *qm) 495 { 496 u32 val; 497 int ret; 498 499 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 500 return; 501 502 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); 503 val |= HZIP_SVA_PREFETCH_DISABLE; 504 writel(val, qm->io_base + HZIP_PREFETCH_CFG); 505 506 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS, 507 val, !(val & HZIP_SVA_DISABLE_READY), 508 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); 509 if (ret) 510 pci_err(qm->pdev, "failed to close sva prefetch\n"); 511 } 512 513 static void hisi_zip_enable_clock_gate(struct hisi_qm *qm) 514 { 515 u32 val; 516 517 if (qm->ver < QM_HW_V3) 518 return; 519 520 val = readl(qm->io_base + HZIP_CLOCK_GATE_CTRL); 521 val |= HZIP_CLOCK_GATED_EN; 522 writel(val, qm->io_base + HZIP_CLOCK_GATE_CTRL); 523 524 val = readl(qm->io_base + HZIP_PEH_CFG_AUTO_GATE); 525 val |= HZIP_PEH_CFG_AUTO_GATE_EN; 526 writel(val, qm->io_base + HZIP_PEH_CFG_AUTO_GATE); 527 } 528 529 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm) 530 { 531 void __iomem *base = qm->io_base; 532 u32 dcomp_bm, comp_bm; 533 534 /* qm user domain */ 535 writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1); 536 writel(ARUSER_M_CFG_ENABLE, base + QM_ARUSER_M_CFG_ENABLE); 537 writel(AXUSER_BASE, base + QM_AWUSER_M_CFG_1); 538 writel(AWUSER_M_CFG_ENABLE, base + QM_AWUSER_M_CFG_ENABLE); 539 writel(WUSER_M_CFG_ENABLE, base + QM_WUSER_M_CFG_ENABLE); 540 541 /* qm cache */ 542 writel(AXI_M_CFG, base + QM_AXI_M_CFG); 543 writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE); 544 545 /* disable FLR triggered by BME(bus master enable) */ 546 writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG); 547 writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE); 548 549 /* cache */ 550 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_0); 551 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_1); 552 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_0); 553 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_1); 554 555 /* user domain configurations */ 556 writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63); 557 writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63); 558 559 if (qm->use_sva && qm->ver == QM_HW_V2) { 560 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63); 561 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63); 562 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_SGL_RUSER_32_63); 563 } else { 564 writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63); 565 writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63); 566 writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63); 567 } 568 569 /* let's open all compression/decompression cores */ 570 dcomp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 571 ZIP_DECOMP_ENABLE_BITMAP, qm->cap_ver); 572 comp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 573 ZIP_COMP_ENABLE_BITMAP, qm->cap_ver); 574 writel(HZIP_DECOMP_CHECK_ENABLE | dcomp_bm | comp_bm, base + HZIP_CLOCK_GATE_CTRL); 575 576 /* enable sqc,cqc writeback */ 577 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE | 578 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) | 579 FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL); 580 581 hisi_zip_enable_clock_gate(qm); 582 583 return 0; 584 } 585 586 static void hisi_zip_master_ooo_ctrl(struct hisi_qm *qm, bool enable) 587 { 588 u32 val1, val2; 589 590 val1 = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 591 if (enable) { 592 val1 |= HZIP_AXI_SHUTDOWN_ENABLE; 593 val2 = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 594 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 595 } else { 596 val1 &= ~HZIP_AXI_SHUTDOWN_ENABLE; 597 val2 = 0x0; 598 } 599 600 if (qm->ver > QM_HW_V2) 601 writel(val2, qm->io_base + HZIP_OOO_SHUTDOWN_SEL); 602 603 writel(val1, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 604 } 605 606 static void hisi_zip_hw_error_enable(struct hisi_qm *qm) 607 { 608 u32 nfe, ce; 609 610 if (qm->ver == QM_HW_V1) { 611 writel(HZIP_CORE_INT_MASK_ALL, 612 qm->io_base + HZIP_CORE_INT_MASK_REG); 613 dev_info(&qm->pdev->dev, "Does not support hw error handle\n"); 614 return; 615 } 616 617 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 618 ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); 619 620 /* clear ZIP hw error source if having */ 621 writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_SOURCE); 622 623 /* configure error type */ 624 writel(ce, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); 625 writel(HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB); 626 writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 627 628 hisi_zip_master_ooo_ctrl(qm, true); 629 630 /* enable ZIP hw error interrupts */ 631 writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG); 632 } 633 634 static void hisi_zip_hw_error_disable(struct hisi_qm *qm) 635 { 636 u32 nfe, ce; 637 638 /* disable ZIP hw error interrupts */ 639 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 640 ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); 641 writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_MASK_REG); 642 643 hisi_zip_master_ooo_ctrl(qm, false); 644 } 645 646 static inline struct hisi_qm *file_to_qm(struct ctrl_debug_file *file) 647 { 648 struct hisi_zip *hisi_zip = file->ctrl->hisi_zip; 649 650 return &hisi_zip->qm; 651 } 652 653 static u32 clear_enable_read(struct hisi_qm *qm) 654 { 655 return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 656 HZIP_SOFT_CTRL_CNT_CLR_CE_BIT; 657 } 658 659 static int clear_enable_write(struct hisi_qm *qm, u32 val) 660 { 661 u32 tmp; 662 663 if (val != 1 && val != 0) 664 return -EINVAL; 665 666 tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 667 ~HZIP_SOFT_CTRL_CNT_CLR_CE_BIT) | val; 668 writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 669 670 return 0; 671 } 672 673 static ssize_t hisi_zip_ctrl_debug_read(struct file *filp, char __user *buf, 674 size_t count, loff_t *pos) 675 { 676 struct ctrl_debug_file *file = filp->private_data; 677 struct hisi_qm *qm = file_to_qm(file); 678 char tbuf[HZIP_BUF_SIZE]; 679 u32 val; 680 int ret; 681 682 ret = hisi_qm_get_dfx_access(qm); 683 if (ret) 684 return ret; 685 686 spin_lock_irq(&file->lock); 687 switch (file->index) { 688 case HZIP_CLEAR_ENABLE: 689 val = clear_enable_read(qm); 690 break; 691 default: 692 goto err_input; 693 } 694 spin_unlock_irq(&file->lock); 695 696 hisi_qm_put_dfx_access(qm); 697 ret = scnprintf(tbuf, sizeof(tbuf), "%u\n", val); 698 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 699 700 err_input: 701 spin_unlock_irq(&file->lock); 702 hisi_qm_put_dfx_access(qm); 703 return -EINVAL; 704 } 705 706 static ssize_t hisi_zip_ctrl_debug_write(struct file *filp, 707 const char __user *buf, 708 size_t count, loff_t *pos) 709 { 710 struct ctrl_debug_file *file = filp->private_data; 711 struct hisi_qm *qm = file_to_qm(file); 712 char tbuf[HZIP_BUF_SIZE]; 713 unsigned long val; 714 int len, ret; 715 716 if (*pos != 0) 717 return 0; 718 719 if (count >= HZIP_BUF_SIZE) 720 return -ENOSPC; 721 722 len = simple_write_to_buffer(tbuf, HZIP_BUF_SIZE - 1, pos, buf, count); 723 if (len < 0) 724 return len; 725 726 tbuf[len] = '\0'; 727 ret = kstrtoul(tbuf, 0, &val); 728 if (ret) 729 return ret; 730 731 ret = hisi_qm_get_dfx_access(qm); 732 if (ret) 733 return ret; 734 735 spin_lock_irq(&file->lock); 736 switch (file->index) { 737 case HZIP_CLEAR_ENABLE: 738 ret = clear_enable_write(qm, val); 739 if (ret) 740 goto err_input; 741 break; 742 default: 743 ret = -EINVAL; 744 goto err_input; 745 } 746 747 ret = count; 748 749 err_input: 750 spin_unlock_irq(&file->lock); 751 hisi_qm_put_dfx_access(qm); 752 return ret; 753 } 754 755 static const struct file_operations ctrl_debug_fops = { 756 .owner = THIS_MODULE, 757 .open = simple_open, 758 .read = hisi_zip_ctrl_debug_read, 759 .write = hisi_zip_ctrl_debug_write, 760 }; 761 762 static int zip_debugfs_atomic64_set(void *data, u64 val) 763 { 764 if (val) 765 return -EINVAL; 766 767 atomic64_set((atomic64_t *)data, 0); 768 769 return 0; 770 } 771 772 static int zip_debugfs_atomic64_get(void *data, u64 *val) 773 { 774 *val = atomic64_read((atomic64_t *)data); 775 776 return 0; 777 } 778 779 DEFINE_DEBUGFS_ATTRIBUTE(zip_atomic64_ops, zip_debugfs_atomic64_get, 780 zip_debugfs_atomic64_set, "%llu\n"); 781 782 static int hisi_zip_regs_show(struct seq_file *s, void *unused) 783 { 784 hisi_qm_regs_dump(s, s->private); 785 786 return 0; 787 } 788 789 DEFINE_SHOW_ATTRIBUTE(hisi_zip_regs); 790 791 static int hisi_zip_core_debug_init(struct hisi_qm *qm) 792 { 793 u32 zip_core_num, zip_comp_core_num; 794 struct device *dev = &qm->pdev->dev; 795 struct debugfs_regset32 *regset; 796 struct dentry *tmp_d; 797 char buf[HZIP_BUF_SIZE]; 798 int i; 799 800 zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); 801 zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP, 802 qm->cap_ver); 803 804 for (i = 0; i < zip_core_num; i++) { 805 if (i < zip_comp_core_num) 806 scnprintf(buf, sizeof(buf), "comp_core%d", i); 807 else 808 scnprintf(buf, sizeof(buf), "decomp_core%d", 809 i - zip_comp_core_num); 810 811 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 812 if (!regset) 813 return -ENOENT; 814 815 regset->regs = hzip_dfx_regs; 816 regset->nregs = ARRAY_SIZE(hzip_dfx_regs); 817 regset->base = qm->io_base + core_offsets[i]; 818 regset->dev = dev; 819 820 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); 821 debugfs_create_file("regs", 0444, tmp_d, regset, 822 &hisi_zip_regs_fops); 823 } 824 825 return 0; 826 } 827 828 static void hisi_zip_dfx_debug_init(struct hisi_qm *qm) 829 { 830 struct dfx_diff_registers *hzip_regs = qm->debug.acc_diff_regs; 831 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 832 struct hisi_zip_dfx *dfx = &zip->dfx; 833 struct dentry *tmp_dir; 834 void *data; 835 int i; 836 837 tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root); 838 for (i = 0; i < ARRAY_SIZE(zip_dfx_files); i++) { 839 data = (atomic64_t *)((uintptr_t)dfx + zip_dfx_files[i].offset); 840 debugfs_create_file(zip_dfx_files[i].name, 841 0644, tmp_dir, data, 842 &zip_atomic64_ops); 843 } 844 845 if (qm->fun_type == QM_HW_PF && hzip_regs) 846 debugfs_create_file("diff_regs", 0444, tmp_dir, 847 qm, &hzip_diff_regs_fops); 848 } 849 850 static int hisi_zip_ctrl_debug_init(struct hisi_qm *qm) 851 { 852 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 853 int i; 854 855 for (i = HZIP_CLEAR_ENABLE; i < HZIP_DEBUG_FILE_NUM; i++) { 856 spin_lock_init(&zip->ctrl->files[i].lock); 857 zip->ctrl->files[i].ctrl = zip->ctrl; 858 zip->ctrl->files[i].index = i; 859 860 debugfs_create_file(ctrl_debug_file_name[i], 0600, 861 qm->debug.debug_root, 862 zip->ctrl->files + i, 863 &ctrl_debug_fops); 864 } 865 866 return hisi_zip_core_debug_init(qm); 867 } 868 869 static int hisi_zip_debugfs_init(struct hisi_qm *qm) 870 { 871 struct device *dev = &qm->pdev->dev; 872 struct dentry *dev_d; 873 int ret; 874 875 dev_d = debugfs_create_dir(dev_name(dev), hzip_debugfs_root); 876 877 qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET; 878 qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN; 879 qm->debug.debug_root = dev_d; 880 ret = hisi_qm_regs_debugfs_init(qm, hzip_diff_regs, ARRAY_SIZE(hzip_diff_regs)); 881 if (ret) { 882 dev_warn(dev, "Failed to init ZIP diff regs!\n"); 883 goto debugfs_remove; 884 } 885 886 hisi_qm_debug_init(qm); 887 888 if (qm->fun_type == QM_HW_PF) { 889 ret = hisi_zip_ctrl_debug_init(qm); 890 if (ret) 891 goto failed_to_create; 892 } 893 894 hisi_zip_dfx_debug_init(qm); 895 896 return 0; 897 898 failed_to_create: 899 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs)); 900 debugfs_remove: 901 debugfs_remove_recursive(hzip_debugfs_root); 902 return ret; 903 } 904 905 /* hisi_zip_debug_regs_clear() - clear the zip debug regs */ 906 static void hisi_zip_debug_regs_clear(struct hisi_qm *qm) 907 { 908 int i, j; 909 910 /* enable register read_clear bit */ 911 writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 912 for (i = 0; i < ARRAY_SIZE(core_offsets); i++) 913 for (j = 0; j < ARRAY_SIZE(hzip_dfx_regs); j++) 914 readl(qm->io_base + core_offsets[i] + 915 hzip_dfx_regs[j].offset); 916 917 /* disable register read_clear bit */ 918 writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 919 920 hisi_qm_debug_regs_clear(qm); 921 } 922 923 static void hisi_zip_debugfs_exit(struct hisi_qm *qm) 924 { 925 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs)); 926 927 debugfs_remove_recursive(qm->debug.debug_root); 928 929 if (qm->fun_type == QM_HW_PF) { 930 hisi_zip_debug_regs_clear(qm); 931 qm->debug.curr_qm_qp_num = 0; 932 } 933 } 934 935 static int hisi_zip_show_last_regs_init(struct hisi_qm *qm) 936 { 937 int core_dfx_regs_num = ARRAY_SIZE(hzip_dump_dfx_regs); 938 int com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs); 939 struct qm_debug *debug = &qm->debug; 940 void __iomem *io_base; 941 u32 zip_core_num; 942 int i, j, idx; 943 944 zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); 945 946 debug->last_words = kcalloc(core_dfx_regs_num * zip_core_num + com_dfx_regs_num, 947 sizeof(unsigned int), GFP_KERNEL); 948 if (!debug->last_words) 949 return -ENOMEM; 950 951 for (i = 0; i < com_dfx_regs_num; i++) { 952 io_base = qm->io_base + hzip_com_dfx_regs[i].offset; 953 debug->last_words[i] = readl_relaxed(io_base); 954 } 955 956 for (i = 0; i < zip_core_num; i++) { 957 io_base = qm->io_base + core_offsets[i]; 958 for (j = 0; j < core_dfx_regs_num; j++) { 959 idx = com_dfx_regs_num + i * core_dfx_regs_num + j; 960 debug->last_words[idx] = readl_relaxed( 961 io_base + hzip_dump_dfx_regs[j].offset); 962 } 963 } 964 965 return 0; 966 } 967 968 static void hisi_zip_show_last_regs_uninit(struct hisi_qm *qm) 969 { 970 struct qm_debug *debug = &qm->debug; 971 972 if (qm->fun_type == QM_HW_VF || !debug->last_words) 973 return; 974 975 kfree(debug->last_words); 976 debug->last_words = NULL; 977 } 978 979 static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm) 980 { 981 int core_dfx_regs_num = ARRAY_SIZE(hzip_dump_dfx_regs); 982 int com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs); 983 u32 zip_core_num, zip_comp_core_num; 984 struct qm_debug *debug = &qm->debug; 985 char buf[HZIP_BUF_SIZE]; 986 void __iomem *base; 987 int i, j, idx; 988 u32 val; 989 990 if (qm->fun_type == QM_HW_VF || !debug->last_words) 991 return; 992 993 for (i = 0; i < com_dfx_regs_num; i++) { 994 val = readl_relaxed(qm->io_base + hzip_com_dfx_regs[i].offset); 995 if (debug->last_words[i] != val) 996 pci_info(qm->pdev, "com_dfx: %s \t= 0x%08x => 0x%08x\n", 997 hzip_com_dfx_regs[i].name, debug->last_words[i], val); 998 } 999 1000 zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); 1001 zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP, 1002 qm->cap_ver); 1003 for (i = 0; i < zip_core_num; i++) { 1004 if (i < zip_comp_core_num) 1005 scnprintf(buf, sizeof(buf), "Comp_core-%d", i); 1006 else 1007 scnprintf(buf, sizeof(buf), "Decomp_core-%d", 1008 i - zip_comp_core_num); 1009 base = qm->io_base + core_offsets[i]; 1010 1011 pci_info(qm->pdev, "==>%s:\n", buf); 1012 /* dump last word for dfx regs during control resetting */ 1013 for (j = 0; j < core_dfx_regs_num; j++) { 1014 idx = com_dfx_regs_num + i * core_dfx_regs_num + j; 1015 val = readl_relaxed(base + hzip_dump_dfx_regs[j].offset); 1016 if (debug->last_words[idx] != val) 1017 pci_info(qm->pdev, "%s \t= 0x%08x => 0x%08x\n", 1018 hzip_dump_dfx_regs[j].name, 1019 debug->last_words[idx], val); 1020 } 1021 } 1022 } 1023 1024 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts) 1025 { 1026 const struct hisi_zip_hw_error *err = zip_hw_error; 1027 struct device *dev = &qm->pdev->dev; 1028 u32 err_val; 1029 1030 while (err->msg) { 1031 if (err->int_msk & err_sts) { 1032 dev_err(dev, "%s [error status=0x%x] found\n", 1033 err->msg, err->int_msk); 1034 1035 if (err->int_msk & HZIP_CORE_INT_STATUS_M_ECC) { 1036 err_val = readl(qm->io_base + 1037 HZIP_CORE_SRAM_ECC_ERR_INFO); 1038 dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n", 1039 ((err_val >> 1040 HZIP_SRAM_ECC_ERR_NUM_SHIFT) & 0xFF)); 1041 } 1042 } 1043 err++; 1044 } 1045 } 1046 1047 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm) 1048 { 1049 return readl(qm->io_base + HZIP_CORE_INT_STATUS); 1050 } 1051 1052 static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 1053 { 1054 u32 nfe; 1055 1056 writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE); 1057 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 1058 writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1059 } 1060 1061 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm) 1062 { 1063 u32 val; 1064 1065 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1066 1067 writel(val & ~HZIP_AXI_SHUTDOWN_ENABLE, 1068 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1069 1070 writel(val | HZIP_AXI_SHUTDOWN_ENABLE, 1071 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1072 } 1073 1074 static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm) 1075 { 1076 u32 nfe_enb; 1077 1078 /* Disable ECC Mbit error report. */ 1079 nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1080 writel(nfe_enb & ~HZIP_CORE_INT_STATUS_M_ECC, 1081 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1082 1083 /* Inject zip ECC Mbit error to block master ooo. */ 1084 writel(HZIP_CORE_INT_STATUS_M_ECC, 1085 qm->io_base + HZIP_CORE_INT_SET); 1086 } 1087 1088 static void hisi_zip_err_info_init(struct hisi_qm *qm) 1089 { 1090 struct hisi_qm_err_info *err_info = &qm->err_info; 1091 1092 err_info->fe = HZIP_CORE_INT_RAS_FE_ENB_MASK; 1093 err_info->ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_QM_CE_MASK_CAP, qm->cap_ver); 1094 err_info->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1095 ZIP_QM_NFE_MASK_CAP, qm->cap_ver); 1096 err_info->ecc_2bits_mask = HZIP_CORE_INT_STATUS_M_ECC; 1097 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1098 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1099 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1100 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1101 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1102 ZIP_QM_RESET_MASK_CAP, qm->cap_ver); 1103 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1104 ZIP_RESET_MASK_CAP, qm->cap_ver); 1105 err_info->msi_wr_port = HZIP_WR_PORT; 1106 err_info->acpi_rst = "ZRST"; 1107 } 1108 1109 static const struct hisi_qm_err_ini hisi_zip_err_ini = { 1110 .hw_init = hisi_zip_set_user_domain_and_cache, 1111 .hw_err_enable = hisi_zip_hw_error_enable, 1112 .hw_err_disable = hisi_zip_hw_error_disable, 1113 .get_dev_hw_err_status = hisi_zip_get_hw_err_status, 1114 .clear_dev_hw_err_status = hisi_zip_clear_hw_err_status, 1115 .log_dev_hw_err = hisi_zip_log_hw_error, 1116 .open_axi_master_ooo = hisi_zip_open_axi_master_ooo, 1117 .close_axi_master_ooo = hisi_zip_close_axi_master_ooo, 1118 .open_sva_prefetch = hisi_zip_open_sva_prefetch, 1119 .close_sva_prefetch = hisi_zip_close_sva_prefetch, 1120 .show_last_dfx_regs = hisi_zip_show_last_dfx_regs, 1121 .err_info_init = hisi_zip_err_info_init, 1122 }; 1123 1124 static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip) 1125 { 1126 struct hisi_qm *qm = &hisi_zip->qm; 1127 struct hisi_zip_ctrl *ctrl; 1128 int ret; 1129 1130 ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL); 1131 if (!ctrl) 1132 return -ENOMEM; 1133 1134 hisi_zip->ctrl = ctrl; 1135 ctrl->hisi_zip = hisi_zip; 1136 qm->err_ini = &hisi_zip_err_ini; 1137 qm->err_ini->err_info_init(qm); 1138 1139 ret = hisi_zip_set_user_domain_and_cache(qm); 1140 if (ret) 1141 return ret; 1142 1143 ret = hisi_zip_set_high_perf(qm); 1144 if (ret) 1145 return ret; 1146 1147 hisi_zip_open_sva_prefetch(qm); 1148 hisi_qm_dev_err_init(qm); 1149 hisi_zip_debug_regs_clear(qm); 1150 1151 ret = hisi_zip_show_last_regs_init(qm); 1152 if (ret) 1153 pci_err(qm->pdev, "Failed to init last word regs!\n"); 1154 1155 return ret; 1156 } 1157 1158 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1159 { 1160 u64 alg_msk; 1161 int ret; 1162 1163 qm->pdev = pdev; 1164 qm->ver = pdev->revision; 1165 qm->mode = uacce_mode; 1166 qm->sqe_size = HZIP_SQE_SIZE; 1167 qm->dev_name = hisi_zip_name; 1168 1169 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_ZIP_PF) ? 1170 QM_HW_PF : QM_HW_VF; 1171 if (qm->fun_type == QM_HW_PF) { 1172 qm->qp_base = HZIP_PF_DEF_Q_BASE; 1173 qm->qp_num = pf_q_num; 1174 qm->debug.curr_qm_qp_num = pf_q_num; 1175 qm->qm_list = &zip_devices; 1176 if (pf_q_num_flag) 1177 set_bit(QM_MODULE_PARAM, &qm->misc_ctl); 1178 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { 1179 /* 1180 * have no way to get qm configure in VM in v1 hardware, 1181 * so currently force PF to uses HZIP_PF_DEF_Q_NUM, and force 1182 * to trigger only one VF in v1 hardware. 1183 * 1184 * v2 hardware has no such problem. 1185 */ 1186 qm->qp_base = HZIP_PF_DEF_Q_NUM; 1187 qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM; 1188 } 1189 1190 ret = hisi_qm_init(qm); 1191 if (ret) { 1192 pci_err(qm->pdev, "Failed to init zip qm configures!\n"); 1193 return ret; 1194 } 1195 1196 alg_msk = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DEV_ALG_BITMAP, qm->cap_ver); 1197 ret = hisi_qm_set_algs(qm, alg_msk, zip_dev_algs, ARRAY_SIZE(zip_dev_algs)); 1198 if (ret) { 1199 pci_err(qm->pdev, "Failed to set zip algs!\n"); 1200 hisi_qm_uninit(qm); 1201 } 1202 1203 return ret; 1204 } 1205 1206 static void hisi_zip_qm_uninit(struct hisi_qm *qm) 1207 { 1208 hisi_qm_uninit(qm); 1209 } 1210 1211 static int hisi_zip_probe_init(struct hisi_zip *hisi_zip) 1212 { 1213 u32 type_rate = HZIP_SHAPER_RATE_COMPRESS; 1214 struct hisi_qm *qm = &hisi_zip->qm; 1215 int ret; 1216 1217 if (qm->fun_type == QM_HW_PF) { 1218 ret = hisi_zip_pf_probe_init(hisi_zip); 1219 if (ret) 1220 return ret; 1221 /* enable shaper type 0 */ 1222 if (qm->ver >= QM_HW_V3) { 1223 type_rate |= QM_SHAPER_ENABLE; 1224 1225 /* ZIP need to enable shaper type 1 */ 1226 type_rate |= HZIP_SHAPER_RATE_DECOMPRESS << QM_SHAPER_TYPE1_OFFSET; 1227 qm->type_rate = type_rate; 1228 } 1229 } 1230 1231 return 0; 1232 } 1233 1234 static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1235 { 1236 struct hisi_zip *hisi_zip; 1237 struct hisi_qm *qm; 1238 int ret; 1239 1240 hisi_zip = devm_kzalloc(&pdev->dev, sizeof(*hisi_zip), GFP_KERNEL); 1241 if (!hisi_zip) 1242 return -ENOMEM; 1243 1244 qm = &hisi_zip->qm; 1245 1246 ret = hisi_zip_qm_init(qm, pdev); 1247 if (ret) { 1248 pci_err(pdev, "Failed to init ZIP QM (%d)!\n", ret); 1249 return ret; 1250 } 1251 1252 ret = hisi_zip_probe_init(hisi_zip); 1253 if (ret) { 1254 pci_err(pdev, "Failed to probe (%d)!\n", ret); 1255 goto err_qm_uninit; 1256 } 1257 1258 ret = hisi_qm_start(qm); 1259 if (ret) 1260 goto err_dev_err_uninit; 1261 1262 ret = hisi_zip_debugfs_init(qm); 1263 if (ret) 1264 pci_err(pdev, "failed to init debugfs (%d)!\n", ret); 1265 1266 ret = hisi_qm_alg_register(qm, &zip_devices); 1267 if (ret < 0) { 1268 pci_err(pdev, "failed to register driver to crypto!\n"); 1269 goto err_qm_stop; 1270 } 1271 1272 if (qm->uacce) { 1273 ret = uacce_register(qm->uacce); 1274 if (ret) { 1275 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 1276 goto err_qm_alg_unregister; 1277 } 1278 } 1279 1280 if (qm->fun_type == QM_HW_PF && vfs_num > 0) { 1281 ret = hisi_qm_sriov_enable(pdev, vfs_num); 1282 if (ret < 0) 1283 goto err_qm_alg_unregister; 1284 } 1285 1286 hisi_qm_pm_init(qm); 1287 1288 return 0; 1289 1290 err_qm_alg_unregister: 1291 hisi_qm_alg_unregister(qm, &zip_devices); 1292 1293 err_qm_stop: 1294 hisi_zip_debugfs_exit(qm); 1295 hisi_qm_stop(qm, QM_NORMAL); 1296 1297 err_dev_err_uninit: 1298 hisi_zip_show_last_regs_uninit(qm); 1299 hisi_qm_dev_err_uninit(qm); 1300 1301 err_qm_uninit: 1302 hisi_zip_qm_uninit(qm); 1303 1304 return ret; 1305 } 1306 1307 static void hisi_zip_remove(struct pci_dev *pdev) 1308 { 1309 struct hisi_qm *qm = pci_get_drvdata(pdev); 1310 1311 hisi_qm_pm_uninit(qm); 1312 hisi_qm_wait_task_finish(qm, &zip_devices); 1313 hisi_qm_alg_unregister(qm, &zip_devices); 1314 1315 if (qm->fun_type == QM_HW_PF && qm->vfs_num) 1316 hisi_qm_sriov_disable(pdev, true); 1317 1318 hisi_zip_debugfs_exit(qm); 1319 hisi_qm_stop(qm, QM_NORMAL); 1320 hisi_zip_show_last_regs_uninit(qm); 1321 hisi_qm_dev_err_uninit(qm); 1322 hisi_zip_qm_uninit(qm); 1323 } 1324 1325 static const struct dev_pm_ops hisi_zip_pm_ops = { 1326 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL) 1327 }; 1328 1329 static const struct pci_error_handlers hisi_zip_err_handler = { 1330 .error_detected = hisi_qm_dev_err_detected, 1331 .slot_reset = hisi_qm_dev_slot_reset, 1332 .reset_prepare = hisi_qm_reset_prepare, 1333 .reset_done = hisi_qm_reset_done, 1334 }; 1335 1336 static struct pci_driver hisi_zip_pci_driver = { 1337 .name = "hisi_zip", 1338 .id_table = hisi_zip_dev_ids, 1339 .probe = hisi_zip_probe, 1340 .remove = hisi_zip_remove, 1341 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ? 1342 hisi_qm_sriov_configure : NULL, 1343 .err_handler = &hisi_zip_err_handler, 1344 .shutdown = hisi_qm_dev_shutdown, 1345 .driver.pm = &hisi_zip_pm_ops, 1346 }; 1347 1348 struct pci_driver *hisi_zip_get_pf_driver(void) 1349 { 1350 return &hisi_zip_pci_driver; 1351 } 1352 EXPORT_SYMBOL_GPL(hisi_zip_get_pf_driver); 1353 1354 static void hisi_zip_register_debugfs(void) 1355 { 1356 if (!debugfs_initialized()) 1357 return; 1358 1359 hzip_debugfs_root = debugfs_create_dir("hisi_zip", NULL); 1360 } 1361 1362 static void hisi_zip_unregister_debugfs(void) 1363 { 1364 debugfs_remove_recursive(hzip_debugfs_root); 1365 } 1366 1367 static int __init hisi_zip_init(void) 1368 { 1369 int ret; 1370 1371 hisi_qm_init_list(&zip_devices); 1372 hisi_zip_register_debugfs(); 1373 1374 ret = pci_register_driver(&hisi_zip_pci_driver); 1375 if (ret < 0) { 1376 hisi_zip_unregister_debugfs(); 1377 pr_err("Failed to register pci driver.\n"); 1378 } 1379 1380 return ret; 1381 } 1382 1383 static void __exit hisi_zip_exit(void) 1384 { 1385 pci_unregister_driver(&hisi_zip_pci_driver); 1386 hisi_zip_unregister_debugfs(); 1387 } 1388 1389 module_init(hisi_zip_init); 1390 module_exit(hisi_zip_exit); 1391 1392 MODULE_LICENSE("GPL v2"); 1393 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>"); 1394 MODULE_DESCRIPTION("Driver for HiSilicon ZIP accelerator"); 1395