xref: /openbmc/linux/drivers/crypto/ccree/cc_host_regs.h (revision 0898782247ae533d1f4e47a06bc5d4870931b284)
14c3f9727SGilad Ben-Yossef /* SPDX-License-Identifier: GPL-2.0 */
2dcf6285dSGilad Ben-Yossef /* Copyright (C) 2012-2019 ARM Limited or its affiliates. */
34c3f9727SGilad Ben-Yossef 
44c3f9727SGilad Ben-Yossef #ifndef __CC_HOST_H__
54c3f9727SGilad Ben-Yossef #define __CC_HOST_H__
64c3f9727SGilad Ben-Yossef 
74c3f9727SGilad Ben-Yossef // --------------------------------------
84c3f9727SGilad Ben-Yossef // BLOCK: HOST_P
94c3f9727SGilad Ben-Yossef // --------------------------------------
10cadfd898SGilad Ben-Yossef 
11cadfd898SGilad Ben-Yossef 
12cadfd898SGilad Ben-Yossef /* IRR */
134c3f9727SGilad Ben-Yossef #define CC_HOST_IRR_REG_OFFSET	0xA00UL
14cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_AES_0_INT_BIT_SHIFT	0x1UL
15cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_AES_0_INT_BIT_SIZE	0x1UL
164c3f9727SGilad Ben-Yossef #define CC_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SHIFT	0x2UL
174c3f9727SGilad Ben-Yossef #define CC_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SIZE	0x1UL
18cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_AES_1_INT_BIT_SHIFT	0x3UL
19cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_AES_1_INT_BIT_SIZE	0x1UL
20cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_AES_2_INT_BIT_SHIFT	0x4UL
21cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_AES_2_INT_BIT_SIZE	0x1UL
22cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_AES_3_INT_BIT_SHIFT	0x5UL
23cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_AES_3_INT_BIT_SIZE	0x1UL
24cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_AES_4_INT_BIT_SHIFT	0x6UL
25cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_AES_4_INT_BIT_SIZE	0x1UL
26cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_AES_5_INT_BIT_SHIFT	0x7UL
27cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_AES_5_INT_BIT_SIZE	0x1UL
284c3f9727SGilad Ben-Yossef #define CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT	0x8UL
294c3f9727SGilad Ben-Yossef #define CC_HOST_IRR_AXI_ERR_INT_BIT_SIZE	0x1UL
30cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_AES_6_INT_BIT_SHIFT	0x9UL
31cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_AES_6_INT_BIT_SIZE	0x1UL
32cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_AES_7_INT_BIT_SHIFT	0xAUL
33cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_AES_7_INT_BIT_SIZE	0x1UL
344c3f9727SGilad Ben-Yossef #define CC_HOST_IRR_GPR0_BIT_SHIFT	0xBUL
354c3f9727SGilad Ben-Yossef #define CC_HOST_IRR_GPR0_BIT_SIZE	0x1UL
36cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_SM_0_INT_BIT_SHIFT	0xCUL
37cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_SM_0_INT_BIT_SIZE	0x1UL
38cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_SM_1_INT_BIT_SHIFT	0xDUL
39cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_SM_1_INT_BIT_SIZE	0x1UL
40cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_SM_2_INT_BIT_SHIFT	0xEUL
41cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_SM_2_INT_BIT_SIZE	0x1UL
42cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_SM_3_INT_BIT_SHIFT	0xFUL
43cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_SM_3_INT_BIT_SIZE	0x1UL
44cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_SM_4_INT_BIT_SHIFT	0x10UL
45cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_SM_4_INT_BIT_SIZE	0x1UL
46cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_SM_5_INT_BIT_SHIFT	0x11UL
47cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_SM_5_INT_BIT_SIZE	0x1UL
48cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_SM_6_INT_BIT_SHIFT	0x12UL
49cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_SM_6_INT_BIT_SIZE	0x1UL
504c3f9727SGilad Ben-Yossef #define CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SHIFT	0x13UL
514c3f9727SGilad Ben-Yossef #define CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SIZE	0x1UL
52cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_SM_7_INT_BIT_SHIFT	0x14UL
53cadfd898SGilad Ben-Yossef #define CC_HOST_IRR_REE_OP_ABORTED_SM_7_INT_BIT_SIZE	0x1UL
544c3f9727SGilad Ben-Yossef #define CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT	0x17UL
554c3f9727SGilad Ben-Yossef #define CC_HOST_IRR_AXIM_COMP_INT_BIT_SIZE	0x1UL
5627b3b22dSGilad Ben-Yossef #define CC_HOST_SEP_SRAM_THRESHOLD_REG_OFFSET	0xA10UL
5727b3b22dSGilad Ben-Yossef #define CC_HOST_SEP_SRAM_THRESHOLD_VALUE_BIT_SHIFT	0x0UL
5827b3b22dSGilad Ben-Yossef #define CC_HOST_SEP_SRAM_THRESHOLD_VALUE_BIT_SIZE	0xCUL
59cadfd898SGilad Ben-Yossef 
60cadfd898SGilad Ben-Yossef /* IMR */
61cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REG_OFFSET	0x0A04UL
62cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SHIFT	0x1UL
63cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SIZE	0x1UL
644c3f9727SGilad Ben-Yossef #define CC_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SHIFT	0x2UL
654c3f9727SGilad Ben-Yossef #define CC_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SIZE	0x1UL
66cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SHIFT	0x3UL
67cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SIZE	0x1UL
68cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SHIFT	0x4UL
69cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SIZE	0x1UL
70cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SHIFT	0x5UL
71cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SIZE	0x1UL
72cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SHIFT	0x6UL
73cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SIZE	0x1UL
74cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SHIFT	0x7UL
75cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SIZE	0x1UL
764c3f9727SGilad Ben-Yossef #define CC_HOST_IMR_AXI_ERR_MASK_BIT_SHIFT	0x8UL
774c3f9727SGilad Ben-Yossef #define CC_HOST_IMR_AXI_ERR_MASK_BIT_SIZE	0x1UL
78cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SHIFT	0x9UL
79cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SIZE	0x1UL
80cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SHIFT	0xAUL
81cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SIZE	0x1UL
824c3f9727SGilad Ben-Yossef #define CC_HOST_IMR_GPR0_BIT_SHIFT	0xBUL
834c3f9727SGilad Ben-Yossef #define CC_HOST_IMR_GPR0_BIT_SIZE	0x1UL
84cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SHIFT	0xCUL
85cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SIZE	0x1UL
86cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SHIFT	0xDUL
87cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SIZE	0x1UL
88cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SHIFT	0xEUL
89cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SIZE	0x1UL
90cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SHIFT	0xFUL
91cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SIZE	0x1UL
92cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SHIFT	0x10UL
93cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SIZE	0x1UL
94cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SHIFT	0x11UL
95cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SIZE	0x1UL
96cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SHIFT	0x12UL
97cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SIZE	0x1UL
984c3f9727SGilad Ben-Yossef #define CC_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SHIFT	0x13UL
994c3f9727SGilad Ben-Yossef #define CC_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SIZE	0x1UL
100cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SHIFT	0x14UL
101cadfd898SGilad Ben-Yossef #define CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SIZE	0x1UL
1024c3f9727SGilad Ben-Yossef #define CC_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SHIFT	0x17UL
1034c3f9727SGilad Ben-Yossef #define CC_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SIZE	0x1UL
104cadfd898SGilad Ben-Yossef 
105cadfd898SGilad Ben-Yossef /* ICR */
1064c3f9727SGilad Ben-Yossef #define CC_HOST_ICR_REG_OFFSET	0xA08UL
1074c3f9727SGilad Ben-Yossef #define CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SHIFT	0x2UL
1084c3f9727SGilad Ben-Yossef #define CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SIZE	0x1UL
1094c3f9727SGilad Ben-Yossef #define CC_HOST_ICR_AXI_ERR_CLEAR_BIT_SHIFT	0x8UL
1104c3f9727SGilad Ben-Yossef #define CC_HOST_ICR_AXI_ERR_CLEAR_BIT_SIZE	0x1UL
1114c3f9727SGilad Ben-Yossef #define CC_HOST_ICR_GPR_INT_CLEAR_BIT_SHIFT	0xBUL
1124c3f9727SGilad Ben-Yossef #define CC_HOST_ICR_GPR_INT_CLEAR_BIT_SIZE	0x1UL
1134c3f9727SGilad Ben-Yossef #define CC_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SHIFT	0x13UL
1144c3f9727SGilad Ben-Yossef #define CC_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SIZE	0x1UL
1154c3f9727SGilad Ben-Yossef #define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SHIFT	0x17UL
1164c3f9727SGilad Ben-Yossef #define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SIZE	0x1UL
117d84f6269SOfir Drang #define CC_NVM_IS_IDLE_REG_OFFSET       0x0A10UL
118d84f6269SOfir Drang #define CC_NVM_IS_IDLE_VALUE_BIT_SHIFT  0x0UL
119d84f6269SOfir Drang #define CC_NVM_IS_IDLE_VALUE_BIT_SIZE   0x1UL
120f98f6e21SGilad Ben-Yossef #define CC_SECURITY_DISABLED_REG_OFFSET		0x0A1CUL
121f98f6e21SGilad Ben-Yossef #define CC_SECURITY_DISABLED_VALUE_BIT_SHIFT	0x0UL
122f98f6e21SGilad Ben-Yossef #define CC_SECURITY_DISABLED_VALUE_BIT_SIZE	0x1UL
123281a58c8SGilad Ben-Yossef #define CC_HOST_SIGNATURE_712_REG_OFFSET	0xA24UL
124281a58c8SGilad Ben-Yossef #define CC_HOST_SIGNATURE_630_REG_OFFSET	0xAC8UL
1254c3f9727SGilad Ben-Yossef #define CC_HOST_SIGNATURE_VALUE_BIT_SHIFT	0x0UL
1264c3f9727SGilad Ben-Yossef #define CC_HOST_SIGNATURE_VALUE_BIT_SIZE	0x20UL
1274c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_REG_OFFSET	0xA28UL
1284c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SHIFT	0x0UL
1294c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SIZE	0x1UL
1304c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SHIFT	0x1UL
1314c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SIZE	0x1UL
1324c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SHIFT	0x2UL
1334c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SIZE	0x1UL
1344c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SHIFT	0x3UL
1354c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SIZE	0x1UL
1364c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SHIFT	0x5UL
1374c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SIZE	0x1UL
1384c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SHIFT	0x6UL
1394c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SIZE	0x3UL
1404c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SHIFT	0x9UL
1414c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SIZE	0x1UL
1424c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SHIFT	0xAUL
1434c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SIZE	0x1UL
1444c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SHIFT	0xBUL
1454c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SIZE	0x1UL
1464c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SHIFT	0xCUL
1474c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SIZE	0x1UL
1484c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SHIFT	0xDUL
1494c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SIZE	0x1UL
1504c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SHIFT	0xEUL
1514c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SIZE	0x1UL
1524c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SHIFT	0xFUL
1534c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SIZE	0x1UL
1544c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SHIFT	0x10UL
1554c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SIZE	0x1UL
1564c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SHIFT	0x11UL
1574c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SIZE	0x1UL
1584c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SHIFT	0x12UL
1594c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SIZE	0x1UL
1604c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SHIFT	0x13UL
1614c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SIZE	0x1UL
1624c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SHIFT	0x14UL
1634c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SIZE	0x1UL
1644c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SHIFT	0x15UL
1654c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SIZE	0x1UL
1664c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SHIFT	0x16UL
1674c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SIZE	0x1UL
1684c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SHIFT	0x17UL
1694c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SIZE	0x1UL
1704c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SHIFT	0x18UL
1714c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SIZE	0x1UL
1724c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SHIFT	0x19UL
1734c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SIZE	0x1UL
1744c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SHIFT	0x1AUL
1754c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SIZE	0x1UL
1764c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SHIFT	0x1BUL
1774c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SIZE	0x1UL
1784c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SHIFT	0x1CUL
1794c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SIZE	0x1UL
1804c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SHIFT	0x1DUL
1814c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SIZE	0x1UL
1824c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SHIFT	0x1EUL
1834c3f9727SGilad Ben-Yossef #define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SIZE	0x1UL
184281a58c8SGilad Ben-Yossef #define CC_HOST_VERSION_712_REG_OFFSET	0xA40UL
185281a58c8SGilad Ben-Yossef #define CC_HOST_VERSION_630_REG_OFFSET	0xAD8UL
1864c3f9727SGilad Ben-Yossef #define CC_HOST_VERSION_VALUE_BIT_SHIFT	0x0UL
1874c3f9727SGilad Ben-Yossef #define CC_HOST_VERSION_VALUE_BIT_SIZE	0x20UL
1884c3f9727SGilad Ben-Yossef #define CC_HOST_KFDE0_VALID_REG_OFFSET	0xA60UL
1894c3f9727SGilad Ben-Yossef #define CC_HOST_KFDE0_VALID_VALUE_BIT_SHIFT	0x0UL
1904c3f9727SGilad Ben-Yossef #define CC_HOST_KFDE0_VALID_VALUE_BIT_SIZE	0x1UL
1914c3f9727SGilad Ben-Yossef #define CC_HOST_KFDE1_VALID_REG_OFFSET	0xA64UL
1924c3f9727SGilad Ben-Yossef #define CC_HOST_KFDE1_VALID_VALUE_BIT_SHIFT	0x0UL
1934c3f9727SGilad Ben-Yossef #define CC_HOST_KFDE1_VALID_VALUE_BIT_SIZE	0x1UL
1944c3f9727SGilad Ben-Yossef #define CC_HOST_KFDE2_VALID_REG_OFFSET	0xA68UL
1954c3f9727SGilad Ben-Yossef #define CC_HOST_KFDE2_VALID_VALUE_BIT_SHIFT	0x0UL
1964c3f9727SGilad Ben-Yossef #define CC_HOST_KFDE2_VALID_VALUE_BIT_SIZE	0x1UL
1974c3f9727SGilad Ben-Yossef #define CC_HOST_KFDE3_VALID_REG_OFFSET	0xA6CUL
1984c3f9727SGilad Ben-Yossef #define CC_HOST_KFDE3_VALID_VALUE_BIT_SHIFT	0x0UL
1994c3f9727SGilad Ben-Yossef #define CC_HOST_KFDE3_VALID_VALUE_BIT_SIZE	0x1UL
2004c3f9727SGilad Ben-Yossef #define CC_HOST_GPR0_REG_OFFSET	0xA70UL
2014c3f9727SGilad Ben-Yossef #define CC_HOST_GPR0_VALUE_BIT_SHIFT	0x0UL
2024c3f9727SGilad Ben-Yossef #define CC_HOST_GPR0_VALUE_BIT_SIZE	0x20UL
2034c3f9727SGilad Ben-Yossef #define CC_GPR_HOST_REG_OFFSET	0xA74UL
2044c3f9727SGilad Ben-Yossef #define CC_GPR_HOST_VALUE_BIT_SHIFT	0x0UL
2054c3f9727SGilad Ben-Yossef #define CC_GPR_HOST_VALUE_BIT_SIZE	0x20UL
2064c3f9727SGilad Ben-Yossef #define CC_HOST_POWER_DOWN_EN_REG_OFFSET	0xA78UL
2074c3f9727SGilad Ben-Yossef #define CC_HOST_POWER_DOWN_EN_VALUE_BIT_SHIFT	0x0UL
2084c3f9727SGilad Ben-Yossef #define CC_HOST_POWER_DOWN_EN_VALUE_BIT_SIZE	0x1UL
209*303f99acSGilad Ben-Yossef #define CC_HOST_REMOVE_INPUT_PINS_REG_OFFSET	0x0A7CUL
210*303f99acSGilad Ben-Yossef #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_ENGINE_BIT_SHIFT	0x0UL
211*303f99acSGilad Ben-Yossef #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_ENGINE_BIT_SIZE	0x1UL
212*303f99acSGilad Ben-Yossef #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_MAC_ENGINE_BIT_SHIFT	0x1UL
213*303f99acSGilad Ben-Yossef #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_MAC_ENGINE_BIT_SIZE	0x1UL
214*303f99acSGilad Ben-Yossef #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_GHASH_ENGINE_BIT_SHIFT	0x2UL
215*303f99acSGilad Ben-Yossef #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_GHASH_ENGINE_BIT_SIZE	0x1UL
216*303f99acSGilad Ben-Yossef #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_DES_ENGINE_BIT_SHIFT	0x3UL
217*303f99acSGilad Ben-Yossef #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_DES_ENGINE_BIT_SIZE	0x1UL
218*303f99acSGilad Ben-Yossef #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_HASH_ENGINE_BIT_SHIFT	0x4UL
219*303f99acSGilad Ben-Yossef #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_HASH_ENGINE_BIT_SIZE	0x1UL
220*303f99acSGilad Ben-Yossef #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM3_ENGINE_BIT_SHIFT	0x5UL
221*303f99acSGilad Ben-Yossef #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM3_ENGINE_BIT_SIZE	0x1UL
222*303f99acSGilad Ben-Yossef #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM4_ENGINE_BIT_SHIFT	0x6UL
223*303f99acSGilad Ben-Yossef #define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM4_ENGINE_BIT_SIZE	0x1UL
224*303f99acSGilad Ben-Yossef #define CC_HOST_REMOVE_INPUT_PINS_OTP_DISCONNECTED_BIT_SHIFT	0x7UL
225*303f99acSGilad Ben-Yossef #define CC_HOST_REMOVE_INPUT_PINS_OTP_DISCONNECTED_BIT_SIZE	0x1UL
2264c3f9727SGilad Ben-Yossef // --------------------------------------
227dcf6285dSGilad Ben-Yossef // BLOCK: ID_REGISTERS
228dcf6285dSGilad Ben-Yossef // --------------------------------------
229dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_4_REG_OFFSET	0x0FD0UL
230dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_4_VALUE_BIT_SHIFT	0x0UL
231dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_4_VALUE_BIT_SIZE	0x4UL
232dcf6285dSGilad Ben-Yossef #define CC_PIDRESERVED0_REG_OFFSET	0x0FD4UL
233dcf6285dSGilad Ben-Yossef #define CC_PIDRESERVED1_REG_OFFSET	0x0FD8UL
234dcf6285dSGilad Ben-Yossef #define CC_PIDRESERVED2_REG_OFFSET	0x0FDCUL
235dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_0_REG_OFFSET	0x0FE0UL
236dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_0_VALUE_BIT_SHIFT	0x0UL
237dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_0_VALUE_BIT_SIZE	0x8UL
238dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_1_REG_OFFSET	0x0FE4UL
239dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_1_PART_1_BIT_SHIFT	0x0UL
240dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_1_PART_1_BIT_SIZE	0x4UL
241dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_1_DES_0_JEP106_BIT_SHIFT	0x4UL
242dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_1_DES_0_JEP106_BIT_SIZE	0x4UL
243dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_2_REG_OFFSET	0x0FE8UL
244dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_2_DES_1_JEP106_BIT_SHIFT	0x0UL
245dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_2_DES_1_JEP106_BIT_SIZE	0x3UL
246dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_2_JEDEC_BIT_SHIFT	0x3UL
247dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_2_JEDEC_BIT_SIZE	0x1UL
248dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_2_REVISION_BIT_SHIFT	0x4UL
249dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_2_REVISION_BIT_SIZE	0x4UL
250dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_3_REG_OFFSET	0x0FECUL
251dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_3_CMOD_BIT_SHIFT	0x0UL
252dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_3_CMOD_BIT_SIZE	0x4UL
253dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_3_REVAND_BIT_SHIFT	0x4UL
254dcf6285dSGilad Ben-Yossef #define CC_PERIPHERAL_ID_3_REVAND_BIT_SIZE	0x4UL
255dcf6285dSGilad Ben-Yossef #define CC_COMPONENT_ID_0_REG_OFFSET	0x0FF0UL
256dcf6285dSGilad Ben-Yossef #define CC_COMPONENT_ID_0_VALUE_BIT_SHIFT	0x0UL
257dcf6285dSGilad Ben-Yossef #define CC_COMPONENT_ID_0_VALUE_BIT_SIZE	0x8UL
258dcf6285dSGilad Ben-Yossef #define CC_COMPONENT_ID_1_REG_OFFSET	0x0FF4UL
259dcf6285dSGilad Ben-Yossef #define CC_COMPONENT_ID_1_PRMBL_1_BIT_SHIFT	0x0UL
260dcf6285dSGilad Ben-Yossef #define CC_COMPONENT_ID_1_PRMBL_1_BIT_SIZE	0x4UL
261dcf6285dSGilad Ben-Yossef #define CC_COMPONENT_ID_1_CLASS_BIT_SHIFT	0x4UL
262dcf6285dSGilad Ben-Yossef #define CC_COMPONENT_ID_1_CLASS_BIT_SIZE	0x4UL
263dcf6285dSGilad Ben-Yossef #define CC_COMPONENT_ID_2_REG_OFFSET	0x0FF8UL
264dcf6285dSGilad Ben-Yossef #define CC_COMPONENT_ID_2_VALUE_BIT_SHIFT	0x0UL
265dcf6285dSGilad Ben-Yossef #define CC_COMPONENT_ID_2_VALUE_BIT_SIZE	0x8UL
266dcf6285dSGilad Ben-Yossef #define CC_COMPONENT_ID_3_REG_OFFSET	0x0FFCUL
267dcf6285dSGilad Ben-Yossef #define CC_COMPONENT_ID_3_VALUE_BIT_SHIFT	0x0UL
268dcf6285dSGilad Ben-Yossef #define CC_COMPONENT_ID_3_VALUE_BIT_SIZE	0x8UL
269dcf6285dSGilad Ben-Yossef // --------------------------------------
2704c3f9727SGilad Ben-Yossef // BLOCK: HOST_SRAM
2714c3f9727SGilad Ben-Yossef // --------------------------------------
2724c3f9727SGilad Ben-Yossef #define CC_SRAM_DATA_REG_OFFSET	0xF00UL
2734c3f9727SGilad Ben-Yossef #define CC_SRAM_DATA_VALUE_BIT_SHIFT	0x0UL
2744c3f9727SGilad Ben-Yossef #define CC_SRAM_DATA_VALUE_BIT_SIZE	0x20UL
2754c3f9727SGilad Ben-Yossef #define CC_SRAM_ADDR_REG_OFFSET	0xF04UL
2764c3f9727SGilad Ben-Yossef #define CC_SRAM_ADDR_VALUE_BIT_SHIFT	0x0UL
2774c3f9727SGilad Ben-Yossef #define CC_SRAM_ADDR_VALUE_BIT_SIZE	0xFUL
2784c3f9727SGilad Ben-Yossef #define CC_SRAM_DATA_READY_REG_OFFSET	0xF08UL
2794c3f9727SGilad Ben-Yossef #define CC_SRAM_DATA_READY_VALUE_BIT_SHIFT	0x0UL
2804c3f9727SGilad Ben-Yossef #define CC_SRAM_DATA_READY_VALUE_BIT_SIZE	0x1UL
2814c3f9727SGilad Ben-Yossef 
2824c3f9727SGilad Ben-Yossef #endif //__CC_HOST_H__
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