133960accSRijo Thomas /* SPDX-License-Identifier: MIT */ 233960accSRijo Thomas /* 3*00aa6e65SRijo Thomas * Copyright (C) 2019,2021 Advanced Micro Devices, Inc. 433960accSRijo Thomas * 533960accSRijo Thomas * Author: Rijo Thomas <Rijo-john.Thomas@amd.com> 633960accSRijo Thomas * Author: Devaraj Rangasamy <Devaraj.Rangasamy@amd.com> 733960accSRijo Thomas * 833960accSRijo Thomas */ 933960accSRijo Thomas 1033960accSRijo Thomas /* This file describes the TEE communication interface between host and AMD 1133960accSRijo Thomas * Secure Processor 1233960accSRijo Thomas */ 1333960accSRijo Thomas 1433960accSRijo Thomas #ifndef __TEE_DEV_H__ 1533960accSRijo Thomas #define __TEE_DEV_H__ 1633960accSRijo Thomas 1733960accSRijo Thomas #include <linux/device.h> 1833960accSRijo Thomas #include <linux/mutex.h> 1933960accSRijo Thomas 2033960accSRijo Thomas #define TEE_DEFAULT_TIMEOUT 10 21*00aa6e65SRijo Thomas #define MAX_BUFFER_SIZE 988 2233960accSRijo Thomas 2333960accSRijo Thomas /** 2433960accSRijo Thomas * enum tee_ring_cmd_id - TEE interface commands for ring buffer configuration 2533960accSRijo Thomas * @TEE_RING_INIT_CMD: Initialize ring buffer 2633960accSRijo Thomas * @TEE_RING_DESTROY_CMD: Destroy ring buffer 2733960accSRijo Thomas * @TEE_RING_MAX_CMD: Maximum command id 2833960accSRijo Thomas */ 2933960accSRijo Thomas enum tee_ring_cmd_id { 3033960accSRijo Thomas TEE_RING_INIT_CMD = 0x00010000, 3133960accSRijo Thomas TEE_RING_DESTROY_CMD = 0x00020000, 3233960accSRijo Thomas TEE_RING_MAX_CMD = 0x000F0000, 3333960accSRijo Thomas }; 3433960accSRijo Thomas 3533960accSRijo Thomas /** 3633960accSRijo Thomas * struct tee_init_ring_cmd - Command to init TEE ring buffer 3733960accSRijo Thomas * @low_addr: bits [31:0] of the physical address of ring buffer 3833960accSRijo Thomas * @hi_addr: bits [63:32] of the physical address of ring buffer 3933960accSRijo Thomas * @size: size of ring buffer in bytes 4033960accSRijo Thomas */ 4133960accSRijo Thomas struct tee_init_ring_cmd { 4233960accSRijo Thomas u32 low_addr; 4333960accSRijo Thomas u32 hi_addr; 4433960accSRijo Thomas u32 size; 4533960accSRijo Thomas }; 4633960accSRijo Thomas 4733960accSRijo Thomas #define MAX_RING_BUFFER_ENTRIES 32 4833960accSRijo Thomas 4933960accSRijo Thomas /** 5033960accSRijo Thomas * struct ring_buf_manager - Helper structure to manage ring buffer. 5133960accSRijo Thomas * @ring_start: starting address of ring buffer 5233960accSRijo Thomas * @ring_size: size of ring buffer in bytes 5333960accSRijo Thomas * @ring_pa: physical address of ring buffer 5433960accSRijo Thomas * @wptr: index to the last written entry in ring buffer 5533960accSRijo Thomas */ 5633960accSRijo Thomas struct ring_buf_manager { 57632b0b53SRijo Thomas struct mutex mutex; /* synchronizes access to ring buffer */ 5833960accSRijo Thomas void *ring_start; 5933960accSRijo Thomas u32 ring_size; 6033960accSRijo Thomas phys_addr_t ring_pa; 6133960accSRijo Thomas u32 wptr; 6233960accSRijo Thomas }; 6333960accSRijo Thomas 6433960accSRijo Thomas struct psp_tee_device { 6533960accSRijo Thomas struct device *dev; 6633960accSRijo Thomas struct psp_device *psp; 6733960accSRijo Thomas void __iomem *io_regs; 6833960accSRijo Thomas struct tee_vdata *vdata; 6933960accSRijo Thomas struct ring_buf_manager rb_mgr; 7033960accSRijo Thomas }; 7133960accSRijo Thomas 7233960accSRijo Thomas /** 7333960accSRijo Thomas * enum tee_cmd_state - TEE command states for the ring buffer interface 7433960accSRijo Thomas * @TEE_CMD_STATE_INIT: initial state of command when sent from host 7533960accSRijo Thomas * @TEE_CMD_STATE_PROCESS: command being processed by TEE environment 7633960accSRijo Thomas * @TEE_CMD_STATE_COMPLETED: command processing completed 7733960accSRijo Thomas */ 7833960accSRijo Thomas enum tee_cmd_state { 7933960accSRijo Thomas TEE_CMD_STATE_INIT, 8033960accSRijo Thomas TEE_CMD_STATE_PROCESS, 8133960accSRijo Thomas TEE_CMD_STATE_COMPLETED, 8233960accSRijo Thomas }; 8333960accSRijo Thomas 8433960accSRijo Thomas /** 85*00aa6e65SRijo Thomas * enum cmd_resp_state - TEE command's response status maintained by driver 86*00aa6e65SRijo Thomas * @CMD_RESPONSE_INVALID: initial state when no command is written to ring 87*00aa6e65SRijo Thomas * @CMD_WAITING_FOR_RESPONSE: driver waiting for response from TEE 88*00aa6e65SRijo Thomas * @CMD_RESPONSE_TIMEDOUT: failed to get response from TEE 89*00aa6e65SRijo Thomas * @CMD_RESPONSE_COPIED: driver has copied response from TEE 90*00aa6e65SRijo Thomas */ 91*00aa6e65SRijo Thomas enum cmd_resp_state { 92*00aa6e65SRijo Thomas CMD_RESPONSE_INVALID, 93*00aa6e65SRijo Thomas CMD_WAITING_FOR_RESPONSE, 94*00aa6e65SRijo Thomas CMD_RESPONSE_TIMEDOUT, 95*00aa6e65SRijo Thomas CMD_RESPONSE_COPIED, 96*00aa6e65SRijo Thomas }; 97*00aa6e65SRijo Thomas 98*00aa6e65SRijo Thomas /** 9933960accSRijo Thomas * struct tee_ring_cmd - Structure of the command buffer in TEE ring 10033960accSRijo Thomas * @cmd_id: refers to &enum tee_cmd_id. Command id for the ring buffer 10133960accSRijo Thomas * interface 10233960accSRijo Thomas * @cmd_state: refers to &enum tee_cmd_state 10333960accSRijo Thomas * @status: status of TEE command execution 10433960accSRijo Thomas * @res0: reserved region 10533960accSRijo Thomas * @pdata: private data (currently unused) 10633960accSRijo Thomas * @res1: reserved region 10733960accSRijo Thomas * @buf: TEE command specific buffer 108*00aa6e65SRijo Thomas * @flag: refers to &enum cmd_resp_state 10933960accSRijo Thomas */ 11033960accSRijo Thomas struct tee_ring_cmd { 11133960accSRijo Thomas u32 cmd_id; 11233960accSRijo Thomas u32 cmd_state; 11333960accSRijo Thomas u32 status; 11433960accSRijo Thomas u32 res0[1]; 11533960accSRijo Thomas u64 pdata; 11633960accSRijo Thomas u32 res1[2]; 11733960accSRijo Thomas u8 buf[MAX_BUFFER_SIZE]; 118*00aa6e65SRijo Thomas u32 flag; 11933960accSRijo Thomas 12033960accSRijo Thomas /* Total size: 1024 bytes */ 12133960accSRijo Thomas } __packed; 12233960accSRijo Thomas 12333960accSRijo Thomas int tee_dev_init(struct psp_device *psp); 12433960accSRijo Thomas void tee_dev_destroy(struct psp_device *psp); 12533960accSRijo Thomas 12633960accSRijo Thomas #endif /* __TEE_DEV_H__ */ 127