1 /* 2 * AMD Cryptographic Coprocessor (CCP) driver 3 * 4 * Copyright (C) 2013,2016 Advanced Micro Devices, Inc. 5 * 6 * Author: Tom Lendacky <thomas.lendacky@amd.com> 7 * Author: Gary R Hook <gary.hook@amd.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #ifndef __CCP_DEV_H__ 15 #define __CCP_DEV_H__ 16 17 #include <linux/device.h> 18 #include <linux/pci.h> 19 #include <linux/spinlock.h> 20 #include <linux/mutex.h> 21 #include <linux/list.h> 22 #include <linux/wait.h> 23 #include <linux/dmapool.h> 24 #include <linux/hw_random.h> 25 #include <linux/bitops.h> 26 #include <linux/interrupt.h> 27 #include <linux/irqreturn.h> 28 #include <linux/dmaengine.h> 29 30 #define MAX_CCP_NAME_LEN 16 31 #define MAX_DMAPOOL_NAME_LEN 32 32 33 #define MAX_HW_QUEUES 5 34 #define MAX_CMD_QLEN 100 35 36 #define TRNG_RETRIES 10 37 38 #define CACHE_NONE 0x00 39 #define CACHE_WB_NO_ALLOC 0xb7 40 41 /****** Register Mappings ******/ 42 #define Q_MASK_REG 0x000 43 #define TRNG_OUT_REG 0x00c 44 #define IRQ_MASK_REG 0x040 45 #define IRQ_STATUS_REG 0x200 46 47 #define DEL_CMD_Q_JOB 0x124 48 #define DEL_Q_ACTIVE 0x00000200 49 #define DEL_Q_ID_SHIFT 6 50 51 #define CMD_REQ0 0x180 52 #define CMD_REQ_INCR 0x04 53 54 #define CMD_Q_STATUS_BASE 0x210 55 #define CMD_Q_INT_STATUS_BASE 0x214 56 #define CMD_Q_STATUS_INCR 0x20 57 58 #define CMD_Q_CACHE_BASE 0x228 59 #define CMD_Q_CACHE_INC 0x20 60 61 #define CMD_Q_ERROR(__qs) ((__qs) & 0x0000003f) 62 #define CMD_Q_DEPTH(__qs) (((__qs) >> 12) & 0x0000000f) 63 64 /****** REQ0 Related Values ******/ 65 #define REQ0_WAIT_FOR_WRITE 0x00000004 66 #define REQ0_INT_ON_COMPLETE 0x00000002 67 #define REQ0_STOP_ON_COMPLETE 0x00000001 68 69 #define REQ0_CMD_Q_SHIFT 9 70 #define REQ0_JOBID_SHIFT 3 71 72 /****** REQ1 Related Values ******/ 73 #define REQ1_PROTECT_SHIFT 27 74 #define REQ1_ENGINE_SHIFT 23 75 #define REQ1_KEY_KSB_SHIFT 2 76 77 #define REQ1_EOM 0x00000002 78 #define REQ1_INIT 0x00000001 79 80 /* AES Related Values */ 81 #define REQ1_AES_TYPE_SHIFT 21 82 #define REQ1_AES_MODE_SHIFT 18 83 #define REQ1_AES_ACTION_SHIFT 17 84 #define REQ1_AES_CFB_SIZE_SHIFT 10 85 86 /* XTS-AES Related Values */ 87 #define REQ1_XTS_AES_SIZE_SHIFT 10 88 89 /* SHA Related Values */ 90 #define REQ1_SHA_TYPE_SHIFT 21 91 92 /* RSA Related Values */ 93 #define REQ1_RSA_MOD_SIZE_SHIFT 10 94 95 /* Pass-Through Related Values */ 96 #define REQ1_PT_BW_SHIFT 12 97 #define REQ1_PT_BS_SHIFT 10 98 99 /* ECC Related Values */ 100 #define REQ1_ECC_AFFINE_CONVERT 0x00200000 101 #define REQ1_ECC_FUNCTION_SHIFT 18 102 103 /****** REQ4 Related Values ******/ 104 #define REQ4_KSB_SHIFT 18 105 #define REQ4_MEMTYPE_SHIFT 16 106 107 /****** REQ6 Related Values ******/ 108 #define REQ6_MEMTYPE_SHIFT 16 109 110 /****** Key Storage Block ******/ 111 #define KSB_START 77 112 #define KSB_END 127 113 #define KSB_COUNT (KSB_END - KSB_START + 1) 114 #define CCP_KSB_BITS 256 115 #define CCP_KSB_BYTES 32 116 117 #define CCP_JOBID_MASK 0x0000003f 118 119 #define CCP_DMAPOOL_MAX_SIZE 64 120 #define CCP_DMAPOOL_ALIGN BIT(5) 121 122 #define CCP_REVERSE_BUF_SIZE 64 123 124 #define CCP_AES_KEY_KSB_COUNT 1 125 #define CCP_AES_CTX_KSB_COUNT 1 126 127 #define CCP_XTS_AES_KEY_KSB_COUNT 1 128 #define CCP_XTS_AES_CTX_KSB_COUNT 1 129 130 #define CCP_SHA_KSB_COUNT 1 131 132 #define CCP_RSA_MAX_WIDTH 4096 133 134 #define CCP_PASSTHRU_BLOCKSIZE 256 135 #define CCP_PASSTHRU_MASKSIZE 32 136 #define CCP_PASSTHRU_KSB_COUNT 1 137 138 #define CCP_ECC_MODULUS_BYTES 48 /* 384-bits */ 139 #define CCP_ECC_MAX_OPERANDS 6 140 #define CCP_ECC_MAX_OUTPUTS 3 141 #define CCP_ECC_SRC_BUF_SIZE 448 142 #define CCP_ECC_DST_BUF_SIZE 192 143 #define CCP_ECC_OPERAND_SIZE 64 144 #define CCP_ECC_OUTPUT_SIZE 64 145 #define CCP_ECC_RESULT_OFFSET 60 146 #define CCP_ECC_RESULT_SUCCESS 0x0001 147 148 struct ccp_op; 149 150 /* Structure for computation functions that are device-specific */ 151 struct ccp_actions { 152 int (*aes)(struct ccp_op *); 153 int (*xts_aes)(struct ccp_op *); 154 int (*sha)(struct ccp_op *); 155 int (*rsa)(struct ccp_op *); 156 int (*passthru)(struct ccp_op *); 157 int (*ecc)(struct ccp_op *); 158 int (*init)(struct ccp_device *); 159 void (*destroy)(struct ccp_device *); 160 irqreturn_t (*irqhandler)(int, void *); 161 }; 162 163 /* Structure to hold CCP version-specific values */ 164 struct ccp_vdata { 165 unsigned int version; 166 const struct ccp_actions *perform; 167 const unsigned int bar; 168 const unsigned int offset; 169 }; 170 171 extern struct ccp_vdata ccpv3; 172 173 struct ccp_device; 174 struct ccp_cmd; 175 176 struct ccp_dma_cmd { 177 struct list_head entry; 178 179 struct ccp_cmd ccp_cmd; 180 }; 181 182 struct ccp_dma_desc { 183 struct list_head entry; 184 185 struct ccp_device *ccp; 186 187 struct list_head pending; 188 struct list_head active; 189 190 enum dma_status status; 191 struct dma_async_tx_descriptor tx_desc; 192 size_t len; 193 }; 194 195 struct ccp_dma_chan { 196 struct ccp_device *ccp; 197 198 spinlock_t lock; 199 struct list_head pending; 200 struct list_head active; 201 struct list_head complete; 202 203 struct tasklet_struct cleanup_tasklet; 204 205 enum dma_status status; 206 struct dma_chan dma_chan; 207 }; 208 209 struct ccp_cmd_queue { 210 struct ccp_device *ccp; 211 212 /* Queue identifier */ 213 u32 id; 214 215 /* Queue dma pool */ 216 struct dma_pool *dma_pool; 217 218 /* Queue reserved KSB regions */ 219 u32 ksb_key; 220 u32 ksb_ctx; 221 222 /* Queue processing thread */ 223 struct task_struct *kthread; 224 unsigned int active; 225 unsigned int suspended; 226 227 /* Number of free command slots available */ 228 unsigned int free_slots; 229 230 /* Interrupt masks */ 231 u32 int_ok; 232 u32 int_err; 233 234 /* Register addresses for queue */ 235 void __iomem *reg_status; 236 void __iomem *reg_int_status; 237 238 /* Status values from job */ 239 u32 int_status; 240 u32 q_status; 241 u32 q_int_status; 242 u32 cmd_error; 243 244 /* Interrupt wait queue */ 245 wait_queue_head_t int_queue; 246 unsigned int int_rcvd; 247 } ____cacheline_aligned; 248 249 struct ccp_device { 250 struct list_head entry; 251 252 struct ccp_vdata *vdata; 253 unsigned int ord; 254 char name[MAX_CCP_NAME_LEN]; 255 char rngname[MAX_CCP_NAME_LEN]; 256 257 struct device *dev; 258 259 /* Bus specific device information 260 */ 261 void *dev_specific; 262 int (*get_irq)(struct ccp_device *ccp); 263 void (*free_irq)(struct ccp_device *ccp); 264 unsigned int irq; 265 266 /* I/O area used for device communication. The register mapping 267 * starts at an offset into the mapped bar. 268 * The CMD_REQx registers and the Delete_Cmd_Queue_Job register 269 * need to be protected while a command queue thread is accessing 270 * them. 271 */ 272 struct mutex req_mutex ____cacheline_aligned; 273 void __iomem *io_map; 274 void __iomem *io_regs; 275 276 /* Master lists that all cmds are queued on. Because there can be 277 * more than one CCP command queue that can process a cmd a separate 278 * backlog list is neeeded so that the backlog completion call 279 * completes before the cmd is available for execution. 280 */ 281 spinlock_t cmd_lock ____cacheline_aligned; 282 unsigned int cmd_count; 283 struct list_head cmd; 284 struct list_head backlog; 285 286 /* The command queues. These represent the queues available on the 287 * CCP that are available for processing cmds 288 */ 289 struct ccp_cmd_queue cmd_q[MAX_HW_QUEUES]; 290 unsigned int cmd_q_count; 291 292 /* Support for the CCP True RNG 293 */ 294 struct hwrng hwrng; 295 unsigned int hwrng_retries; 296 297 /* Support for the CCP DMA capabilities 298 */ 299 struct dma_device dma_dev; 300 struct ccp_dma_chan *ccp_dma_chan; 301 struct kmem_cache *dma_cmd_cache; 302 struct kmem_cache *dma_desc_cache; 303 304 /* A counter used to generate job-ids for cmds submitted to the CCP 305 */ 306 atomic_t current_id ____cacheline_aligned; 307 308 /* The CCP uses key storage blocks (KSB) to maintain context for certain 309 * operations. To prevent multiple cmds from using the same KSB range 310 * a command queue reserves a KSB range for the duration of the cmd. 311 * Each queue, will however, reserve 2 KSB blocks for operations that 312 * only require single KSB entries (eg. AES context/iv and key) in order 313 * to avoid allocation contention. This will reserve at most 10 KSB 314 * entries, leaving 40 KSB entries available for dynamic allocation. 315 */ 316 struct mutex ksb_mutex ____cacheline_aligned; 317 DECLARE_BITMAP(ksb, KSB_COUNT); 318 wait_queue_head_t ksb_queue; 319 unsigned int ksb_avail; 320 unsigned int ksb_count; 321 u32 ksb_start; 322 323 /* Suspend support */ 324 unsigned int suspending; 325 wait_queue_head_t suspend_queue; 326 327 /* DMA caching attribute support */ 328 unsigned int axcache; 329 }; 330 331 enum ccp_memtype { 332 CCP_MEMTYPE_SYSTEM = 0, 333 CCP_MEMTYPE_KSB, 334 CCP_MEMTYPE_LOCAL, 335 CCP_MEMTYPE__LAST, 336 }; 337 338 struct ccp_dma_info { 339 dma_addr_t address; 340 unsigned int offset; 341 unsigned int length; 342 enum dma_data_direction dir; 343 }; 344 345 struct ccp_dm_workarea { 346 struct device *dev; 347 struct dma_pool *dma_pool; 348 unsigned int length; 349 350 u8 *address; 351 struct ccp_dma_info dma; 352 }; 353 354 struct ccp_sg_workarea { 355 struct scatterlist *sg; 356 int nents; 357 358 struct scatterlist *dma_sg; 359 struct device *dma_dev; 360 unsigned int dma_count; 361 enum dma_data_direction dma_dir; 362 363 unsigned int sg_used; 364 365 u64 bytes_left; 366 }; 367 368 struct ccp_data { 369 struct ccp_sg_workarea sg_wa; 370 struct ccp_dm_workarea dm_wa; 371 }; 372 373 struct ccp_mem { 374 enum ccp_memtype type; 375 union { 376 struct ccp_dma_info dma; 377 u32 ksb; 378 } u; 379 }; 380 381 struct ccp_aes_op { 382 enum ccp_aes_type type; 383 enum ccp_aes_mode mode; 384 enum ccp_aes_action action; 385 }; 386 387 struct ccp_xts_aes_op { 388 enum ccp_aes_action action; 389 enum ccp_xts_aes_unit_size unit_size; 390 }; 391 392 struct ccp_sha_op { 393 enum ccp_sha_type type; 394 u64 msg_bits; 395 }; 396 397 struct ccp_rsa_op { 398 u32 mod_size; 399 u32 input_len; 400 }; 401 402 struct ccp_passthru_op { 403 enum ccp_passthru_bitwise bit_mod; 404 enum ccp_passthru_byteswap byte_swap; 405 }; 406 407 struct ccp_ecc_op { 408 enum ccp_ecc_function function; 409 }; 410 411 struct ccp_op { 412 struct ccp_cmd_queue *cmd_q; 413 414 u32 jobid; 415 u32 ioc; 416 u32 soc; 417 u32 ksb_key; 418 u32 ksb_ctx; 419 u32 init; 420 u32 eom; 421 422 struct ccp_mem src; 423 struct ccp_mem dst; 424 425 union { 426 struct ccp_aes_op aes; 427 struct ccp_xts_aes_op xts; 428 struct ccp_sha_op sha; 429 struct ccp_rsa_op rsa; 430 struct ccp_passthru_op passthru; 431 struct ccp_ecc_op ecc; 432 } u; 433 }; 434 435 static inline u32 ccp_addr_lo(struct ccp_dma_info *info) 436 { 437 return lower_32_bits(info->address + info->offset); 438 } 439 440 static inline u32 ccp_addr_hi(struct ccp_dma_info *info) 441 { 442 return upper_32_bits(info->address + info->offset) & 0x0000ffff; 443 } 444 445 int ccp_pci_init(void); 446 void ccp_pci_exit(void); 447 448 int ccp_platform_init(void); 449 void ccp_platform_exit(void); 450 451 void ccp_add_device(struct ccp_device *ccp); 452 void ccp_del_device(struct ccp_device *ccp); 453 454 struct ccp_device *ccp_alloc_struct(struct device *dev); 455 bool ccp_queues_suspended(struct ccp_device *ccp); 456 int ccp_cmd_queue_thread(void *data); 457 458 int ccp_run_cmd(struct ccp_cmd_queue *cmd_q, struct ccp_cmd *cmd); 459 460 int ccp_dmaengine_register(struct ccp_device *ccp); 461 void ccp_dmaengine_unregister(struct ccp_device *ccp); 462 463 #endif 464