1*9e2c7d99SGeorge Cherian /* 2*9e2c7d99SGeorge Cherian * Copyright (C) 2016 Cavium, Inc. 3*9e2c7d99SGeorge Cherian * 4*9e2c7d99SGeorge Cherian * This program is free software; you can redistribute it and/or modify it 5*9e2c7d99SGeorge Cherian * under the terms of version 2 of the GNU General Public License 6*9e2c7d99SGeorge Cherian * as published by the Free Software Foundation. 7*9e2c7d99SGeorge Cherian */ 8*9e2c7d99SGeorge Cherian 9*9e2c7d99SGeorge Cherian #ifndef __CPTPF_H 10*9e2c7d99SGeorge Cherian #define __CPTPF_H 11*9e2c7d99SGeorge Cherian 12*9e2c7d99SGeorge Cherian #include "cpt_common.h" 13*9e2c7d99SGeorge Cherian 14*9e2c7d99SGeorge Cherian #define CSR_DELAY 30 15*9e2c7d99SGeorge Cherian #define CPT_MAX_CORE_GROUPS 8 16*9e2c7d99SGeorge Cherian #define CPT_MAX_SE_CORES 10 17*9e2c7d99SGeorge Cherian #define CPT_MAX_AE_CORES 6 18*9e2c7d99SGeorge Cherian #define CPT_MAX_TOTAL_CORES (CPT_MAX_SE_CORES + CPT_MAX_AE_CORES) 19*9e2c7d99SGeorge Cherian #define CPT_MAX_VF_NUM 16 20*9e2c7d99SGeorge Cherian #define CPT_PF_MSIX_VECTORS 3 21*9e2c7d99SGeorge Cherian #define CPT_PF_INT_VEC_E_MBOXX(a) (0x02 + (a)) 22*9e2c7d99SGeorge Cherian #define CPT_UCODE_VERSION_SZ 32 23*9e2c7d99SGeorge Cherian struct cpt_device; 24*9e2c7d99SGeorge Cherian 25*9e2c7d99SGeorge Cherian struct microcode { 26*9e2c7d99SGeorge Cherian u8 is_mc_valid; 27*9e2c7d99SGeorge Cherian u8 is_ae; 28*9e2c7d99SGeorge Cherian u8 group; 29*9e2c7d99SGeorge Cherian u8 num_cores; 30*9e2c7d99SGeorge Cherian u32 code_size; 31*9e2c7d99SGeorge Cherian u64 core_mask; 32*9e2c7d99SGeorge Cherian u8 version[CPT_UCODE_VERSION_SZ]; 33*9e2c7d99SGeorge Cherian /* Base info */ 34*9e2c7d99SGeorge Cherian dma_addr_t phys_base; 35*9e2c7d99SGeorge Cherian void *code; 36*9e2c7d99SGeorge Cherian }; 37*9e2c7d99SGeorge Cherian 38*9e2c7d99SGeorge Cherian struct cpt_vf_info { 39*9e2c7d99SGeorge Cherian u8 state; 40*9e2c7d99SGeorge Cherian u8 priority; 41*9e2c7d99SGeorge Cherian u8 id; 42*9e2c7d99SGeorge Cherian u32 qlen; 43*9e2c7d99SGeorge Cherian }; 44*9e2c7d99SGeorge Cherian 45*9e2c7d99SGeorge Cherian /** 46*9e2c7d99SGeorge Cherian * cpt device structure 47*9e2c7d99SGeorge Cherian */ 48*9e2c7d99SGeorge Cherian struct cpt_device { 49*9e2c7d99SGeorge Cherian u16 flags; /* Flags to hold device status bits */ 50*9e2c7d99SGeorge Cherian u8 num_vf_en; /* Number of VFs enabled (0...CPT_MAX_VF_NUM) */ 51*9e2c7d99SGeorge Cherian struct cpt_vf_info vfinfo[CPT_MAX_VF_NUM]; /* Per VF info */ 52*9e2c7d99SGeorge Cherian 53*9e2c7d99SGeorge Cherian void __iomem *reg_base; /* Register start address */ 54*9e2c7d99SGeorge Cherian /* MSI-X */ 55*9e2c7d99SGeorge Cherian u8 num_vec; 56*9e2c7d99SGeorge Cherian bool msix_enabled; 57*9e2c7d99SGeorge Cherian struct msix_entry msix_entries[CPT_PF_MSIX_VECTORS]; 58*9e2c7d99SGeorge Cherian bool irq_allocated[CPT_PF_MSIX_VECTORS]; 59*9e2c7d99SGeorge Cherian struct pci_dev *pdev; /* pci device handle */ 60*9e2c7d99SGeorge Cherian 61*9e2c7d99SGeorge Cherian struct microcode mcode[CPT_MAX_CORE_GROUPS]; 62*9e2c7d99SGeorge Cherian u8 next_mc_idx; /* next microcode index */ 63*9e2c7d99SGeorge Cherian u8 next_group; 64*9e2c7d99SGeorge Cherian u8 max_se_cores; 65*9e2c7d99SGeorge Cherian u8 max_ae_cores; 66*9e2c7d99SGeorge Cherian }; 67*9e2c7d99SGeorge Cherian 68*9e2c7d99SGeorge Cherian void cpt_mbox_intr_handler(struct cpt_device *cpt, int mbx); 69*9e2c7d99SGeorge Cherian #endif /* __CPTPF_H */ 70