1*25763b3cSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 29e2c7d99SGeorge Cherian /* 39e2c7d99SGeorge Cherian * Copyright (C) 2016 Cavium, Inc. 49e2c7d99SGeorge Cherian */ 59e2c7d99SGeorge Cherian 69e2c7d99SGeorge Cherian #ifndef __CPTPF_H 79e2c7d99SGeorge Cherian #define __CPTPF_H 89e2c7d99SGeorge Cherian 99e2c7d99SGeorge Cherian #include "cpt_common.h" 109e2c7d99SGeorge Cherian 119e2c7d99SGeorge Cherian #define CSR_DELAY 30 129e2c7d99SGeorge Cherian #define CPT_MAX_CORE_GROUPS 8 139e2c7d99SGeorge Cherian #define CPT_MAX_SE_CORES 10 149e2c7d99SGeorge Cherian #define CPT_MAX_AE_CORES 6 159e2c7d99SGeorge Cherian #define CPT_MAX_TOTAL_CORES (CPT_MAX_SE_CORES + CPT_MAX_AE_CORES) 169e2c7d99SGeorge Cherian #define CPT_MAX_VF_NUM 16 179e2c7d99SGeorge Cherian #define CPT_PF_MSIX_VECTORS 3 189e2c7d99SGeorge Cherian #define CPT_PF_INT_VEC_E_MBOXX(a) (0x02 + (a)) 199e2c7d99SGeorge Cherian #define CPT_UCODE_VERSION_SZ 32 209e2c7d99SGeorge Cherian struct cpt_device; 219e2c7d99SGeorge Cherian 229e2c7d99SGeorge Cherian struct microcode { 239e2c7d99SGeorge Cherian u8 is_mc_valid; 249e2c7d99SGeorge Cherian u8 is_ae; 259e2c7d99SGeorge Cherian u8 group; 269e2c7d99SGeorge Cherian u8 num_cores; 279e2c7d99SGeorge Cherian u32 code_size; 289e2c7d99SGeorge Cherian u64 core_mask; 299e2c7d99SGeorge Cherian u8 version[CPT_UCODE_VERSION_SZ]; 309e2c7d99SGeorge Cherian /* Base info */ 319e2c7d99SGeorge Cherian dma_addr_t phys_base; 329e2c7d99SGeorge Cherian void *code; 339e2c7d99SGeorge Cherian }; 349e2c7d99SGeorge Cherian 359e2c7d99SGeorge Cherian struct cpt_vf_info { 369e2c7d99SGeorge Cherian u8 state; 379e2c7d99SGeorge Cherian u8 priority; 389e2c7d99SGeorge Cherian u8 id; 399e2c7d99SGeorge Cherian u32 qlen; 409e2c7d99SGeorge Cherian }; 419e2c7d99SGeorge Cherian 429e2c7d99SGeorge Cherian /** 439e2c7d99SGeorge Cherian * cpt device structure 449e2c7d99SGeorge Cherian */ 459e2c7d99SGeorge Cherian struct cpt_device { 469e2c7d99SGeorge Cherian u16 flags; /* Flags to hold device status bits */ 479e2c7d99SGeorge Cherian u8 num_vf_en; /* Number of VFs enabled (0...CPT_MAX_VF_NUM) */ 489e2c7d99SGeorge Cherian struct cpt_vf_info vfinfo[CPT_MAX_VF_NUM]; /* Per VF info */ 499e2c7d99SGeorge Cherian 509e2c7d99SGeorge Cherian void __iomem *reg_base; /* Register start address */ 519e2c7d99SGeorge Cherian struct pci_dev *pdev; /* pci device handle */ 529e2c7d99SGeorge Cherian 539e2c7d99SGeorge Cherian struct microcode mcode[CPT_MAX_CORE_GROUPS]; 549e2c7d99SGeorge Cherian u8 next_mc_idx; /* next microcode index */ 559e2c7d99SGeorge Cherian u8 next_group; 569e2c7d99SGeorge Cherian u8 max_se_cores; 579e2c7d99SGeorge Cherian u8 max_ae_cores; 589e2c7d99SGeorge Cherian }; 599e2c7d99SGeorge Cherian 609e2c7d99SGeorge Cherian void cpt_mbox_intr_handler(struct cpt_device *cpt, int mbx); 619e2c7d99SGeorge Cherian #endif /* __CPTPF_H */ 62