1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2021 Aspeed Technology Inc. 4 */ 5 6 #include "aspeed-hace.h" 7 8 #ifdef CONFIG_CRYPTO_DEV_ASPEED_DEBUG 9 #define AHASH_DBG(h, fmt, ...) \ 10 dev_info((h)->dev, "%s() " fmt, __func__, ##__VA_ARGS__) 11 #else 12 #define AHASH_DBG(h, fmt, ...) \ 13 dev_dbg((h)->dev, "%s() " fmt, __func__, ##__VA_ARGS__) 14 #endif 15 16 /* Initialization Vectors for SHA-family */ 17 static const __be32 sha1_iv[8] = { 18 cpu_to_be32(SHA1_H0), cpu_to_be32(SHA1_H1), 19 cpu_to_be32(SHA1_H2), cpu_to_be32(SHA1_H3), 20 cpu_to_be32(SHA1_H4), 0, 0, 0 21 }; 22 23 static const __be32 sha224_iv[8] = { 24 cpu_to_be32(SHA224_H0), cpu_to_be32(SHA224_H1), 25 cpu_to_be32(SHA224_H2), cpu_to_be32(SHA224_H3), 26 cpu_to_be32(SHA224_H4), cpu_to_be32(SHA224_H5), 27 cpu_to_be32(SHA224_H6), cpu_to_be32(SHA224_H7), 28 }; 29 30 static const __be32 sha256_iv[8] = { 31 cpu_to_be32(SHA256_H0), cpu_to_be32(SHA256_H1), 32 cpu_to_be32(SHA256_H2), cpu_to_be32(SHA256_H3), 33 cpu_to_be32(SHA256_H4), cpu_to_be32(SHA256_H5), 34 cpu_to_be32(SHA256_H6), cpu_to_be32(SHA256_H7), 35 }; 36 37 static const __be64 sha384_iv[8] = { 38 cpu_to_be64(SHA384_H0), cpu_to_be64(SHA384_H1), 39 cpu_to_be64(SHA384_H2), cpu_to_be64(SHA384_H3), 40 cpu_to_be64(SHA384_H4), cpu_to_be64(SHA384_H5), 41 cpu_to_be64(SHA384_H6), cpu_to_be64(SHA384_H7) 42 }; 43 44 static const __be64 sha512_iv[8] = { 45 cpu_to_be64(SHA512_H0), cpu_to_be64(SHA512_H1), 46 cpu_to_be64(SHA512_H2), cpu_to_be64(SHA512_H3), 47 cpu_to_be64(SHA512_H4), cpu_to_be64(SHA512_H5), 48 cpu_to_be64(SHA512_H6), cpu_to_be64(SHA512_H7) 49 }; 50 51 static const __be32 sha512_224_iv[16] = { 52 cpu_to_be32(0xC8373D8CUL), cpu_to_be32(0xA24D5419UL), 53 cpu_to_be32(0x6699E173UL), cpu_to_be32(0xD6D4DC89UL), 54 cpu_to_be32(0xAEB7FA1DUL), cpu_to_be32(0x829CFF32UL), 55 cpu_to_be32(0x14D59D67UL), cpu_to_be32(0xCF9F2F58UL), 56 cpu_to_be32(0x692B6D0FUL), cpu_to_be32(0xA84DD47BUL), 57 cpu_to_be32(0x736FE377UL), cpu_to_be32(0x4289C404UL), 58 cpu_to_be32(0xA8859D3FUL), cpu_to_be32(0xC8361D6AUL), 59 cpu_to_be32(0xADE61211UL), cpu_to_be32(0xA192D691UL) 60 }; 61 62 static const __be32 sha512_256_iv[16] = { 63 cpu_to_be32(0x94213122UL), cpu_to_be32(0x2CF72BFCUL), 64 cpu_to_be32(0xA35F559FUL), cpu_to_be32(0xC2644CC8UL), 65 cpu_to_be32(0x6BB89323UL), cpu_to_be32(0x51B1536FUL), 66 cpu_to_be32(0x19773896UL), cpu_to_be32(0xBDEA4059UL), 67 cpu_to_be32(0xE23E2896UL), cpu_to_be32(0xE3FF8EA8UL), 68 cpu_to_be32(0x251E5EBEUL), cpu_to_be32(0x92398653UL), 69 cpu_to_be32(0xFC99012BUL), cpu_to_be32(0xAAB8852CUL), 70 cpu_to_be32(0xDC2DB70EUL), cpu_to_be32(0xA22CC581UL) 71 }; 72 73 /* The purpose of this padding is to ensure that the padded message is a 74 * multiple of 512 bits (SHA1/SHA224/SHA256) or 1024 bits (SHA384/SHA512). 75 * The bit "1" is appended at the end of the message followed by 76 * "padlen-1" zero bits. Then a 64 bits block (SHA1/SHA224/SHA256) or 77 * 128 bits block (SHA384/SHA512) equals to the message length in bits 78 * is appended. 79 * 80 * For SHA1/SHA224/SHA256, padlen is calculated as followed: 81 * - if message length < 56 bytes then padlen = 56 - message length 82 * - else padlen = 64 + 56 - message length 83 * 84 * For SHA384/SHA512, padlen is calculated as followed: 85 * - if message length < 112 bytes then padlen = 112 - message length 86 * - else padlen = 128 + 112 - message length 87 */ 88 static void aspeed_ahash_fill_padding(struct aspeed_hace_dev *hace_dev, 89 struct aspeed_sham_reqctx *rctx) 90 { 91 unsigned int index, padlen; 92 __be64 bits[2]; 93 94 AHASH_DBG(hace_dev, "rctx flags:0x%x\n", (u32)rctx->flags); 95 96 switch (rctx->flags & SHA_FLAGS_MASK) { 97 case SHA_FLAGS_SHA1: 98 case SHA_FLAGS_SHA224: 99 case SHA_FLAGS_SHA256: 100 bits[0] = cpu_to_be64(rctx->digcnt[0] << 3); 101 index = rctx->bufcnt & 0x3f; 102 padlen = (index < 56) ? (56 - index) : ((64 + 56) - index); 103 *(rctx->buffer + rctx->bufcnt) = 0x80; 104 memset(rctx->buffer + rctx->bufcnt + 1, 0, padlen - 1); 105 memcpy(rctx->buffer + rctx->bufcnt + padlen, bits, 8); 106 rctx->bufcnt += padlen + 8; 107 break; 108 default: 109 bits[1] = cpu_to_be64(rctx->digcnt[0] << 3); 110 bits[0] = cpu_to_be64(rctx->digcnt[1] << 3 | 111 rctx->digcnt[0] >> 61); 112 index = rctx->bufcnt & 0x7f; 113 padlen = (index < 112) ? (112 - index) : ((128 + 112) - index); 114 *(rctx->buffer + rctx->bufcnt) = 0x80; 115 memset(rctx->buffer + rctx->bufcnt + 1, 0, padlen - 1); 116 memcpy(rctx->buffer + rctx->bufcnt + padlen, bits, 16); 117 rctx->bufcnt += padlen + 16; 118 break; 119 } 120 } 121 122 /* 123 * Prepare DMA buffer before hardware engine 124 * processing. 125 */ 126 static int aspeed_ahash_dma_prepare(struct aspeed_hace_dev *hace_dev) 127 { 128 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine; 129 struct ahash_request *req = hash_engine->req; 130 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 131 int length, remain; 132 133 length = rctx->total + rctx->bufcnt; 134 remain = length % rctx->block_size; 135 136 AHASH_DBG(hace_dev, "length:0x%x, remain:0x%x\n", length, remain); 137 138 if (rctx->bufcnt) 139 memcpy(hash_engine->ahash_src_addr, rctx->buffer, rctx->bufcnt); 140 141 if (rctx->total + rctx->bufcnt < ASPEED_CRYPTO_SRC_DMA_BUF_LEN) { 142 scatterwalk_map_and_copy(hash_engine->ahash_src_addr + 143 rctx->bufcnt, rctx->src_sg, 144 rctx->offset, rctx->total - remain, 0); 145 rctx->offset += rctx->total - remain; 146 147 } else { 148 dev_warn(hace_dev->dev, "Hash data length is too large\n"); 149 return -EINVAL; 150 } 151 152 scatterwalk_map_and_copy(rctx->buffer, rctx->src_sg, 153 rctx->offset, remain, 0); 154 155 rctx->bufcnt = remain; 156 rctx->digest_dma_addr = dma_map_single(hace_dev->dev, rctx->digest, 157 SHA512_DIGEST_SIZE, 158 DMA_BIDIRECTIONAL); 159 if (dma_mapping_error(hace_dev->dev, rctx->digest_dma_addr)) { 160 dev_warn(hace_dev->dev, "dma_map() rctx digest error\n"); 161 return -ENOMEM; 162 } 163 164 hash_engine->src_length = length - remain; 165 hash_engine->src_dma = hash_engine->ahash_src_dma_addr; 166 hash_engine->digest_dma = rctx->digest_dma_addr; 167 168 return 0; 169 } 170 171 /* 172 * Prepare DMA buffer as SG list buffer before 173 * hardware engine processing. 174 */ 175 static int aspeed_ahash_dma_prepare_sg(struct aspeed_hace_dev *hace_dev) 176 { 177 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine; 178 struct ahash_request *req = hash_engine->req; 179 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 180 struct aspeed_sg_list *src_list; 181 struct scatterlist *s; 182 int length, remain, sg_len, i; 183 int rc = 0; 184 185 remain = (rctx->total + rctx->bufcnt) % rctx->block_size; 186 length = rctx->total + rctx->bufcnt - remain; 187 188 AHASH_DBG(hace_dev, "%s:0x%x, %s:%zu, %s:0x%x, %s:0x%x\n", 189 "rctx total", rctx->total, "bufcnt", rctx->bufcnt, 190 "length", length, "remain", remain); 191 192 sg_len = dma_map_sg(hace_dev->dev, rctx->src_sg, rctx->src_nents, 193 DMA_TO_DEVICE); 194 if (!sg_len) { 195 dev_warn(hace_dev->dev, "dma_map_sg() src error\n"); 196 rc = -ENOMEM; 197 goto end; 198 } 199 200 src_list = (struct aspeed_sg_list *)hash_engine->ahash_src_addr; 201 rctx->digest_dma_addr = dma_map_single(hace_dev->dev, rctx->digest, 202 SHA512_DIGEST_SIZE, 203 DMA_BIDIRECTIONAL); 204 if (dma_mapping_error(hace_dev->dev, rctx->digest_dma_addr)) { 205 dev_warn(hace_dev->dev, "dma_map() rctx digest error\n"); 206 rc = -ENOMEM; 207 goto free_src_sg; 208 } 209 210 if (rctx->bufcnt != 0) { 211 rctx->buffer_dma_addr = dma_map_single(hace_dev->dev, 212 rctx->buffer, 213 rctx->block_size * 2, 214 DMA_TO_DEVICE); 215 if (dma_mapping_error(hace_dev->dev, rctx->buffer_dma_addr)) { 216 dev_warn(hace_dev->dev, "dma_map() rctx buffer error\n"); 217 rc = -ENOMEM; 218 goto free_rctx_digest; 219 } 220 221 src_list[0].phy_addr = rctx->buffer_dma_addr; 222 src_list[0].len = rctx->bufcnt; 223 length -= src_list[0].len; 224 225 /* Last sg list */ 226 if (length == 0) 227 src_list[0].len |= HASH_SG_LAST_LIST; 228 229 src_list[0].phy_addr = cpu_to_le32(src_list[0].phy_addr); 230 src_list[0].len = cpu_to_le32(src_list[0].len); 231 src_list++; 232 } 233 234 if (length != 0) { 235 for_each_sg(rctx->src_sg, s, sg_len, i) { 236 src_list[i].phy_addr = sg_dma_address(s); 237 238 if (length > sg_dma_len(s)) { 239 src_list[i].len = sg_dma_len(s); 240 length -= sg_dma_len(s); 241 242 } else { 243 /* Last sg list */ 244 src_list[i].len = length; 245 src_list[i].len |= HASH_SG_LAST_LIST; 246 length = 0; 247 } 248 249 src_list[i].phy_addr = cpu_to_le32(src_list[i].phy_addr); 250 src_list[i].len = cpu_to_le32(src_list[i].len); 251 } 252 } 253 254 if (length != 0) { 255 rc = -EINVAL; 256 goto free_rctx_buffer; 257 } 258 259 rctx->offset = rctx->total - remain; 260 hash_engine->src_length = rctx->total + rctx->bufcnt - remain; 261 hash_engine->src_dma = hash_engine->ahash_src_dma_addr; 262 hash_engine->digest_dma = rctx->digest_dma_addr; 263 264 return 0; 265 266 free_rctx_buffer: 267 if (rctx->bufcnt != 0) 268 dma_unmap_single(hace_dev->dev, rctx->buffer_dma_addr, 269 rctx->block_size * 2, DMA_TO_DEVICE); 270 free_rctx_digest: 271 dma_unmap_single(hace_dev->dev, rctx->digest_dma_addr, 272 SHA512_DIGEST_SIZE, DMA_BIDIRECTIONAL); 273 free_src_sg: 274 dma_unmap_sg(hace_dev->dev, rctx->src_sg, rctx->src_nents, 275 DMA_TO_DEVICE); 276 end: 277 return rc; 278 } 279 280 static int aspeed_ahash_complete(struct aspeed_hace_dev *hace_dev) 281 { 282 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine; 283 struct ahash_request *req = hash_engine->req; 284 285 AHASH_DBG(hace_dev, "\n"); 286 287 hash_engine->flags &= ~CRYPTO_FLAGS_BUSY; 288 289 crypto_finalize_hash_request(hace_dev->crypt_engine_hash, req, 0); 290 291 return 0; 292 } 293 294 /* 295 * Copy digest to the corresponding request result. 296 * This function will be called at final() stage. 297 */ 298 static int aspeed_ahash_transfer(struct aspeed_hace_dev *hace_dev) 299 { 300 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine; 301 struct ahash_request *req = hash_engine->req; 302 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 303 304 AHASH_DBG(hace_dev, "\n"); 305 306 dma_unmap_single(hace_dev->dev, rctx->digest_dma_addr, 307 SHA512_DIGEST_SIZE, DMA_BIDIRECTIONAL); 308 309 dma_unmap_single(hace_dev->dev, rctx->buffer_dma_addr, 310 rctx->block_size * 2, DMA_TO_DEVICE); 311 312 memcpy(req->result, rctx->digest, rctx->digsize); 313 314 return aspeed_ahash_complete(hace_dev); 315 } 316 317 /* 318 * Trigger hardware engines to do the math. 319 */ 320 static int aspeed_hace_ahash_trigger(struct aspeed_hace_dev *hace_dev, 321 aspeed_hace_fn_t resume) 322 { 323 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine; 324 struct ahash_request *req = hash_engine->req; 325 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 326 327 AHASH_DBG(hace_dev, "src_dma:%pad, digest_dma:%pad, length:%zu\n", 328 &hash_engine->src_dma, &hash_engine->digest_dma, 329 hash_engine->src_length); 330 331 rctx->cmd |= HASH_CMD_INT_ENABLE; 332 hash_engine->resume = resume; 333 334 ast_hace_write(hace_dev, hash_engine->src_dma, ASPEED_HACE_HASH_SRC); 335 ast_hace_write(hace_dev, hash_engine->digest_dma, 336 ASPEED_HACE_HASH_DIGEST_BUFF); 337 ast_hace_write(hace_dev, hash_engine->digest_dma, 338 ASPEED_HACE_HASH_KEY_BUFF); 339 ast_hace_write(hace_dev, hash_engine->src_length, 340 ASPEED_HACE_HASH_DATA_LEN); 341 342 /* Memory barrier to ensure all data setup before engine starts */ 343 mb(); 344 345 ast_hace_write(hace_dev, rctx->cmd, ASPEED_HACE_HASH_CMD); 346 347 return -EINPROGRESS; 348 } 349 350 /* 351 * HMAC resume aims to do the second pass produces 352 * the final HMAC code derived from the inner hash 353 * result and the outer key. 354 */ 355 static int aspeed_ahash_hmac_resume(struct aspeed_hace_dev *hace_dev) 356 { 357 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine; 358 struct ahash_request *req = hash_engine->req; 359 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 360 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 361 struct aspeed_sham_ctx *tctx = crypto_ahash_ctx(tfm); 362 struct aspeed_sha_hmac_ctx *bctx = tctx->base; 363 int rc = 0; 364 365 AHASH_DBG(hace_dev, "\n"); 366 367 dma_unmap_single(hace_dev->dev, rctx->digest_dma_addr, 368 SHA512_DIGEST_SIZE, DMA_BIDIRECTIONAL); 369 370 dma_unmap_single(hace_dev->dev, rctx->buffer_dma_addr, 371 rctx->block_size * 2, DMA_TO_DEVICE); 372 373 /* o key pad + hash sum 1 */ 374 memcpy(rctx->buffer, bctx->opad, rctx->block_size); 375 memcpy(rctx->buffer + rctx->block_size, rctx->digest, rctx->digsize); 376 377 rctx->bufcnt = rctx->block_size + rctx->digsize; 378 rctx->digcnt[0] = rctx->block_size + rctx->digsize; 379 380 aspeed_ahash_fill_padding(hace_dev, rctx); 381 memcpy(rctx->digest, rctx->sha_iv, rctx->ivsize); 382 383 rctx->digest_dma_addr = dma_map_single(hace_dev->dev, rctx->digest, 384 SHA512_DIGEST_SIZE, 385 DMA_BIDIRECTIONAL); 386 if (dma_mapping_error(hace_dev->dev, rctx->digest_dma_addr)) { 387 dev_warn(hace_dev->dev, "dma_map() rctx digest error\n"); 388 rc = -ENOMEM; 389 goto end; 390 } 391 392 rctx->buffer_dma_addr = dma_map_single(hace_dev->dev, rctx->buffer, 393 rctx->block_size * 2, 394 DMA_TO_DEVICE); 395 if (dma_mapping_error(hace_dev->dev, rctx->buffer_dma_addr)) { 396 dev_warn(hace_dev->dev, "dma_map() rctx buffer error\n"); 397 rc = -ENOMEM; 398 goto free_rctx_digest; 399 } 400 401 hash_engine->src_dma = rctx->buffer_dma_addr; 402 hash_engine->src_length = rctx->bufcnt; 403 hash_engine->digest_dma = rctx->digest_dma_addr; 404 405 return aspeed_hace_ahash_trigger(hace_dev, aspeed_ahash_transfer); 406 407 free_rctx_digest: 408 dma_unmap_single(hace_dev->dev, rctx->digest_dma_addr, 409 SHA512_DIGEST_SIZE, DMA_BIDIRECTIONAL); 410 end: 411 return rc; 412 } 413 414 static int aspeed_ahash_req_final(struct aspeed_hace_dev *hace_dev) 415 { 416 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine; 417 struct ahash_request *req = hash_engine->req; 418 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 419 int rc = 0; 420 421 AHASH_DBG(hace_dev, "\n"); 422 423 aspeed_ahash_fill_padding(hace_dev, rctx); 424 425 rctx->digest_dma_addr = dma_map_single(hace_dev->dev, 426 rctx->digest, 427 SHA512_DIGEST_SIZE, 428 DMA_BIDIRECTIONAL); 429 if (dma_mapping_error(hace_dev->dev, rctx->digest_dma_addr)) { 430 dev_warn(hace_dev->dev, "dma_map() rctx digest error\n"); 431 rc = -ENOMEM; 432 goto end; 433 } 434 435 rctx->buffer_dma_addr = dma_map_single(hace_dev->dev, 436 rctx->buffer, 437 rctx->block_size * 2, 438 DMA_TO_DEVICE); 439 if (dma_mapping_error(hace_dev->dev, rctx->buffer_dma_addr)) { 440 dev_warn(hace_dev->dev, "dma_map() rctx buffer error\n"); 441 rc = -ENOMEM; 442 goto free_rctx_digest; 443 } 444 445 hash_engine->src_dma = rctx->buffer_dma_addr; 446 hash_engine->src_length = rctx->bufcnt; 447 hash_engine->digest_dma = rctx->digest_dma_addr; 448 449 if (rctx->flags & SHA_FLAGS_HMAC) 450 return aspeed_hace_ahash_trigger(hace_dev, 451 aspeed_ahash_hmac_resume); 452 453 return aspeed_hace_ahash_trigger(hace_dev, aspeed_ahash_transfer); 454 455 free_rctx_digest: 456 dma_unmap_single(hace_dev->dev, rctx->digest_dma_addr, 457 SHA512_DIGEST_SIZE, DMA_BIDIRECTIONAL); 458 end: 459 return rc; 460 } 461 462 static int aspeed_ahash_update_resume_sg(struct aspeed_hace_dev *hace_dev) 463 { 464 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine; 465 struct ahash_request *req = hash_engine->req; 466 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 467 468 AHASH_DBG(hace_dev, "\n"); 469 470 dma_unmap_sg(hace_dev->dev, rctx->src_sg, rctx->src_nents, 471 DMA_TO_DEVICE); 472 473 if (rctx->bufcnt != 0) 474 dma_unmap_single(hace_dev->dev, rctx->buffer_dma_addr, 475 rctx->block_size * 2, 476 DMA_TO_DEVICE); 477 478 dma_unmap_single(hace_dev->dev, rctx->digest_dma_addr, 479 SHA512_DIGEST_SIZE, DMA_BIDIRECTIONAL); 480 481 scatterwalk_map_and_copy(rctx->buffer, rctx->src_sg, rctx->offset, 482 rctx->total - rctx->offset, 0); 483 484 rctx->bufcnt = rctx->total - rctx->offset; 485 rctx->cmd &= ~HASH_CMD_HASH_SRC_SG_CTRL; 486 487 if (rctx->flags & SHA_FLAGS_FINUP) 488 return aspeed_ahash_req_final(hace_dev); 489 490 return aspeed_ahash_complete(hace_dev); 491 } 492 493 static int aspeed_ahash_update_resume(struct aspeed_hace_dev *hace_dev) 494 { 495 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine; 496 struct ahash_request *req = hash_engine->req; 497 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 498 499 AHASH_DBG(hace_dev, "\n"); 500 501 dma_unmap_single(hace_dev->dev, rctx->digest_dma_addr, 502 SHA512_DIGEST_SIZE, DMA_BIDIRECTIONAL); 503 504 if (rctx->flags & SHA_FLAGS_FINUP) 505 return aspeed_ahash_req_final(hace_dev); 506 507 return aspeed_ahash_complete(hace_dev); 508 } 509 510 static int aspeed_ahash_req_update(struct aspeed_hace_dev *hace_dev) 511 { 512 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine; 513 struct ahash_request *req = hash_engine->req; 514 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 515 aspeed_hace_fn_t resume; 516 int ret; 517 518 AHASH_DBG(hace_dev, "\n"); 519 520 if (hace_dev->version == AST2600_VERSION) { 521 rctx->cmd |= HASH_CMD_HASH_SRC_SG_CTRL; 522 resume = aspeed_ahash_update_resume_sg; 523 524 } else { 525 resume = aspeed_ahash_update_resume; 526 } 527 528 ret = hash_engine->dma_prepare(hace_dev); 529 if (ret) 530 return ret; 531 532 return aspeed_hace_ahash_trigger(hace_dev, resume); 533 } 534 535 static int aspeed_hace_hash_handle_queue(struct aspeed_hace_dev *hace_dev, 536 struct ahash_request *req) 537 { 538 return crypto_transfer_hash_request_to_engine( 539 hace_dev->crypt_engine_hash, req); 540 } 541 542 static int aspeed_ahash_do_request(struct crypto_engine *engine, void *areq) 543 { 544 struct ahash_request *req = ahash_request_cast(areq); 545 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 546 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 547 struct aspeed_sham_ctx *tctx = crypto_ahash_ctx(tfm); 548 struct aspeed_hace_dev *hace_dev = tctx->hace_dev; 549 struct aspeed_engine_hash *hash_engine; 550 int ret = 0; 551 552 hash_engine = &hace_dev->hash_engine; 553 hash_engine->flags |= CRYPTO_FLAGS_BUSY; 554 555 if (rctx->op == SHA_OP_UPDATE) 556 ret = aspeed_ahash_req_update(hace_dev); 557 else if (rctx->op == SHA_OP_FINAL) 558 ret = aspeed_ahash_req_final(hace_dev); 559 560 if (ret != -EINPROGRESS) 561 return ret; 562 563 return 0; 564 } 565 566 static int aspeed_ahash_prepare_request(struct crypto_engine *engine, 567 void *areq) 568 { 569 struct ahash_request *req = ahash_request_cast(areq); 570 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 571 struct aspeed_sham_ctx *tctx = crypto_ahash_ctx(tfm); 572 struct aspeed_hace_dev *hace_dev = tctx->hace_dev; 573 struct aspeed_engine_hash *hash_engine; 574 575 hash_engine = &hace_dev->hash_engine; 576 hash_engine->req = req; 577 578 if (hace_dev->version == AST2600_VERSION) 579 hash_engine->dma_prepare = aspeed_ahash_dma_prepare_sg; 580 else 581 hash_engine->dma_prepare = aspeed_ahash_dma_prepare; 582 583 return 0; 584 } 585 586 static int aspeed_sham_update(struct ahash_request *req) 587 { 588 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 589 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 590 struct aspeed_sham_ctx *tctx = crypto_ahash_ctx(tfm); 591 struct aspeed_hace_dev *hace_dev = tctx->hace_dev; 592 593 AHASH_DBG(hace_dev, "req->nbytes: %d\n", req->nbytes); 594 595 rctx->total = req->nbytes; 596 rctx->src_sg = req->src; 597 rctx->offset = 0; 598 rctx->src_nents = sg_nents(req->src); 599 rctx->op = SHA_OP_UPDATE; 600 601 rctx->digcnt[0] += rctx->total; 602 if (rctx->digcnt[0] < rctx->total) 603 rctx->digcnt[1]++; 604 605 if (rctx->bufcnt + rctx->total < rctx->block_size) { 606 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, 607 rctx->src_sg, rctx->offset, 608 rctx->total, 0); 609 rctx->bufcnt += rctx->total; 610 611 return 0; 612 } 613 614 return aspeed_hace_hash_handle_queue(hace_dev, req); 615 } 616 617 static int aspeed_sham_shash_digest(struct crypto_shash *tfm, u32 flags, 618 const u8 *data, unsigned int len, u8 *out) 619 { 620 SHASH_DESC_ON_STACK(shash, tfm); 621 622 shash->tfm = tfm; 623 624 return crypto_shash_digest(shash, data, len, out); 625 } 626 627 static int aspeed_sham_final(struct ahash_request *req) 628 { 629 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 630 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 631 struct aspeed_sham_ctx *tctx = crypto_ahash_ctx(tfm); 632 struct aspeed_hace_dev *hace_dev = tctx->hace_dev; 633 634 AHASH_DBG(hace_dev, "req->nbytes:%d, rctx->total:%d\n", 635 req->nbytes, rctx->total); 636 rctx->op = SHA_OP_FINAL; 637 638 return aspeed_hace_hash_handle_queue(hace_dev, req); 639 } 640 641 static int aspeed_sham_finup(struct ahash_request *req) 642 { 643 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 644 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 645 struct aspeed_sham_ctx *tctx = crypto_ahash_ctx(tfm); 646 struct aspeed_hace_dev *hace_dev = tctx->hace_dev; 647 int rc1, rc2; 648 649 AHASH_DBG(hace_dev, "req->nbytes: %d\n", req->nbytes); 650 651 rctx->flags |= SHA_FLAGS_FINUP; 652 653 rc1 = aspeed_sham_update(req); 654 if (rc1 == -EINPROGRESS || rc1 == -EBUSY) 655 return rc1; 656 657 /* 658 * final() has to be always called to cleanup resources 659 * even if update() failed, except EINPROGRESS 660 */ 661 rc2 = aspeed_sham_final(req); 662 663 return rc1 ? : rc2; 664 } 665 666 static int aspeed_sham_init(struct ahash_request *req) 667 { 668 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 669 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 670 struct aspeed_sham_ctx *tctx = crypto_ahash_ctx(tfm); 671 struct aspeed_hace_dev *hace_dev = tctx->hace_dev; 672 struct aspeed_sha_hmac_ctx *bctx = tctx->base; 673 674 AHASH_DBG(hace_dev, "%s: digest size:%d\n", 675 crypto_tfm_alg_name(&tfm->base), 676 crypto_ahash_digestsize(tfm)); 677 678 rctx->cmd = HASH_CMD_ACC_MODE; 679 rctx->flags = 0; 680 681 switch (crypto_ahash_digestsize(tfm)) { 682 case SHA1_DIGEST_SIZE: 683 rctx->cmd |= HASH_CMD_SHA1 | HASH_CMD_SHA_SWAP; 684 rctx->flags |= SHA_FLAGS_SHA1; 685 rctx->digsize = SHA1_DIGEST_SIZE; 686 rctx->block_size = SHA1_BLOCK_SIZE; 687 rctx->sha_iv = sha1_iv; 688 rctx->ivsize = 32; 689 memcpy(rctx->digest, sha1_iv, rctx->ivsize); 690 break; 691 case SHA224_DIGEST_SIZE: 692 rctx->cmd |= HASH_CMD_SHA224 | HASH_CMD_SHA_SWAP; 693 rctx->flags |= SHA_FLAGS_SHA224; 694 rctx->digsize = SHA224_DIGEST_SIZE; 695 rctx->block_size = SHA224_BLOCK_SIZE; 696 rctx->sha_iv = sha224_iv; 697 rctx->ivsize = 32; 698 memcpy(rctx->digest, sha224_iv, rctx->ivsize); 699 break; 700 case SHA256_DIGEST_SIZE: 701 rctx->cmd |= HASH_CMD_SHA256 | HASH_CMD_SHA_SWAP; 702 rctx->flags |= SHA_FLAGS_SHA256; 703 rctx->digsize = SHA256_DIGEST_SIZE; 704 rctx->block_size = SHA256_BLOCK_SIZE; 705 rctx->sha_iv = sha256_iv; 706 rctx->ivsize = 32; 707 memcpy(rctx->digest, sha256_iv, rctx->ivsize); 708 break; 709 case SHA384_DIGEST_SIZE: 710 rctx->cmd |= HASH_CMD_SHA512_SER | HASH_CMD_SHA384 | 711 HASH_CMD_SHA_SWAP; 712 rctx->flags |= SHA_FLAGS_SHA384; 713 rctx->digsize = SHA384_DIGEST_SIZE; 714 rctx->block_size = SHA384_BLOCK_SIZE; 715 rctx->sha_iv = (const __be32 *)sha384_iv; 716 rctx->ivsize = 64; 717 memcpy(rctx->digest, sha384_iv, rctx->ivsize); 718 break; 719 case SHA512_DIGEST_SIZE: 720 rctx->cmd |= HASH_CMD_SHA512_SER | HASH_CMD_SHA512 | 721 HASH_CMD_SHA_SWAP; 722 rctx->flags |= SHA_FLAGS_SHA512; 723 rctx->digsize = SHA512_DIGEST_SIZE; 724 rctx->block_size = SHA512_BLOCK_SIZE; 725 rctx->sha_iv = (const __be32 *)sha512_iv; 726 rctx->ivsize = 64; 727 memcpy(rctx->digest, sha512_iv, rctx->ivsize); 728 break; 729 default: 730 dev_warn(tctx->hace_dev->dev, "digest size %d not support\n", 731 crypto_ahash_digestsize(tfm)); 732 return -EINVAL; 733 } 734 735 rctx->bufcnt = 0; 736 rctx->total = 0; 737 rctx->digcnt[0] = 0; 738 rctx->digcnt[1] = 0; 739 740 /* HMAC init */ 741 if (tctx->flags & SHA_FLAGS_HMAC) { 742 rctx->digcnt[0] = rctx->block_size; 743 rctx->bufcnt = rctx->block_size; 744 memcpy(rctx->buffer, bctx->ipad, rctx->block_size); 745 rctx->flags |= SHA_FLAGS_HMAC; 746 } 747 748 return 0; 749 } 750 751 static int aspeed_sha512s_init(struct ahash_request *req) 752 { 753 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 754 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 755 struct aspeed_sham_ctx *tctx = crypto_ahash_ctx(tfm); 756 struct aspeed_hace_dev *hace_dev = tctx->hace_dev; 757 struct aspeed_sha_hmac_ctx *bctx = tctx->base; 758 759 AHASH_DBG(hace_dev, "digest size: %d\n", crypto_ahash_digestsize(tfm)); 760 761 rctx->cmd = HASH_CMD_ACC_MODE; 762 rctx->flags = 0; 763 764 switch (crypto_ahash_digestsize(tfm)) { 765 case SHA224_DIGEST_SIZE: 766 rctx->cmd |= HASH_CMD_SHA512_SER | HASH_CMD_SHA512_224 | 767 HASH_CMD_SHA_SWAP; 768 rctx->flags |= SHA_FLAGS_SHA512_224; 769 rctx->digsize = SHA224_DIGEST_SIZE; 770 rctx->block_size = SHA512_BLOCK_SIZE; 771 rctx->sha_iv = sha512_224_iv; 772 rctx->ivsize = 64; 773 memcpy(rctx->digest, sha512_224_iv, rctx->ivsize); 774 break; 775 case SHA256_DIGEST_SIZE: 776 rctx->cmd |= HASH_CMD_SHA512_SER | HASH_CMD_SHA512_256 | 777 HASH_CMD_SHA_SWAP; 778 rctx->flags |= SHA_FLAGS_SHA512_256; 779 rctx->digsize = SHA256_DIGEST_SIZE; 780 rctx->block_size = SHA512_BLOCK_SIZE; 781 rctx->sha_iv = sha512_256_iv; 782 rctx->ivsize = 64; 783 memcpy(rctx->digest, sha512_256_iv, rctx->ivsize); 784 break; 785 default: 786 dev_warn(tctx->hace_dev->dev, "digest size %d not support\n", 787 crypto_ahash_digestsize(tfm)); 788 return -EINVAL; 789 } 790 791 rctx->bufcnt = 0; 792 rctx->total = 0; 793 rctx->digcnt[0] = 0; 794 rctx->digcnt[1] = 0; 795 796 /* HMAC init */ 797 if (tctx->flags & SHA_FLAGS_HMAC) { 798 rctx->digcnt[0] = rctx->block_size; 799 rctx->bufcnt = rctx->block_size; 800 memcpy(rctx->buffer, bctx->ipad, rctx->block_size); 801 rctx->flags |= SHA_FLAGS_HMAC; 802 } 803 804 return 0; 805 } 806 807 static int aspeed_sham_digest(struct ahash_request *req) 808 { 809 return aspeed_sham_init(req) ? : aspeed_sham_finup(req); 810 } 811 812 static int aspeed_sham_setkey(struct crypto_ahash *tfm, const u8 *key, 813 unsigned int keylen) 814 { 815 struct aspeed_sham_ctx *tctx = crypto_ahash_ctx(tfm); 816 struct aspeed_hace_dev *hace_dev = tctx->hace_dev; 817 struct aspeed_sha_hmac_ctx *bctx = tctx->base; 818 int ds = crypto_shash_digestsize(bctx->shash); 819 int bs = crypto_shash_blocksize(bctx->shash); 820 int err = 0; 821 int i; 822 823 AHASH_DBG(hace_dev, "%s: keylen:%d\n", crypto_tfm_alg_name(&tfm->base), 824 keylen); 825 826 if (keylen > bs) { 827 err = aspeed_sham_shash_digest(bctx->shash, 828 crypto_shash_get_flags(bctx->shash), 829 key, keylen, bctx->ipad); 830 if (err) 831 return err; 832 keylen = ds; 833 834 } else { 835 memcpy(bctx->ipad, key, keylen); 836 } 837 838 memset(bctx->ipad + keylen, 0, bs - keylen); 839 memcpy(bctx->opad, bctx->ipad, bs); 840 841 for (i = 0; i < bs; i++) { 842 bctx->ipad[i] ^= HMAC_IPAD_VALUE; 843 bctx->opad[i] ^= HMAC_OPAD_VALUE; 844 } 845 846 return err; 847 } 848 849 static int aspeed_sham_cra_init(struct crypto_tfm *tfm) 850 { 851 struct ahash_alg *alg = __crypto_ahash_alg(tfm->__crt_alg); 852 struct aspeed_sham_ctx *tctx = crypto_tfm_ctx(tfm); 853 struct aspeed_hace_alg *ast_alg; 854 855 ast_alg = container_of(alg, struct aspeed_hace_alg, alg.ahash); 856 tctx->hace_dev = ast_alg->hace_dev; 857 tctx->flags = 0; 858 859 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), 860 sizeof(struct aspeed_sham_reqctx)); 861 862 if (ast_alg->alg_base) { 863 /* hmac related */ 864 struct aspeed_sha_hmac_ctx *bctx = tctx->base; 865 866 tctx->flags |= SHA_FLAGS_HMAC; 867 bctx->shash = crypto_alloc_shash(ast_alg->alg_base, 0, 868 CRYPTO_ALG_NEED_FALLBACK); 869 if (IS_ERR(bctx->shash)) { 870 dev_warn(ast_alg->hace_dev->dev, 871 "base driver '%s' could not be loaded.\n", 872 ast_alg->alg_base); 873 return PTR_ERR(bctx->shash); 874 } 875 } 876 877 tctx->enginectx.op.do_one_request = aspeed_ahash_do_request; 878 tctx->enginectx.op.prepare_request = aspeed_ahash_prepare_request; 879 tctx->enginectx.op.unprepare_request = NULL; 880 881 return 0; 882 } 883 884 static void aspeed_sham_cra_exit(struct crypto_tfm *tfm) 885 { 886 struct aspeed_sham_ctx *tctx = crypto_tfm_ctx(tfm); 887 struct aspeed_hace_dev *hace_dev = tctx->hace_dev; 888 889 AHASH_DBG(hace_dev, "%s\n", crypto_tfm_alg_name(tfm)); 890 891 if (tctx->flags & SHA_FLAGS_HMAC) { 892 struct aspeed_sha_hmac_ctx *bctx = tctx->base; 893 894 crypto_free_shash(bctx->shash); 895 } 896 } 897 898 static int aspeed_sham_export(struct ahash_request *req, void *out) 899 { 900 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 901 902 memcpy(out, rctx, sizeof(*rctx)); 903 904 return 0; 905 } 906 907 static int aspeed_sham_import(struct ahash_request *req, const void *in) 908 { 909 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 910 911 memcpy(rctx, in, sizeof(*rctx)); 912 913 return 0; 914 } 915 916 struct aspeed_hace_alg aspeed_ahash_algs[] = { 917 { 918 .alg.ahash = { 919 .init = aspeed_sham_init, 920 .update = aspeed_sham_update, 921 .final = aspeed_sham_final, 922 .finup = aspeed_sham_finup, 923 .digest = aspeed_sham_digest, 924 .export = aspeed_sham_export, 925 .import = aspeed_sham_import, 926 .halg = { 927 .digestsize = SHA1_DIGEST_SIZE, 928 .statesize = sizeof(struct aspeed_sham_reqctx), 929 .base = { 930 .cra_name = "sha1", 931 .cra_driver_name = "aspeed-sha1", 932 .cra_priority = 300, 933 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 934 CRYPTO_ALG_ASYNC | 935 CRYPTO_ALG_KERN_DRIVER_ONLY, 936 .cra_blocksize = SHA1_BLOCK_SIZE, 937 .cra_ctxsize = sizeof(struct aspeed_sham_ctx), 938 .cra_alignmask = 0, 939 .cra_module = THIS_MODULE, 940 .cra_init = aspeed_sham_cra_init, 941 .cra_exit = aspeed_sham_cra_exit, 942 } 943 } 944 }, 945 }, 946 { 947 .alg.ahash = { 948 .init = aspeed_sham_init, 949 .update = aspeed_sham_update, 950 .final = aspeed_sham_final, 951 .finup = aspeed_sham_finup, 952 .digest = aspeed_sham_digest, 953 .export = aspeed_sham_export, 954 .import = aspeed_sham_import, 955 .halg = { 956 .digestsize = SHA256_DIGEST_SIZE, 957 .statesize = sizeof(struct aspeed_sham_reqctx), 958 .base = { 959 .cra_name = "sha256", 960 .cra_driver_name = "aspeed-sha256", 961 .cra_priority = 300, 962 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 963 CRYPTO_ALG_ASYNC | 964 CRYPTO_ALG_KERN_DRIVER_ONLY, 965 .cra_blocksize = SHA256_BLOCK_SIZE, 966 .cra_ctxsize = sizeof(struct aspeed_sham_ctx), 967 .cra_alignmask = 0, 968 .cra_module = THIS_MODULE, 969 .cra_init = aspeed_sham_cra_init, 970 .cra_exit = aspeed_sham_cra_exit, 971 } 972 } 973 }, 974 }, 975 { 976 .alg.ahash = { 977 .init = aspeed_sham_init, 978 .update = aspeed_sham_update, 979 .final = aspeed_sham_final, 980 .finup = aspeed_sham_finup, 981 .digest = aspeed_sham_digest, 982 .export = aspeed_sham_export, 983 .import = aspeed_sham_import, 984 .halg = { 985 .digestsize = SHA224_DIGEST_SIZE, 986 .statesize = sizeof(struct aspeed_sham_reqctx), 987 .base = { 988 .cra_name = "sha224", 989 .cra_driver_name = "aspeed-sha224", 990 .cra_priority = 300, 991 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 992 CRYPTO_ALG_ASYNC | 993 CRYPTO_ALG_KERN_DRIVER_ONLY, 994 .cra_blocksize = SHA224_BLOCK_SIZE, 995 .cra_ctxsize = sizeof(struct aspeed_sham_ctx), 996 .cra_alignmask = 0, 997 .cra_module = THIS_MODULE, 998 .cra_init = aspeed_sham_cra_init, 999 .cra_exit = aspeed_sham_cra_exit, 1000 } 1001 } 1002 }, 1003 }, 1004 { 1005 .alg_base = "sha1", 1006 .alg.ahash = { 1007 .init = aspeed_sham_init, 1008 .update = aspeed_sham_update, 1009 .final = aspeed_sham_final, 1010 .finup = aspeed_sham_finup, 1011 .digest = aspeed_sham_digest, 1012 .setkey = aspeed_sham_setkey, 1013 .export = aspeed_sham_export, 1014 .import = aspeed_sham_import, 1015 .halg = { 1016 .digestsize = SHA1_DIGEST_SIZE, 1017 .statesize = sizeof(struct aspeed_sham_reqctx), 1018 .base = { 1019 .cra_name = "hmac(sha1)", 1020 .cra_driver_name = "aspeed-hmac-sha1", 1021 .cra_priority = 300, 1022 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1023 CRYPTO_ALG_ASYNC | 1024 CRYPTO_ALG_KERN_DRIVER_ONLY, 1025 .cra_blocksize = SHA1_BLOCK_SIZE, 1026 .cra_ctxsize = sizeof(struct aspeed_sham_ctx) + 1027 sizeof(struct aspeed_sha_hmac_ctx), 1028 .cra_alignmask = 0, 1029 .cra_module = THIS_MODULE, 1030 .cra_init = aspeed_sham_cra_init, 1031 .cra_exit = aspeed_sham_cra_exit, 1032 } 1033 } 1034 }, 1035 }, 1036 { 1037 .alg_base = "sha224", 1038 .alg.ahash = { 1039 .init = aspeed_sham_init, 1040 .update = aspeed_sham_update, 1041 .final = aspeed_sham_final, 1042 .finup = aspeed_sham_finup, 1043 .digest = aspeed_sham_digest, 1044 .setkey = aspeed_sham_setkey, 1045 .export = aspeed_sham_export, 1046 .import = aspeed_sham_import, 1047 .halg = { 1048 .digestsize = SHA224_DIGEST_SIZE, 1049 .statesize = sizeof(struct aspeed_sham_reqctx), 1050 .base = { 1051 .cra_name = "hmac(sha224)", 1052 .cra_driver_name = "aspeed-hmac-sha224", 1053 .cra_priority = 300, 1054 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1055 CRYPTO_ALG_ASYNC | 1056 CRYPTO_ALG_KERN_DRIVER_ONLY, 1057 .cra_blocksize = SHA224_BLOCK_SIZE, 1058 .cra_ctxsize = sizeof(struct aspeed_sham_ctx) + 1059 sizeof(struct aspeed_sha_hmac_ctx), 1060 .cra_alignmask = 0, 1061 .cra_module = THIS_MODULE, 1062 .cra_init = aspeed_sham_cra_init, 1063 .cra_exit = aspeed_sham_cra_exit, 1064 } 1065 } 1066 }, 1067 }, 1068 { 1069 .alg_base = "sha256", 1070 .alg.ahash = { 1071 .init = aspeed_sham_init, 1072 .update = aspeed_sham_update, 1073 .final = aspeed_sham_final, 1074 .finup = aspeed_sham_finup, 1075 .digest = aspeed_sham_digest, 1076 .setkey = aspeed_sham_setkey, 1077 .export = aspeed_sham_export, 1078 .import = aspeed_sham_import, 1079 .halg = { 1080 .digestsize = SHA256_DIGEST_SIZE, 1081 .statesize = sizeof(struct aspeed_sham_reqctx), 1082 .base = { 1083 .cra_name = "hmac(sha256)", 1084 .cra_driver_name = "aspeed-hmac-sha256", 1085 .cra_priority = 300, 1086 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1087 CRYPTO_ALG_ASYNC | 1088 CRYPTO_ALG_KERN_DRIVER_ONLY, 1089 .cra_blocksize = SHA256_BLOCK_SIZE, 1090 .cra_ctxsize = sizeof(struct aspeed_sham_ctx) + 1091 sizeof(struct aspeed_sha_hmac_ctx), 1092 .cra_alignmask = 0, 1093 .cra_module = THIS_MODULE, 1094 .cra_init = aspeed_sham_cra_init, 1095 .cra_exit = aspeed_sham_cra_exit, 1096 } 1097 } 1098 }, 1099 }, 1100 }; 1101 1102 struct aspeed_hace_alg aspeed_ahash_algs_g6[] = { 1103 { 1104 .alg.ahash = { 1105 .init = aspeed_sham_init, 1106 .update = aspeed_sham_update, 1107 .final = aspeed_sham_final, 1108 .finup = aspeed_sham_finup, 1109 .digest = aspeed_sham_digest, 1110 .export = aspeed_sham_export, 1111 .import = aspeed_sham_import, 1112 .halg = { 1113 .digestsize = SHA384_DIGEST_SIZE, 1114 .statesize = sizeof(struct aspeed_sham_reqctx), 1115 .base = { 1116 .cra_name = "sha384", 1117 .cra_driver_name = "aspeed-sha384", 1118 .cra_priority = 300, 1119 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1120 CRYPTO_ALG_ASYNC | 1121 CRYPTO_ALG_KERN_DRIVER_ONLY, 1122 .cra_blocksize = SHA384_BLOCK_SIZE, 1123 .cra_ctxsize = sizeof(struct aspeed_sham_ctx), 1124 .cra_alignmask = 0, 1125 .cra_module = THIS_MODULE, 1126 .cra_init = aspeed_sham_cra_init, 1127 .cra_exit = aspeed_sham_cra_exit, 1128 } 1129 } 1130 }, 1131 }, 1132 { 1133 .alg.ahash = { 1134 .init = aspeed_sham_init, 1135 .update = aspeed_sham_update, 1136 .final = aspeed_sham_final, 1137 .finup = aspeed_sham_finup, 1138 .digest = aspeed_sham_digest, 1139 .export = aspeed_sham_export, 1140 .import = aspeed_sham_import, 1141 .halg = { 1142 .digestsize = SHA512_DIGEST_SIZE, 1143 .statesize = sizeof(struct aspeed_sham_reqctx), 1144 .base = { 1145 .cra_name = "sha512", 1146 .cra_driver_name = "aspeed-sha512", 1147 .cra_priority = 300, 1148 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1149 CRYPTO_ALG_ASYNC | 1150 CRYPTO_ALG_KERN_DRIVER_ONLY, 1151 .cra_blocksize = SHA512_BLOCK_SIZE, 1152 .cra_ctxsize = sizeof(struct aspeed_sham_ctx), 1153 .cra_alignmask = 0, 1154 .cra_module = THIS_MODULE, 1155 .cra_init = aspeed_sham_cra_init, 1156 .cra_exit = aspeed_sham_cra_exit, 1157 } 1158 } 1159 }, 1160 }, 1161 { 1162 .alg.ahash = { 1163 .init = aspeed_sha512s_init, 1164 .update = aspeed_sham_update, 1165 .final = aspeed_sham_final, 1166 .finup = aspeed_sham_finup, 1167 .digest = aspeed_sham_digest, 1168 .export = aspeed_sham_export, 1169 .import = aspeed_sham_import, 1170 .halg = { 1171 .digestsize = SHA224_DIGEST_SIZE, 1172 .statesize = sizeof(struct aspeed_sham_reqctx), 1173 .base = { 1174 .cra_name = "sha512_224", 1175 .cra_driver_name = "aspeed-sha512_224", 1176 .cra_priority = 300, 1177 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1178 CRYPTO_ALG_ASYNC | 1179 CRYPTO_ALG_KERN_DRIVER_ONLY, 1180 .cra_blocksize = SHA512_BLOCK_SIZE, 1181 .cra_ctxsize = sizeof(struct aspeed_sham_ctx), 1182 .cra_alignmask = 0, 1183 .cra_module = THIS_MODULE, 1184 .cra_init = aspeed_sham_cra_init, 1185 .cra_exit = aspeed_sham_cra_exit, 1186 } 1187 } 1188 }, 1189 }, 1190 { 1191 .alg.ahash = { 1192 .init = aspeed_sha512s_init, 1193 .update = aspeed_sham_update, 1194 .final = aspeed_sham_final, 1195 .finup = aspeed_sham_finup, 1196 .digest = aspeed_sham_digest, 1197 .export = aspeed_sham_export, 1198 .import = aspeed_sham_import, 1199 .halg = { 1200 .digestsize = SHA256_DIGEST_SIZE, 1201 .statesize = sizeof(struct aspeed_sham_reqctx), 1202 .base = { 1203 .cra_name = "sha512_256", 1204 .cra_driver_name = "aspeed-sha512_256", 1205 .cra_priority = 300, 1206 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1207 CRYPTO_ALG_ASYNC | 1208 CRYPTO_ALG_KERN_DRIVER_ONLY, 1209 .cra_blocksize = SHA512_BLOCK_SIZE, 1210 .cra_ctxsize = sizeof(struct aspeed_sham_ctx), 1211 .cra_alignmask = 0, 1212 .cra_module = THIS_MODULE, 1213 .cra_init = aspeed_sham_cra_init, 1214 .cra_exit = aspeed_sham_cra_exit, 1215 } 1216 } 1217 }, 1218 }, 1219 { 1220 .alg_base = "sha384", 1221 .alg.ahash = { 1222 .init = aspeed_sham_init, 1223 .update = aspeed_sham_update, 1224 .final = aspeed_sham_final, 1225 .finup = aspeed_sham_finup, 1226 .digest = aspeed_sham_digest, 1227 .setkey = aspeed_sham_setkey, 1228 .export = aspeed_sham_export, 1229 .import = aspeed_sham_import, 1230 .halg = { 1231 .digestsize = SHA384_DIGEST_SIZE, 1232 .statesize = sizeof(struct aspeed_sham_reqctx), 1233 .base = { 1234 .cra_name = "hmac(sha384)", 1235 .cra_driver_name = "aspeed-hmac-sha384", 1236 .cra_priority = 300, 1237 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1238 CRYPTO_ALG_ASYNC | 1239 CRYPTO_ALG_KERN_DRIVER_ONLY, 1240 .cra_blocksize = SHA384_BLOCK_SIZE, 1241 .cra_ctxsize = sizeof(struct aspeed_sham_ctx) + 1242 sizeof(struct aspeed_sha_hmac_ctx), 1243 .cra_alignmask = 0, 1244 .cra_module = THIS_MODULE, 1245 .cra_init = aspeed_sham_cra_init, 1246 .cra_exit = aspeed_sham_cra_exit, 1247 } 1248 } 1249 }, 1250 }, 1251 { 1252 .alg_base = "sha512", 1253 .alg.ahash = { 1254 .init = aspeed_sham_init, 1255 .update = aspeed_sham_update, 1256 .final = aspeed_sham_final, 1257 .finup = aspeed_sham_finup, 1258 .digest = aspeed_sham_digest, 1259 .setkey = aspeed_sham_setkey, 1260 .export = aspeed_sham_export, 1261 .import = aspeed_sham_import, 1262 .halg = { 1263 .digestsize = SHA512_DIGEST_SIZE, 1264 .statesize = sizeof(struct aspeed_sham_reqctx), 1265 .base = { 1266 .cra_name = "hmac(sha512)", 1267 .cra_driver_name = "aspeed-hmac-sha512", 1268 .cra_priority = 300, 1269 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1270 CRYPTO_ALG_ASYNC | 1271 CRYPTO_ALG_KERN_DRIVER_ONLY, 1272 .cra_blocksize = SHA512_BLOCK_SIZE, 1273 .cra_ctxsize = sizeof(struct aspeed_sham_ctx) + 1274 sizeof(struct aspeed_sha_hmac_ctx), 1275 .cra_alignmask = 0, 1276 .cra_module = THIS_MODULE, 1277 .cra_init = aspeed_sham_cra_init, 1278 .cra_exit = aspeed_sham_cra_exit, 1279 } 1280 } 1281 }, 1282 }, 1283 { 1284 .alg_base = "sha512_224", 1285 .alg.ahash = { 1286 .init = aspeed_sha512s_init, 1287 .update = aspeed_sham_update, 1288 .final = aspeed_sham_final, 1289 .finup = aspeed_sham_finup, 1290 .digest = aspeed_sham_digest, 1291 .setkey = aspeed_sham_setkey, 1292 .export = aspeed_sham_export, 1293 .import = aspeed_sham_import, 1294 .halg = { 1295 .digestsize = SHA224_DIGEST_SIZE, 1296 .statesize = sizeof(struct aspeed_sham_reqctx), 1297 .base = { 1298 .cra_name = "hmac(sha512_224)", 1299 .cra_driver_name = "aspeed-hmac-sha512_224", 1300 .cra_priority = 300, 1301 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1302 CRYPTO_ALG_ASYNC | 1303 CRYPTO_ALG_KERN_DRIVER_ONLY, 1304 .cra_blocksize = SHA512_BLOCK_SIZE, 1305 .cra_ctxsize = sizeof(struct aspeed_sham_ctx) + 1306 sizeof(struct aspeed_sha_hmac_ctx), 1307 .cra_alignmask = 0, 1308 .cra_module = THIS_MODULE, 1309 .cra_init = aspeed_sham_cra_init, 1310 .cra_exit = aspeed_sham_cra_exit, 1311 } 1312 } 1313 }, 1314 }, 1315 { 1316 .alg_base = "sha512_256", 1317 .alg.ahash = { 1318 .init = aspeed_sha512s_init, 1319 .update = aspeed_sham_update, 1320 .final = aspeed_sham_final, 1321 .finup = aspeed_sham_finup, 1322 .digest = aspeed_sham_digest, 1323 .setkey = aspeed_sham_setkey, 1324 .export = aspeed_sham_export, 1325 .import = aspeed_sham_import, 1326 .halg = { 1327 .digestsize = SHA256_DIGEST_SIZE, 1328 .statesize = sizeof(struct aspeed_sham_reqctx), 1329 .base = { 1330 .cra_name = "hmac(sha512_256)", 1331 .cra_driver_name = "aspeed-hmac-sha512_256", 1332 .cra_priority = 300, 1333 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1334 CRYPTO_ALG_ASYNC | 1335 CRYPTO_ALG_KERN_DRIVER_ONLY, 1336 .cra_blocksize = SHA512_BLOCK_SIZE, 1337 .cra_ctxsize = sizeof(struct aspeed_sham_ctx) + 1338 sizeof(struct aspeed_sha_hmac_ctx), 1339 .cra_alignmask = 0, 1340 .cra_module = THIS_MODULE, 1341 .cra_init = aspeed_sham_cra_init, 1342 .cra_exit = aspeed_sham_cra_exit, 1343 } 1344 } 1345 }, 1346 }, 1347 }; 1348 1349 void aspeed_unregister_hace_hash_algs(struct aspeed_hace_dev *hace_dev) 1350 { 1351 int i; 1352 1353 for (i = 0; i < ARRAY_SIZE(aspeed_ahash_algs); i++) 1354 crypto_unregister_ahash(&aspeed_ahash_algs[i].alg.ahash); 1355 1356 if (hace_dev->version != AST2600_VERSION) 1357 return; 1358 1359 for (i = 0; i < ARRAY_SIZE(aspeed_ahash_algs_g6); i++) 1360 crypto_unregister_ahash(&aspeed_ahash_algs_g6[i].alg.ahash); 1361 } 1362 1363 void aspeed_register_hace_hash_algs(struct aspeed_hace_dev *hace_dev) 1364 { 1365 int rc, i; 1366 1367 AHASH_DBG(hace_dev, "\n"); 1368 1369 for (i = 0; i < ARRAY_SIZE(aspeed_ahash_algs); i++) { 1370 aspeed_ahash_algs[i].hace_dev = hace_dev; 1371 rc = crypto_register_ahash(&aspeed_ahash_algs[i].alg.ahash); 1372 if (rc) { 1373 AHASH_DBG(hace_dev, "Failed to register %s\n", 1374 aspeed_ahash_algs[i].alg.ahash.halg.base.cra_name); 1375 } 1376 } 1377 1378 if (hace_dev->version != AST2600_VERSION) 1379 return; 1380 1381 for (i = 0; i < ARRAY_SIZE(aspeed_ahash_algs_g6); i++) { 1382 aspeed_ahash_algs_g6[i].hace_dev = hace_dev; 1383 rc = crypto_register_ahash(&aspeed_ahash_algs_g6[i].alg.ahash); 1384 if (rc) { 1385 AHASH_DBG(hace_dev, "Failed to register %s\n", 1386 aspeed_ahash_algs_g6[i].alg.ahash.halg.base.cra_name); 1387 } 1388 } 1389 } 1390