1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2021 Aspeed Technology Inc. 4 */ 5 6 #include "aspeed-hace.h" 7 8 #ifdef CONFIG_CRYPTO_DEV_ASPEED_DEBUG 9 #define AHASH_DBG(h, fmt, ...) \ 10 dev_info((h)->dev, "%s() " fmt, __func__, ##__VA_ARGS__) 11 #else 12 #define AHASH_DBG(h, fmt, ...) \ 13 dev_dbg((h)->dev, "%s() " fmt, __func__, ##__VA_ARGS__) 14 #endif 15 16 /* Initialization Vectors for SHA-family */ 17 static const __be32 sha1_iv[8] = { 18 cpu_to_be32(SHA1_H0), cpu_to_be32(SHA1_H1), 19 cpu_to_be32(SHA1_H2), cpu_to_be32(SHA1_H3), 20 cpu_to_be32(SHA1_H4), 0, 0, 0 21 }; 22 23 static const __be32 sha224_iv[8] = { 24 cpu_to_be32(SHA224_H0), cpu_to_be32(SHA224_H1), 25 cpu_to_be32(SHA224_H2), cpu_to_be32(SHA224_H3), 26 cpu_to_be32(SHA224_H4), cpu_to_be32(SHA224_H5), 27 cpu_to_be32(SHA224_H6), cpu_to_be32(SHA224_H7), 28 }; 29 30 static const __be32 sha256_iv[8] = { 31 cpu_to_be32(SHA256_H0), cpu_to_be32(SHA256_H1), 32 cpu_to_be32(SHA256_H2), cpu_to_be32(SHA256_H3), 33 cpu_to_be32(SHA256_H4), cpu_to_be32(SHA256_H5), 34 cpu_to_be32(SHA256_H6), cpu_to_be32(SHA256_H7), 35 }; 36 37 static const __be64 sha384_iv[8] = { 38 cpu_to_be64(SHA384_H0), cpu_to_be64(SHA384_H1), 39 cpu_to_be64(SHA384_H2), cpu_to_be64(SHA384_H3), 40 cpu_to_be64(SHA384_H4), cpu_to_be64(SHA384_H5), 41 cpu_to_be64(SHA384_H6), cpu_to_be64(SHA384_H7) 42 }; 43 44 static const __be64 sha512_iv[8] = { 45 cpu_to_be64(SHA512_H0), cpu_to_be64(SHA512_H1), 46 cpu_to_be64(SHA512_H2), cpu_to_be64(SHA512_H3), 47 cpu_to_be64(SHA512_H4), cpu_to_be64(SHA512_H5), 48 cpu_to_be64(SHA512_H6), cpu_to_be64(SHA512_H7) 49 }; 50 51 static const __be32 sha512_224_iv[16] = { 52 cpu_to_be32(0xC8373D8CUL), cpu_to_be32(0xA24D5419UL), 53 cpu_to_be32(0x6699E173UL), cpu_to_be32(0xD6D4DC89UL), 54 cpu_to_be32(0xAEB7FA1DUL), cpu_to_be32(0x829CFF32UL), 55 cpu_to_be32(0x14D59D67UL), cpu_to_be32(0xCF9F2F58UL), 56 cpu_to_be32(0x692B6D0FUL), cpu_to_be32(0xA84DD47BUL), 57 cpu_to_be32(0x736FE377UL), cpu_to_be32(0x4289C404UL), 58 cpu_to_be32(0xA8859D3FUL), cpu_to_be32(0xC8361D6AUL), 59 cpu_to_be32(0xADE61211UL), cpu_to_be32(0xA192D691UL) 60 }; 61 62 static const __be32 sha512_256_iv[16] = { 63 cpu_to_be32(0x94213122UL), cpu_to_be32(0x2CF72BFCUL), 64 cpu_to_be32(0xA35F559FUL), cpu_to_be32(0xC2644CC8UL), 65 cpu_to_be32(0x6BB89323UL), cpu_to_be32(0x51B1536FUL), 66 cpu_to_be32(0x19773896UL), cpu_to_be32(0xBDEA4059UL), 67 cpu_to_be32(0xE23E2896UL), cpu_to_be32(0xE3FF8EA8UL), 68 cpu_to_be32(0x251E5EBEUL), cpu_to_be32(0x92398653UL), 69 cpu_to_be32(0xFC99012BUL), cpu_to_be32(0xAAB8852CUL), 70 cpu_to_be32(0xDC2DB70EUL), cpu_to_be32(0xA22CC581UL) 71 }; 72 73 /* The purpose of this padding is to ensure that the padded message is a 74 * multiple of 512 bits (SHA1/SHA224/SHA256) or 1024 bits (SHA384/SHA512). 75 * The bit "1" is appended at the end of the message followed by 76 * "padlen-1" zero bits. Then a 64 bits block (SHA1/SHA224/SHA256) or 77 * 128 bits block (SHA384/SHA512) equals to the message length in bits 78 * is appended. 79 * 80 * For SHA1/SHA224/SHA256, padlen is calculated as followed: 81 * - if message length < 56 bytes then padlen = 56 - message length 82 * - else padlen = 64 + 56 - message length 83 * 84 * For SHA384/SHA512, padlen is calculated as followed: 85 * - if message length < 112 bytes then padlen = 112 - message length 86 * - else padlen = 128 + 112 - message length 87 */ 88 static void aspeed_ahash_fill_padding(struct aspeed_hace_dev *hace_dev, 89 struct aspeed_sham_reqctx *rctx) 90 { 91 unsigned int index, padlen; 92 __be64 bits[2]; 93 94 AHASH_DBG(hace_dev, "rctx flags:0x%x\n", (u32)rctx->flags); 95 96 switch (rctx->flags & SHA_FLAGS_MASK) { 97 case SHA_FLAGS_SHA1: 98 case SHA_FLAGS_SHA224: 99 case SHA_FLAGS_SHA256: 100 bits[0] = cpu_to_be64(rctx->digcnt[0] << 3); 101 index = rctx->bufcnt & 0x3f; 102 padlen = (index < 56) ? (56 - index) : ((64 + 56) - index); 103 *(rctx->buffer + rctx->bufcnt) = 0x80; 104 memset(rctx->buffer + rctx->bufcnt + 1, 0, padlen - 1); 105 memcpy(rctx->buffer + rctx->bufcnt + padlen, bits, 8); 106 rctx->bufcnt += padlen + 8; 107 break; 108 default: 109 bits[1] = cpu_to_be64(rctx->digcnt[0] << 3); 110 bits[0] = cpu_to_be64(rctx->digcnt[1] << 3 | 111 rctx->digcnt[0] >> 61); 112 index = rctx->bufcnt & 0x7f; 113 padlen = (index < 112) ? (112 - index) : ((128 + 112) - index); 114 *(rctx->buffer + rctx->bufcnt) = 0x80; 115 memset(rctx->buffer + rctx->bufcnt + 1, 0, padlen - 1); 116 memcpy(rctx->buffer + rctx->bufcnt + padlen, bits, 16); 117 rctx->bufcnt += padlen + 16; 118 break; 119 } 120 } 121 122 /* 123 * Prepare DMA buffer before hardware engine 124 * processing. 125 */ 126 static int aspeed_ahash_dma_prepare(struct aspeed_hace_dev *hace_dev) 127 { 128 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine; 129 struct ahash_request *req = hash_engine->req; 130 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 131 int length, remain; 132 133 length = rctx->total + rctx->bufcnt; 134 remain = length % rctx->block_size; 135 136 AHASH_DBG(hace_dev, "length:0x%x, remain:0x%x\n", length, remain); 137 138 if (rctx->bufcnt) 139 memcpy(hash_engine->ahash_src_addr, rctx->buffer, rctx->bufcnt); 140 141 if (rctx->total + rctx->bufcnt < ASPEED_CRYPTO_SRC_DMA_BUF_LEN) { 142 scatterwalk_map_and_copy(hash_engine->ahash_src_addr + 143 rctx->bufcnt, rctx->src_sg, 144 rctx->offset, rctx->total - remain, 0); 145 rctx->offset += rctx->total - remain; 146 147 } else { 148 dev_warn(hace_dev->dev, "Hash data length is too large\n"); 149 return -EINVAL; 150 } 151 152 scatterwalk_map_and_copy(rctx->buffer, rctx->src_sg, 153 rctx->offset, remain, 0); 154 155 rctx->bufcnt = remain; 156 rctx->digest_dma_addr = dma_map_single(hace_dev->dev, rctx->digest, 157 SHA512_DIGEST_SIZE, 158 DMA_BIDIRECTIONAL); 159 if (dma_mapping_error(hace_dev->dev, rctx->digest_dma_addr)) { 160 dev_warn(hace_dev->dev, "dma_map() rctx digest error\n"); 161 return -ENOMEM; 162 } 163 164 hash_engine->src_length = length - remain; 165 hash_engine->src_dma = hash_engine->ahash_src_dma_addr; 166 hash_engine->digest_dma = rctx->digest_dma_addr; 167 168 return 0; 169 } 170 171 /* 172 * Prepare DMA buffer as SG list buffer before 173 * hardware engine processing. 174 */ 175 static int aspeed_ahash_dma_prepare_sg(struct aspeed_hace_dev *hace_dev) 176 { 177 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine; 178 struct ahash_request *req = hash_engine->req; 179 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 180 struct aspeed_sg_list *src_list; 181 struct scatterlist *s; 182 int length, remain, sg_len, i; 183 int rc = 0; 184 185 remain = (rctx->total + rctx->bufcnt) % rctx->block_size; 186 length = rctx->total + rctx->bufcnt - remain; 187 188 AHASH_DBG(hace_dev, "%s:0x%x, %s:%zu, %s:0x%x, %s:0x%x\n", 189 "rctx total", rctx->total, "bufcnt", rctx->bufcnt, 190 "length", length, "remain", remain); 191 192 sg_len = dma_map_sg(hace_dev->dev, rctx->src_sg, rctx->src_nents, 193 DMA_TO_DEVICE); 194 if (!sg_len) { 195 dev_warn(hace_dev->dev, "dma_map_sg() src error\n"); 196 rc = -ENOMEM; 197 goto end; 198 } 199 200 src_list = (struct aspeed_sg_list *)hash_engine->ahash_src_addr; 201 rctx->digest_dma_addr = dma_map_single(hace_dev->dev, rctx->digest, 202 SHA512_DIGEST_SIZE, 203 DMA_BIDIRECTIONAL); 204 if (dma_mapping_error(hace_dev->dev, rctx->digest_dma_addr)) { 205 dev_warn(hace_dev->dev, "dma_map() rctx digest error\n"); 206 rc = -ENOMEM; 207 goto free_src_sg; 208 } 209 210 if (rctx->bufcnt != 0) { 211 u32 phy_addr; 212 u32 len; 213 214 rctx->buffer_dma_addr = dma_map_single(hace_dev->dev, 215 rctx->buffer, 216 rctx->block_size * 2, 217 DMA_TO_DEVICE); 218 if (dma_mapping_error(hace_dev->dev, rctx->buffer_dma_addr)) { 219 dev_warn(hace_dev->dev, "dma_map() rctx buffer error\n"); 220 rc = -ENOMEM; 221 goto free_rctx_digest; 222 } 223 224 phy_addr = rctx->buffer_dma_addr; 225 len = rctx->bufcnt; 226 length -= len; 227 228 /* Last sg list */ 229 if (length == 0) 230 len |= HASH_SG_LAST_LIST; 231 232 src_list[0].phy_addr = cpu_to_le32(phy_addr); 233 src_list[0].len = cpu_to_le32(len); 234 src_list++; 235 } 236 237 if (length != 0) { 238 for_each_sg(rctx->src_sg, s, sg_len, i) { 239 u32 phy_addr = sg_dma_address(s); 240 u32 len = sg_dma_len(s); 241 242 if (length > len) 243 length -= len; 244 else { 245 /* Last sg list */ 246 len = length; 247 len |= HASH_SG_LAST_LIST; 248 length = 0; 249 } 250 251 src_list[i].phy_addr = cpu_to_le32(phy_addr); 252 src_list[i].len = cpu_to_le32(len); 253 } 254 } 255 256 if (length != 0) { 257 rc = -EINVAL; 258 goto free_rctx_buffer; 259 } 260 261 rctx->offset = rctx->total - remain; 262 hash_engine->src_length = rctx->total + rctx->bufcnt - remain; 263 hash_engine->src_dma = hash_engine->ahash_src_dma_addr; 264 hash_engine->digest_dma = rctx->digest_dma_addr; 265 266 return 0; 267 268 free_rctx_buffer: 269 if (rctx->bufcnt != 0) 270 dma_unmap_single(hace_dev->dev, rctx->buffer_dma_addr, 271 rctx->block_size * 2, DMA_TO_DEVICE); 272 free_rctx_digest: 273 dma_unmap_single(hace_dev->dev, rctx->digest_dma_addr, 274 SHA512_DIGEST_SIZE, DMA_BIDIRECTIONAL); 275 free_src_sg: 276 dma_unmap_sg(hace_dev->dev, rctx->src_sg, rctx->src_nents, 277 DMA_TO_DEVICE); 278 end: 279 return rc; 280 } 281 282 static int aspeed_ahash_complete(struct aspeed_hace_dev *hace_dev) 283 { 284 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine; 285 struct ahash_request *req = hash_engine->req; 286 287 AHASH_DBG(hace_dev, "\n"); 288 289 hash_engine->flags &= ~CRYPTO_FLAGS_BUSY; 290 291 crypto_finalize_hash_request(hace_dev->crypt_engine_hash, req, 0); 292 293 return 0; 294 } 295 296 /* 297 * Copy digest to the corresponding request result. 298 * This function will be called at final() stage. 299 */ 300 static int aspeed_ahash_transfer(struct aspeed_hace_dev *hace_dev) 301 { 302 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine; 303 struct ahash_request *req = hash_engine->req; 304 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 305 306 AHASH_DBG(hace_dev, "\n"); 307 308 dma_unmap_single(hace_dev->dev, rctx->digest_dma_addr, 309 SHA512_DIGEST_SIZE, DMA_BIDIRECTIONAL); 310 311 dma_unmap_single(hace_dev->dev, rctx->buffer_dma_addr, 312 rctx->block_size * 2, DMA_TO_DEVICE); 313 314 memcpy(req->result, rctx->digest, rctx->digsize); 315 316 return aspeed_ahash_complete(hace_dev); 317 } 318 319 /* 320 * Trigger hardware engines to do the math. 321 */ 322 static int aspeed_hace_ahash_trigger(struct aspeed_hace_dev *hace_dev, 323 aspeed_hace_fn_t resume) 324 { 325 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine; 326 struct ahash_request *req = hash_engine->req; 327 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 328 329 AHASH_DBG(hace_dev, "src_dma:%pad, digest_dma:%pad, length:%zu\n", 330 &hash_engine->src_dma, &hash_engine->digest_dma, 331 hash_engine->src_length); 332 333 rctx->cmd |= HASH_CMD_INT_ENABLE; 334 hash_engine->resume = resume; 335 336 ast_hace_write(hace_dev, hash_engine->src_dma, ASPEED_HACE_HASH_SRC); 337 ast_hace_write(hace_dev, hash_engine->digest_dma, 338 ASPEED_HACE_HASH_DIGEST_BUFF); 339 ast_hace_write(hace_dev, hash_engine->digest_dma, 340 ASPEED_HACE_HASH_KEY_BUFF); 341 ast_hace_write(hace_dev, hash_engine->src_length, 342 ASPEED_HACE_HASH_DATA_LEN); 343 344 /* Memory barrier to ensure all data setup before engine starts */ 345 mb(); 346 347 ast_hace_write(hace_dev, rctx->cmd, ASPEED_HACE_HASH_CMD); 348 349 return -EINPROGRESS; 350 } 351 352 /* 353 * HMAC resume aims to do the second pass produces 354 * the final HMAC code derived from the inner hash 355 * result and the outer key. 356 */ 357 static int aspeed_ahash_hmac_resume(struct aspeed_hace_dev *hace_dev) 358 { 359 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine; 360 struct ahash_request *req = hash_engine->req; 361 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 362 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 363 struct aspeed_sham_ctx *tctx = crypto_ahash_ctx(tfm); 364 struct aspeed_sha_hmac_ctx *bctx = tctx->base; 365 int rc = 0; 366 367 AHASH_DBG(hace_dev, "\n"); 368 369 dma_unmap_single(hace_dev->dev, rctx->digest_dma_addr, 370 SHA512_DIGEST_SIZE, DMA_BIDIRECTIONAL); 371 372 dma_unmap_single(hace_dev->dev, rctx->buffer_dma_addr, 373 rctx->block_size * 2, DMA_TO_DEVICE); 374 375 /* o key pad + hash sum 1 */ 376 memcpy(rctx->buffer, bctx->opad, rctx->block_size); 377 memcpy(rctx->buffer + rctx->block_size, rctx->digest, rctx->digsize); 378 379 rctx->bufcnt = rctx->block_size + rctx->digsize; 380 rctx->digcnt[0] = rctx->block_size + rctx->digsize; 381 382 aspeed_ahash_fill_padding(hace_dev, rctx); 383 memcpy(rctx->digest, rctx->sha_iv, rctx->ivsize); 384 385 rctx->digest_dma_addr = dma_map_single(hace_dev->dev, rctx->digest, 386 SHA512_DIGEST_SIZE, 387 DMA_BIDIRECTIONAL); 388 if (dma_mapping_error(hace_dev->dev, rctx->digest_dma_addr)) { 389 dev_warn(hace_dev->dev, "dma_map() rctx digest error\n"); 390 rc = -ENOMEM; 391 goto end; 392 } 393 394 rctx->buffer_dma_addr = dma_map_single(hace_dev->dev, rctx->buffer, 395 rctx->block_size * 2, 396 DMA_TO_DEVICE); 397 if (dma_mapping_error(hace_dev->dev, rctx->buffer_dma_addr)) { 398 dev_warn(hace_dev->dev, "dma_map() rctx buffer error\n"); 399 rc = -ENOMEM; 400 goto free_rctx_digest; 401 } 402 403 hash_engine->src_dma = rctx->buffer_dma_addr; 404 hash_engine->src_length = rctx->bufcnt; 405 hash_engine->digest_dma = rctx->digest_dma_addr; 406 407 return aspeed_hace_ahash_trigger(hace_dev, aspeed_ahash_transfer); 408 409 free_rctx_digest: 410 dma_unmap_single(hace_dev->dev, rctx->digest_dma_addr, 411 SHA512_DIGEST_SIZE, DMA_BIDIRECTIONAL); 412 end: 413 return rc; 414 } 415 416 static int aspeed_ahash_req_final(struct aspeed_hace_dev *hace_dev) 417 { 418 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine; 419 struct ahash_request *req = hash_engine->req; 420 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 421 int rc = 0; 422 423 AHASH_DBG(hace_dev, "\n"); 424 425 aspeed_ahash_fill_padding(hace_dev, rctx); 426 427 rctx->digest_dma_addr = dma_map_single(hace_dev->dev, 428 rctx->digest, 429 SHA512_DIGEST_SIZE, 430 DMA_BIDIRECTIONAL); 431 if (dma_mapping_error(hace_dev->dev, rctx->digest_dma_addr)) { 432 dev_warn(hace_dev->dev, "dma_map() rctx digest error\n"); 433 rc = -ENOMEM; 434 goto end; 435 } 436 437 rctx->buffer_dma_addr = dma_map_single(hace_dev->dev, 438 rctx->buffer, 439 rctx->block_size * 2, 440 DMA_TO_DEVICE); 441 if (dma_mapping_error(hace_dev->dev, rctx->buffer_dma_addr)) { 442 dev_warn(hace_dev->dev, "dma_map() rctx buffer error\n"); 443 rc = -ENOMEM; 444 goto free_rctx_digest; 445 } 446 447 hash_engine->src_dma = rctx->buffer_dma_addr; 448 hash_engine->src_length = rctx->bufcnt; 449 hash_engine->digest_dma = rctx->digest_dma_addr; 450 451 if (rctx->flags & SHA_FLAGS_HMAC) 452 return aspeed_hace_ahash_trigger(hace_dev, 453 aspeed_ahash_hmac_resume); 454 455 return aspeed_hace_ahash_trigger(hace_dev, aspeed_ahash_transfer); 456 457 free_rctx_digest: 458 dma_unmap_single(hace_dev->dev, rctx->digest_dma_addr, 459 SHA512_DIGEST_SIZE, DMA_BIDIRECTIONAL); 460 end: 461 return rc; 462 } 463 464 static int aspeed_ahash_update_resume_sg(struct aspeed_hace_dev *hace_dev) 465 { 466 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine; 467 struct ahash_request *req = hash_engine->req; 468 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 469 470 AHASH_DBG(hace_dev, "\n"); 471 472 dma_unmap_sg(hace_dev->dev, rctx->src_sg, rctx->src_nents, 473 DMA_TO_DEVICE); 474 475 if (rctx->bufcnt != 0) 476 dma_unmap_single(hace_dev->dev, rctx->buffer_dma_addr, 477 rctx->block_size * 2, 478 DMA_TO_DEVICE); 479 480 dma_unmap_single(hace_dev->dev, rctx->digest_dma_addr, 481 SHA512_DIGEST_SIZE, DMA_BIDIRECTIONAL); 482 483 scatterwalk_map_and_copy(rctx->buffer, rctx->src_sg, rctx->offset, 484 rctx->total - rctx->offset, 0); 485 486 rctx->bufcnt = rctx->total - rctx->offset; 487 rctx->cmd &= ~HASH_CMD_HASH_SRC_SG_CTRL; 488 489 if (rctx->flags & SHA_FLAGS_FINUP) 490 return aspeed_ahash_req_final(hace_dev); 491 492 return aspeed_ahash_complete(hace_dev); 493 } 494 495 static int aspeed_ahash_update_resume(struct aspeed_hace_dev *hace_dev) 496 { 497 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine; 498 struct ahash_request *req = hash_engine->req; 499 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 500 501 AHASH_DBG(hace_dev, "\n"); 502 503 dma_unmap_single(hace_dev->dev, rctx->digest_dma_addr, 504 SHA512_DIGEST_SIZE, DMA_BIDIRECTIONAL); 505 506 if (rctx->flags & SHA_FLAGS_FINUP) 507 return aspeed_ahash_req_final(hace_dev); 508 509 return aspeed_ahash_complete(hace_dev); 510 } 511 512 static int aspeed_ahash_req_update(struct aspeed_hace_dev *hace_dev) 513 { 514 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine; 515 struct ahash_request *req = hash_engine->req; 516 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 517 aspeed_hace_fn_t resume; 518 int ret; 519 520 AHASH_DBG(hace_dev, "\n"); 521 522 if (hace_dev->version == AST2600_VERSION) { 523 rctx->cmd |= HASH_CMD_HASH_SRC_SG_CTRL; 524 resume = aspeed_ahash_update_resume_sg; 525 526 } else { 527 resume = aspeed_ahash_update_resume; 528 } 529 530 ret = hash_engine->dma_prepare(hace_dev); 531 if (ret) 532 return ret; 533 534 return aspeed_hace_ahash_trigger(hace_dev, resume); 535 } 536 537 static int aspeed_hace_hash_handle_queue(struct aspeed_hace_dev *hace_dev, 538 struct ahash_request *req) 539 { 540 return crypto_transfer_hash_request_to_engine( 541 hace_dev->crypt_engine_hash, req); 542 } 543 544 static int aspeed_ahash_do_request(struct crypto_engine *engine, void *areq) 545 { 546 struct ahash_request *req = ahash_request_cast(areq); 547 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 548 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 549 struct aspeed_sham_ctx *tctx = crypto_ahash_ctx(tfm); 550 struct aspeed_hace_dev *hace_dev = tctx->hace_dev; 551 struct aspeed_engine_hash *hash_engine; 552 int ret = 0; 553 554 hash_engine = &hace_dev->hash_engine; 555 hash_engine->flags |= CRYPTO_FLAGS_BUSY; 556 557 if (rctx->op == SHA_OP_UPDATE) 558 ret = aspeed_ahash_req_update(hace_dev); 559 else if (rctx->op == SHA_OP_FINAL) 560 ret = aspeed_ahash_req_final(hace_dev); 561 562 if (ret != -EINPROGRESS) 563 return ret; 564 565 return 0; 566 } 567 568 static void aspeed_ahash_prepare_request(struct crypto_engine *engine, 569 void *areq) 570 { 571 struct ahash_request *req = ahash_request_cast(areq); 572 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 573 struct aspeed_sham_ctx *tctx = crypto_ahash_ctx(tfm); 574 struct aspeed_hace_dev *hace_dev = tctx->hace_dev; 575 struct aspeed_engine_hash *hash_engine; 576 577 hash_engine = &hace_dev->hash_engine; 578 hash_engine->req = req; 579 580 if (hace_dev->version == AST2600_VERSION) 581 hash_engine->dma_prepare = aspeed_ahash_dma_prepare_sg; 582 else 583 hash_engine->dma_prepare = aspeed_ahash_dma_prepare; 584 } 585 586 static int aspeed_ahash_do_one(struct crypto_engine *engine, void *areq) 587 { 588 aspeed_ahash_prepare_request(engine, areq); 589 return aspeed_ahash_do_request(engine, areq); 590 } 591 592 static int aspeed_sham_update(struct ahash_request *req) 593 { 594 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 595 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 596 struct aspeed_sham_ctx *tctx = crypto_ahash_ctx(tfm); 597 struct aspeed_hace_dev *hace_dev = tctx->hace_dev; 598 599 AHASH_DBG(hace_dev, "req->nbytes: %d\n", req->nbytes); 600 601 rctx->total = req->nbytes; 602 rctx->src_sg = req->src; 603 rctx->offset = 0; 604 rctx->src_nents = sg_nents(req->src); 605 rctx->op = SHA_OP_UPDATE; 606 607 rctx->digcnt[0] += rctx->total; 608 if (rctx->digcnt[0] < rctx->total) 609 rctx->digcnt[1]++; 610 611 if (rctx->bufcnt + rctx->total < rctx->block_size) { 612 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, 613 rctx->src_sg, rctx->offset, 614 rctx->total, 0); 615 rctx->bufcnt += rctx->total; 616 617 return 0; 618 } 619 620 return aspeed_hace_hash_handle_queue(hace_dev, req); 621 } 622 623 static int aspeed_sham_shash_digest(struct crypto_shash *tfm, u32 flags, 624 const u8 *data, unsigned int len, u8 *out) 625 { 626 SHASH_DESC_ON_STACK(shash, tfm); 627 628 shash->tfm = tfm; 629 630 return crypto_shash_digest(shash, data, len, out); 631 } 632 633 static int aspeed_sham_final(struct ahash_request *req) 634 { 635 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 636 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 637 struct aspeed_sham_ctx *tctx = crypto_ahash_ctx(tfm); 638 struct aspeed_hace_dev *hace_dev = tctx->hace_dev; 639 640 AHASH_DBG(hace_dev, "req->nbytes:%d, rctx->total:%d\n", 641 req->nbytes, rctx->total); 642 rctx->op = SHA_OP_FINAL; 643 644 return aspeed_hace_hash_handle_queue(hace_dev, req); 645 } 646 647 static int aspeed_sham_finup(struct ahash_request *req) 648 { 649 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 650 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 651 struct aspeed_sham_ctx *tctx = crypto_ahash_ctx(tfm); 652 struct aspeed_hace_dev *hace_dev = tctx->hace_dev; 653 int rc1, rc2; 654 655 AHASH_DBG(hace_dev, "req->nbytes: %d\n", req->nbytes); 656 657 rctx->flags |= SHA_FLAGS_FINUP; 658 659 rc1 = aspeed_sham_update(req); 660 if (rc1 == -EINPROGRESS || rc1 == -EBUSY) 661 return rc1; 662 663 /* 664 * final() has to be always called to cleanup resources 665 * even if update() failed, except EINPROGRESS 666 */ 667 rc2 = aspeed_sham_final(req); 668 669 return rc1 ? : rc2; 670 } 671 672 static int aspeed_sham_init(struct ahash_request *req) 673 { 674 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 675 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 676 struct aspeed_sham_ctx *tctx = crypto_ahash_ctx(tfm); 677 struct aspeed_hace_dev *hace_dev = tctx->hace_dev; 678 struct aspeed_sha_hmac_ctx *bctx = tctx->base; 679 680 AHASH_DBG(hace_dev, "%s: digest size:%d\n", 681 crypto_tfm_alg_name(&tfm->base), 682 crypto_ahash_digestsize(tfm)); 683 684 rctx->cmd = HASH_CMD_ACC_MODE; 685 rctx->flags = 0; 686 687 switch (crypto_ahash_digestsize(tfm)) { 688 case SHA1_DIGEST_SIZE: 689 rctx->cmd |= HASH_CMD_SHA1 | HASH_CMD_SHA_SWAP; 690 rctx->flags |= SHA_FLAGS_SHA1; 691 rctx->digsize = SHA1_DIGEST_SIZE; 692 rctx->block_size = SHA1_BLOCK_SIZE; 693 rctx->sha_iv = sha1_iv; 694 rctx->ivsize = 32; 695 memcpy(rctx->digest, sha1_iv, rctx->ivsize); 696 break; 697 case SHA224_DIGEST_SIZE: 698 rctx->cmd |= HASH_CMD_SHA224 | HASH_CMD_SHA_SWAP; 699 rctx->flags |= SHA_FLAGS_SHA224; 700 rctx->digsize = SHA224_DIGEST_SIZE; 701 rctx->block_size = SHA224_BLOCK_SIZE; 702 rctx->sha_iv = sha224_iv; 703 rctx->ivsize = 32; 704 memcpy(rctx->digest, sha224_iv, rctx->ivsize); 705 break; 706 case SHA256_DIGEST_SIZE: 707 rctx->cmd |= HASH_CMD_SHA256 | HASH_CMD_SHA_SWAP; 708 rctx->flags |= SHA_FLAGS_SHA256; 709 rctx->digsize = SHA256_DIGEST_SIZE; 710 rctx->block_size = SHA256_BLOCK_SIZE; 711 rctx->sha_iv = sha256_iv; 712 rctx->ivsize = 32; 713 memcpy(rctx->digest, sha256_iv, rctx->ivsize); 714 break; 715 case SHA384_DIGEST_SIZE: 716 rctx->cmd |= HASH_CMD_SHA512_SER | HASH_CMD_SHA384 | 717 HASH_CMD_SHA_SWAP; 718 rctx->flags |= SHA_FLAGS_SHA384; 719 rctx->digsize = SHA384_DIGEST_SIZE; 720 rctx->block_size = SHA384_BLOCK_SIZE; 721 rctx->sha_iv = (const __be32 *)sha384_iv; 722 rctx->ivsize = 64; 723 memcpy(rctx->digest, sha384_iv, rctx->ivsize); 724 break; 725 case SHA512_DIGEST_SIZE: 726 rctx->cmd |= HASH_CMD_SHA512_SER | HASH_CMD_SHA512 | 727 HASH_CMD_SHA_SWAP; 728 rctx->flags |= SHA_FLAGS_SHA512; 729 rctx->digsize = SHA512_DIGEST_SIZE; 730 rctx->block_size = SHA512_BLOCK_SIZE; 731 rctx->sha_iv = (const __be32 *)sha512_iv; 732 rctx->ivsize = 64; 733 memcpy(rctx->digest, sha512_iv, rctx->ivsize); 734 break; 735 default: 736 dev_warn(tctx->hace_dev->dev, "digest size %d not support\n", 737 crypto_ahash_digestsize(tfm)); 738 return -EINVAL; 739 } 740 741 rctx->bufcnt = 0; 742 rctx->total = 0; 743 rctx->digcnt[0] = 0; 744 rctx->digcnt[1] = 0; 745 746 /* HMAC init */ 747 if (tctx->flags & SHA_FLAGS_HMAC) { 748 rctx->digcnt[0] = rctx->block_size; 749 rctx->bufcnt = rctx->block_size; 750 memcpy(rctx->buffer, bctx->ipad, rctx->block_size); 751 rctx->flags |= SHA_FLAGS_HMAC; 752 } 753 754 return 0; 755 } 756 757 static int aspeed_sha512s_init(struct ahash_request *req) 758 { 759 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 760 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 761 struct aspeed_sham_ctx *tctx = crypto_ahash_ctx(tfm); 762 struct aspeed_hace_dev *hace_dev = tctx->hace_dev; 763 struct aspeed_sha_hmac_ctx *bctx = tctx->base; 764 765 AHASH_DBG(hace_dev, "digest size: %d\n", crypto_ahash_digestsize(tfm)); 766 767 rctx->cmd = HASH_CMD_ACC_MODE; 768 rctx->flags = 0; 769 770 switch (crypto_ahash_digestsize(tfm)) { 771 case SHA224_DIGEST_SIZE: 772 rctx->cmd |= HASH_CMD_SHA512_SER | HASH_CMD_SHA512_224 | 773 HASH_CMD_SHA_SWAP; 774 rctx->flags |= SHA_FLAGS_SHA512_224; 775 rctx->digsize = SHA224_DIGEST_SIZE; 776 rctx->block_size = SHA512_BLOCK_SIZE; 777 rctx->sha_iv = sha512_224_iv; 778 rctx->ivsize = 64; 779 memcpy(rctx->digest, sha512_224_iv, rctx->ivsize); 780 break; 781 case SHA256_DIGEST_SIZE: 782 rctx->cmd |= HASH_CMD_SHA512_SER | HASH_CMD_SHA512_256 | 783 HASH_CMD_SHA_SWAP; 784 rctx->flags |= SHA_FLAGS_SHA512_256; 785 rctx->digsize = SHA256_DIGEST_SIZE; 786 rctx->block_size = SHA512_BLOCK_SIZE; 787 rctx->sha_iv = sha512_256_iv; 788 rctx->ivsize = 64; 789 memcpy(rctx->digest, sha512_256_iv, rctx->ivsize); 790 break; 791 default: 792 dev_warn(tctx->hace_dev->dev, "digest size %d not support\n", 793 crypto_ahash_digestsize(tfm)); 794 return -EINVAL; 795 } 796 797 rctx->bufcnt = 0; 798 rctx->total = 0; 799 rctx->digcnt[0] = 0; 800 rctx->digcnt[1] = 0; 801 802 /* HMAC init */ 803 if (tctx->flags & SHA_FLAGS_HMAC) { 804 rctx->digcnt[0] = rctx->block_size; 805 rctx->bufcnt = rctx->block_size; 806 memcpy(rctx->buffer, bctx->ipad, rctx->block_size); 807 rctx->flags |= SHA_FLAGS_HMAC; 808 } 809 810 return 0; 811 } 812 813 static int aspeed_sham_digest(struct ahash_request *req) 814 { 815 return aspeed_sham_init(req) ? : aspeed_sham_finup(req); 816 } 817 818 static int aspeed_sham_setkey(struct crypto_ahash *tfm, const u8 *key, 819 unsigned int keylen) 820 { 821 struct aspeed_sham_ctx *tctx = crypto_ahash_ctx(tfm); 822 struct aspeed_hace_dev *hace_dev = tctx->hace_dev; 823 struct aspeed_sha_hmac_ctx *bctx = tctx->base; 824 int ds = crypto_shash_digestsize(bctx->shash); 825 int bs = crypto_shash_blocksize(bctx->shash); 826 int err = 0; 827 int i; 828 829 AHASH_DBG(hace_dev, "%s: keylen:%d\n", crypto_tfm_alg_name(&tfm->base), 830 keylen); 831 832 if (keylen > bs) { 833 err = aspeed_sham_shash_digest(bctx->shash, 834 crypto_shash_get_flags(bctx->shash), 835 key, keylen, bctx->ipad); 836 if (err) 837 return err; 838 keylen = ds; 839 840 } else { 841 memcpy(bctx->ipad, key, keylen); 842 } 843 844 memset(bctx->ipad + keylen, 0, bs - keylen); 845 memcpy(bctx->opad, bctx->ipad, bs); 846 847 for (i = 0; i < bs; i++) { 848 bctx->ipad[i] ^= HMAC_IPAD_VALUE; 849 bctx->opad[i] ^= HMAC_OPAD_VALUE; 850 } 851 852 return err; 853 } 854 855 static int aspeed_sham_cra_init(struct crypto_tfm *tfm) 856 { 857 struct ahash_alg *alg = __crypto_ahash_alg(tfm->__crt_alg); 858 struct aspeed_sham_ctx *tctx = crypto_tfm_ctx(tfm); 859 struct aspeed_hace_alg *ast_alg; 860 861 ast_alg = container_of(alg, struct aspeed_hace_alg, alg.ahash); 862 tctx->hace_dev = ast_alg->hace_dev; 863 tctx->flags = 0; 864 865 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), 866 sizeof(struct aspeed_sham_reqctx)); 867 868 if (ast_alg->alg_base) { 869 /* hmac related */ 870 struct aspeed_sha_hmac_ctx *bctx = tctx->base; 871 872 tctx->flags |= SHA_FLAGS_HMAC; 873 bctx->shash = crypto_alloc_shash(ast_alg->alg_base, 0, 874 CRYPTO_ALG_NEED_FALLBACK); 875 if (IS_ERR(bctx->shash)) { 876 dev_warn(ast_alg->hace_dev->dev, 877 "base driver '%s' could not be loaded.\n", 878 ast_alg->alg_base); 879 return PTR_ERR(bctx->shash); 880 } 881 } 882 883 tctx->enginectx.op.do_one_request = aspeed_ahash_do_one; 884 885 return 0; 886 } 887 888 static void aspeed_sham_cra_exit(struct crypto_tfm *tfm) 889 { 890 struct aspeed_sham_ctx *tctx = crypto_tfm_ctx(tfm); 891 struct aspeed_hace_dev *hace_dev = tctx->hace_dev; 892 893 AHASH_DBG(hace_dev, "%s\n", crypto_tfm_alg_name(tfm)); 894 895 if (tctx->flags & SHA_FLAGS_HMAC) { 896 struct aspeed_sha_hmac_ctx *bctx = tctx->base; 897 898 crypto_free_shash(bctx->shash); 899 } 900 } 901 902 static int aspeed_sham_export(struct ahash_request *req, void *out) 903 { 904 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 905 906 memcpy(out, rctx, sizeof(*rctx)); 907 908 return 0; 909 } 910 911 static int aspeed_sham_import(struct ahash_request *req, const void *in) 912 { 913 struct aspeed_sham_reqctx *rctx = ahash_request_ctx(req); 914 915 memcpy(rctx, in, sizeof(*rctx)); 916 917 return 0; 918 } 919 920 static struct aspeed_hace_alg aspeed_ahash_algs[] = { 921 { 922 .alg.ahash = { 923 .init = aspeed_sham_init, 924 .update = aspeed_sham_update, 925 .final = aspeed_sham_final, 926 .finup = aspeed_sham_finup, 927 .digest = aspeed_sham_digest, 928 .export = aspeed_sham_export, 929 .import = aspeed_sham_import, 930 .halg = { 931 .digestsize = SHA1_DIGEST_SIZE, 932 .statesize = sizeof(struct aspeed_sham_reqctx), 933 .base = { 934 .cra_name = "sha1", 935 .cra_driver_name = "aspeed-sha1", 936 .cra_priority = 300, 937 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 938 CRYPTO_ALG_ASYNC | 939 CRYPTO_ALG_KERN_DRIVER_ONLY, 940 .cra_blocksize = SHA1_BLOCK_SIZE, 941 .cra_ctxsize = sizeof(struct aspeed_sham_ctx), 942 .cra_alignmask = 0, 943 .cra_module = THIS_MODULE, 944 .cra_init = aspeed_sham_cra_init, 945 .cra_exit = aspeed_sham_cra_exit, 946 } 947 } 948 }, 949 }, 950 { 951 .alg.ahash = { 952 .init = aspeed_sham_init, 953 .update = aspeed_sham_update, 954 .final = aspeed_sham_final, 955 .finup = aspeed_sham_finup, 956 .digest = aspeed_sham_digest, 957 .export = aspeed_sham_export, 958 .import = aspeed_sham_import, 959 .halg = { 960 .digestsize = SHA256_DIGEST_SIZE, 961 .statesize = sizeof(struct aspeed_sham_reqctx), 962 .base = { 963 .cra_name = "sha256", 964 .cra_driver_name = "aspeed-sha256", 965 .cra_priority = 300, 966 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 967 CRYPTO_ALG_ASYNC | 968 CRYPTO_ALG_KERN_DRIVER_ONLY, 969 .cra_blocksize = SHA256_BLOCK_SIZE, 970 .cra_ctxsize = sizeof(struct aspeed_sham_ctx), 971 .cra_alignmask = 0, 972 .cra_module = THIS_MODULE, 973 .cra_init = aspeed_sham_cra_init, 974 .cra_exit = aspeed_sham_cra_exit, 975 } 976 } 977 }, 978 }, 979 { 980 .alg.ahash = { 981 .init = aspeed_sham_init, 982 .update = aspeed_sham_update, 983 .final = aspeed_sham_final, 984 .finup = aspeed_sham_finup, 985 .digest = aspeed_sham_digest, 986 .export = aspeed_sham_export, 987 .import = aspeed_sham_import, 988 .halg = { 989 .digestsize = SHA224_DIGEST_SIZE, 990 .statesize = sizeof(struct aspeed_sham_reqctx), 991 .base = { 992 .cra_name = "sha224", 993 .cra_driver_name = "aspeed-sha224", 994 .cra_priority = 300, 995 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 996 CRYPTO_ALG_ASYNC | 997 CRYPTO_ALG_KERN_DRIVER_ONLY, 998 .cra_blocksize = SHA224_BLOCK_SIZE, 999 .cra_ctxsize = sizeof(struct aspeed_sham_ctx), 1000 .cra_alignmask = 0, 1001 .cra_module = THIS_MODULE, 1002 .cra_init = aspeed_sham_cra_init, 1003 .cra_exit = aspeed_sham_cra_exit, 1004 } 1005 } 1006 }, 1007 }, 1008 { 1009 .alg_base = "sha1", 1010 .alg.ahash = { 1011 .init = aspeed_sham_init, 1012 .update = aspeed_sham_update, 1013 .final = aspeed_sham_final, 1014 .finup = aspeed_sham_finup, 1015 .digest = aspeed_sham_digest, 1016 .setkey = aspeed_sham_setkey, 1017 .export = aspeed_sham_export, 1018 .import = aspeed_sham_import, 1019 .halg = { 1020 .digestsize = SHA1_DIGEST_SIZE, 1021 .statesize = sizeof(struct aspeed_sham_reqctx), 1022 .base = { 1023 .cra_name = "hmac(sha1)", 1024 .cra_driver_name = "aspeed-hmac-sha1", 1025 .cra_priority = 300, 1026 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1027 CRYPTO_ALG_ASYNC | 1028 CRYPTO_ALG_KERN_DRIVER_ONLY, 1029 .cra_blocksize = SHA1_BLOCK_SIZE, 1030 .cra_ctxsize = sizeof(struct aspeed_sham_ctx) + 1031 sizeof(struct aspeed_sha_hmac_ctx), 1032 .cra_alignmask = 0, 1033 .cra_module = THIS_MODULE, 1034 .cra_init = aspeed_sham_cra_init, 1035 .cra_exit = aspeed_sham_cra_exit, 1036 } 1037 } 1038 }, 1039 }, 1040 { 1041 .alg_base = "sha224", 1042 .alg.ahash = { 1043 .init = aspeed_sham_init, 1044 .update = aspeed_sham_update, 1045 .final = aspeed_sham_final, 1046 .finup = aspeed_sham_finup, 1047 .digest = aspeed_sham_digest, 1048 .setkey = aspeed_sham_setkey, 1049 .export = aspeed_sham_export, 1050 .import = aspeed_sham_import, 1051 .halg = { 1052 .digestsize = SHA224_DIGEST_SIZE, 1053 .statesize = sizeof(struct aspeed_sham_reqctx), 1054 .base = { 1055 .cra_name = "hmac(sha224)", 1056 .cra_driver_name = "aspeed-hmac-sha224", 1057 .cra_priority = 300, 1058 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1059 CRYPTO_ALG_ASYNC | 1060 CRYPTO_ALG_KERN_DRIVER_ONLY, 1061 .cra_blocksize = SHA224_BLOCK_SIZE, 1062 .cra_ctxsize = sizeof(struct aspeed_sham_ctx) + 1063 sizeof(struct aspeed_sha_hmac_ctx), 1064 .cra_alignmask = 0, 1065 .cra_module = THIS_MODULE, 1066 .cra_init = aspeed_sham_cra_init, 1067 .cra_exit = aspeed_sham_cra_exit, 1068 } 1069 } 1070 }, 1071 }, 1072 { 1073 .alg_base = "sha256", 1074 .alg.ahash = { 1075 .init = aspeed_sham_init, 1076 .update = aspeed_sham_update, 1077 .final = aspeed_sham_final, 1078 .finup = aspeed_sham_finup, 1079 .digest = aspeed_sham_digest, 1080 .setkey = aspeed_sham_setkey, 1081 .export = aspeed_sham_export, 1082 .import = aspeed_sham_import, 1083 .halg = { 1084 .digestsize = SHA256_DIGEST_SIZE, 1085 .statesize = sizeof(struct aspeed_sham_reqctx), 1086 .base = { 1087 .cra_name = "hmac(sha256)", 1088 .cra_driver_name = "aspeed-hmac-sha256", 1089 .cra_priority = 300, 1090 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1091 CRYPTO_ALG_ASYNC | 1092 CRYPTO_ALG_KERN_DRIVER_ONLY, 1093 .cra_blocksize = SHA256_BLOCK_SIZE, 1094 .cra_ctxsize = sizeof(struct aspeed_sham_ctx) + 1095 sizeof(struct aspeed_sha_hmac_ctx), 1096 .cra_alignmask = 0, 1097 .cra_module = THIS_MODULE, 1098 .cra_init = aspeed_sham_cra_init, 1099 .cra_exit = aspeed_sham_cra_exit, 1100 } 1101 } 1102 }, 1103 }, 1104 }; 1105 1106 static struct aspeed_hace_alg aspeed_ahash_algs_g6[] = { 1107 { 1108 .alg.ahash = { 1109 .init = aspeed_sham_init, 1110 .update = aspeed_sham_update, 1111 .final = aspeed_sham_final, 1112 .finup = aspeed_sham_finup, 1113 .digest = aspeed_sham_digest, 1114 .export = aspeed_sham_export, 1115 .import = aspeed_sham_import, 1116 .halg = { 1117 .digestsize = SHA384_DIGEST_SIZE, 1118 .statesize = sizeof(struct aspeed_sham_reqctx), 1119 .base = { 1120 .cra_name = "sha384", 1121 .cra_driver_name = "aspeed-sha384", 1122 .cra_priority = 300, 1123 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1124 CRYPTO_ALG_ASYNC | 1125 CRYPTO_ALG_KERN_DRIVER_ONLY, 1126 .cra_blocksize = SHA384_BLOCK_SIZE, 1127 .cra_ctxsize = sizeof(struct aspeed_sham_ctx), 1128 .cra_alignmask = 0, 1129 .cra_module = THIS_MODULE, 1130 .cra_init = aspeed_sham_cra_init, 1131 .cra_exit = aspeed_sham_cra_exit, 1132 } 1133 } 1134 }, 1135 }, 1136 { 1137 .alg.ahash = { 1138 .init = aspeed_sham_init, 1139 .update = aspeed_sham_update, 1140 .final = aspeed_sham_final, 1141 .finup = aspeed_sham_finup, 1142 .digest = aspeed_sham_digest, 1143 .export = aspeed_sham_export, 1144 .import = aspeed_sham_import, 1145 .halg = { 1146 .digestsize = SHA512_DIGEST_SIZE, 1147 .statesize = sizeof(struct aspeed_sham_reqctx), 1148 .base = { 1149 .cra_name = "sha512", 1150 .cra_driver_name = "aspeed-sha512", 1151 .cra_priority = 300, 1152 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1153 CRYPTO_ALG_ASYNC | 1154 CRYPTO_ALG_KERN_DRIVER_ONLY, 1155 .cra_blocksize = SHA512_BLOCK_SIZE, 1156 .cra_ctxsize = sizeof(struct aspeed_sham_ctx), 1157 .cra_alignmask = 0, 1158 .cra_module = THIS_MODULE, 1159 .cra_init = aspeed_sham_cra_init, 1160 .cra_exit = aspeed_sham_cra_exit, 1161 } 1162 } 1163 }, 1164 }, 1165 { 1166 .alg.ahash = { 1167 .init = aspeed_sha512s_init, 1168 .update = aspeed_sham_update, 1169 .final = aspeed_sham_final, 1170 .finup = aspeed_sham_finup, 1171 .digest = aspeed_sham_digest, 1172 .export = aspeed_sham_export, 1173 .import = aspeed_sham_import, 1174 .halg = { 1175 .digestsize = SHA224_DIGEST_SIZE, 1176 .statesize = sizeof(struct aspeed_sham_reqctx), 1177 .base = { 1178 .cra_name = "sha512_224", 1179 .cra_driver_name = "aspeed-sha512_224", 1180 .cra_priority = 300, 1181 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1182 CRYPTO_ALG_ASYNC | 1183 CRYPTO_ALG_KERN_DRIVER_ONLY, 1184 .cra_blocksize = SHA512_BLOCK_SIZE, 1185 .cra_ctxsize = sizeof(struct aspeed_sham_ctx), 1186 .cra_alignmask = 0, 1187 .cra_module = THIS_MODULE, 1188 .cra_init = aspeed_sham_cra_init, 1189 .cra_exit = aspeed_sham_cra_exit, 1190 } 1191 } 1192 }, 1193 }, 1194 { 1195 .alg.ahash = { 1196 .init = aspeed_sha512s_init, 1197 .update = aspeed_sham_update, 1198 .final = aspeed_sham_final, 1199 .finup = aspeed_sham_finup, 1200 .digest = aspeed_sham_digest, 1201 .export = aspeed_sham_export, 1202 .import = aspeed_sham_import, 1203 .halg = { 1204 .digestsize = SHA256_DIGEST_SIZE, 1205 .statesize = sizeof(struct aspeed_sham_reqctx), 1206 .base = { 1207 .cra_name = "sha512_256", 1208 .cra_driver_name = "aspeed-sha512_256", 1209 .cra_priority = 300, 1210 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1211 CRYPTO_ALG_ASYNC | 1212 CRYPTO_ALG_KERN_DRIVER_ONLY, 1213 .cra_blocksize = SHA512_BLOCK_SIZE, 1214 .cra_ctxsize = sizeof(struct aspeed_sham_ctx), 1215 .cra_alignmask = 0, 1216 .cra_module = THIS_MODULE, 1217 .cra_init = aspeed_sham_cra_init, 1218 .cra_exit = aspeed_sham_cra_exit, 1219 } 1220 } 1221 }, 1222 }, 1223 { 1224 .alg_base = "sha384", 1225 .alg.ahash = { 1226 .init = aspeed_sham_init, 1227 .update = aspeed_sham_update, 1228 .final = aspeed_sham_final, 1229 .finup = aspeed_sham_finup, 1230 .digest = aspeed_sham_digest, 1231 .setkey = aspeed_sham_setkey, 1232 .export = aspeed_sham_export, 1233 .import = aspeed_sham_import, 1234 .halg = { 1235 .digestsize = SHA384_DIGEST_SIZE, 1236 .statesize = sizeof(struct aspeed_sham_reqctx), 1237 .base = { 1238 .cra_name = "hmac(sha384)", 1239 .cra_driver_name = "aspeed-hmac-sha384", 1240 .cra_priority = 300, 1241 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1242 CRYPTO_ALG_ASYNC | 1243 CRYPTO_ALG_KERN_DRIVER_ONLY, 1244 .cra_blocksize = SHA384_BLOCK_SIZE, 1245 .cra_ctxsize = sizeof(struct aspeed_sham_ctx) + 1246 sizeof(struct aspeed_sha_hmac_ctx), 1247 .cra_alignmask = 0, 1248 .cra_module = THIS_MODULE, 1249 .cra_init = aspeed_sham_cra_init, 1250 .cra_exit = aspeed_sham_cra_exit, 1251 } 1252 } 1253 }, 1254 }, 1255 { 1256 .alg_base = "sha512", 1257 .alg.ahash = { 1258 .init = aspeed_sham_init, 1259 .update = aspeed_sham_update, 1260 .final = aspeed_sham_final, 1261 .finup = aspeed_sham_finup, 1262 .digest = aspeed_sham_digest, 1263 .setkey = aspeed_sham_setkey, 1264 .export = aspeed_sham_export, 1265 .import = aspeed_sham_import, 1266 .halg = { 1267 .digestsize = SHA512_DIGEST_SIZE, 1268 .statesize = sizeof(struct aspeed_sham_reqctx), 1269 .base = { 1270 .cra_name = "hmac(sha512)", 1271 .cra_driver_name = "aspeed-hmac-sha512", 1272 .cra_priority = 300, 1273 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1274 CRYPTO_ALG_ASYNC | 1275 CRYPTO_ALG_KERN_DRIVER_ONLY, 1276 .cra_blocksize = SHA512_BLOCK_SIZE, 1277 .cra_ctxsize = sizeof(struct aspeed_sham_ctx) + 1278 sizeof(struct aspeed_sha_hmac_ctx), 1279 .cra_alignmask = 0, 1280 .cra_module = THIS_MODULE, 1281 .cra_init = aspeed_sham_cra_init, 1282 .cra_exit = aspeed_sham_cra_exit, 1283 } 1284 } 1285 }, 1286 }, 1287 { 1288 .alg_base = "sha512_224", 1289 .alg.ahash = { 1290 .init = aspeed_sha512s_init, 1291 .update = aspeed_sham_update, 1292 .final = aspeed_sham_final, 1293 .finup = aspeed_sham_finup, 1294 .digest = aspeed_sham_digest, 1295 .setkey = aspeed_sham_setkey, 1296 .export = aspeed_sham_export, 1297 .import = aspeed_sham_import, 1298 .halg = { 1299 .digestsize = SHA224_DIGEST_SIZE, 1300 .statesize = sizeof(struct aspeed_sham_reqctx), 1301 .base = { 1302 .cra_name = "hmac(sha512_224)", 1303 .cra_driver_name = "aspeed-hmac-sha512_224", 1304 .cra_priority = 300, 1305 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1306 CRYPTO_ALG_ASYNC | 1307 CRYPTO_ALG_KERN_DRIVER_ONLY, 1308 .cra_blocksize = SHA512_BLOCK_SIZE, 1309 .cra_ctxsize = sizeof(struct aspeed_sham_ctx) + 1310 sizeof(struct aspeed_sha_hmac_ctx), 1311 .cra_alignmask = 0, 1312 .cra_module = THIS_MODULE, 1313 .cra_init = aspeed_sham_cra_init, 1314 .cra_exit = aspeed_sham_cra_exit, 1315 } 1316 } 1317 }, 1318 }, 1319 { 1320 .alg_base = "sha512_256", 1321 .alg.ahash = { 1322 .init = aspeed_sha512s_init, 1323 .update = aspeed_sham_update, 1324 .final = aspeed_sham_final, 1325 .finup = aspeed_sham_finup, 1326 .digest = aspeed_sham_digest, 1327 .setkey = aspeed_sham_setkey, 1328 .export = aspeed_sham_export, 1329 .import = aspeed_sham_import, 1330 .halg = { 1331 .digestsize = SHA256_DIGEST_SIZE, 1332 .statesize = sizeof(struct aspeed_sham_reqctx), 1333 .base = { 1334 .cra_name = "hmac(sha512_256)", 1335 .cra_driver_name = "aspeed-hmac-sha512_256", 1336 .cra_priority = 300, 1337 .cra_flags = CRYPTO_ALG_TYPE_AHASH | 1338 CRYPTO_ALG_ASYNC | 1339 CRYPTO_ALG_KERN_DRIVER_ONLY, 1340 .cra_blocksize = SHA512_BLOCK_SIZE, 1341 .cra_ctxsize = sizeof(struct aspeed_sham_ctx) + 1342 sizeof(struct aspeed_sha_hmac_ctx), 1343 .cra_alignmask = 0, 1344 .cra_module = THIS_MODULE, 1345 .cra_init = aspeed_sham_cra_init, 1346 .cra_exit = aspeed_sham_cra_exit, 1347 } 1348 } 1349 }, 1350 }, 1351 }; 1352 1353 void aspeed_unregister_hace_hash_algs(struct aspeed_hace_dev *hace_dev) 1354 { 1355 int i; 1356 1357 for (i = 0; i < ARRAY_SIZE(aspeed_ahash_algs); i++) 1358 crypto_unregister_ahash(&aspeed_ahash_algs[i].alg.ahash); 1359 1360 if (hace_dev->version != AST2600_VERSION) 1361 return; 1362 1363 for (i = 0; i < ARRAY_SIZE(aspeed_ahash_algs_g6); i++) 1364 crypto_unregister_ahash(&aspeed_ahash_algs_g6[i].alg.ahash); 1365 } 1366 1367 void aspeed_register_hace_hash_algs(struct aspeed_hace_dev *hace_dev) 1368 { 1369 int rc, i; 1370 1371 AHASH_DBG(hace_dev, "\n"); 1372 1373 for (i = 0; i < ARRAY_SIZE(aspeed_ahash_algs); i++) { 1374 aspeed_ahash_algs[i].hace_dev = hace_dev; 1375 rc = crypto_register_ahash(&aspeed_ahash_algs[i].alg.ahash); 1376 if (rc) { 1377 AHASH_DBG(hace_dev, "Failed to register %s\n", 1378 aspeed_ahash_algs[i].alg.ahash.halg.base.cra_name); 1379 } 1380 } 1381 1382 if (hace_dev->version != AST2600_VERSION) 1383 return; 1384 1385 for (i = 0; i < ARRAY_SIZE(aspeed_ahash_algs_g6); i++) { 1386 aspeed_ahash_algs_g6[i].hace_dev = hace_dev; 1387 rc = crypto_register_ahash(&aspeed_ahash_algs_g6[i].alg.ahash); 1388 if (rc) { 1389 AHASH_DBG(hace_dev, "Failed to register %s\n", 1390 aspeed_ahash_algs_g6[i].alg.ahash.halg.base.cra_name); 1391 } 1392 } 1393 } 1394