1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * amlgoic-core.c - hardware cryptographic offloader for Amlogic GXL SoC 4 * 5 * Copyright (C) 2018-2019 Corentin Labbe <clabbe@baylibre.com> 6 * 7 * Core file which registers crypto algorithms supported by the hardware. 8 */ 9 10 #include <crypto/engine.h> 11 #include <crypto/internal/skcipher.h> 12 #include <linux/clk.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/err.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/irq.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/platform_device.h> 23 24 #include "amlogic-gxl.h" 25 26 static irqreturn_t meson_irq_handler(int irq, void *data) 27 { 28 struct meson_dev *mc = (struct meson_dev *)data; 29 int flow; 30 u32 p; 31 32 for (flow = 0; flow < MAXFLOW; flow++) { 33 if (mc->irqs[flow] == irq) { 34 p = readl(mc->base + ((0x04 + flow) << 2)); 35 if (p) { 36 writel_relaxed(0xF, mc->base + ((0x4 + flow) << 2)); 37 mc->chanlist[flow].status = 1; 38 complete(&mc->chanlist[flow].complete); 39 return IRQ_HANDLED; 40 } 41 dev_err(mc->dev, "%s %d Got irq for flow %d but ctrl is empty\n", __func__, irq, flow); 42 } 43 } 44 45 dev_err(mc->dev, "%s %d from unknown irq\n", __func__, irq); 46 return IRQ_HANDLED; 47 } 48 49 static struct meson_alg_template mc_algs[] = { 50 { 51 .type = CRYPTO_ALG_TYPE_SKCIPHER, 52 .blockmode = MESON_OPMODE_CBC, 53 .alg.skcipher.base = { 54 .base = { 55 .cra_name = "cbc(aes)", 56 .cra_driver_name = "cbc-aes-gxl", 57 .cra_priority = 400, 58 .cra_blocksize = AES_BLOCK_SIZE, 59 .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER | 60 CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY | 61 CRYPTO_ALG_NEED_FALLBACK, 62 .cra_ctxsize = sizeof(struct meson_cipher_tfm_ctx), 63 .cra_module = THIS_MODULE, 64 .cra_alignmask = 0xf, 65 .cra_init = meson_cipher_init, 66 .cra_exit = meson_cipher_exit, 67 }, 68 .min_keysize = AES_MIN_KEY_SIZE, 69 .max_keysize = AES_MAX_KEY_SIZE, 70 .ivsize = AES_BLOCK_SIZE, 71 .setkey = meson_aes_setkey, 72 .encrypt = meson_skencrypt, 73 .decrypt = meson_skdecrypt, 74 }, 75 .alg.skcipher.op = { 76 .do_one_request = meson_handle_cipher_request, 77 }, 78 }, 79 { 80 .type = CRYPTO_ALG_TYPE_SKCIPHER, 81 .blockmode = MESON_OPMODE_ECB, 82 .alg.skcipher.base = { 83 .base = { 84 .cra_name = "ecb(aes)", 85 .cra_driver_name = "ecb-aes-gxl", 86 .cra_priority = 400, 87 .cra_blocksize = AES_BLOCK_SIZE, 88 .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER | 89 CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY | 90 CRYPTO_ALG_NEED_FALLBACK, 91 .cra_ctxsize = sizeof(struct meson_cipher_tfm_ctx), 92 .cra_module = THIS_MODULE, 93 .cra_alignmask = 0xf, 94 .cra_init = meson_cipher_init, 95 .cra_exit = meson_cipher_exit, 96 }, 97 .min_keysize = AES_MIN_KEY_SIZE, 98 .max_keysize = AES_MAX_KEY_SIZE, 99 .setkey = meson_aes_setkey, 100 .encrypt = meson_skencrypt, 101 .decrypt = meson_skdecrypt, 102 }, 103 .alg.skcipher.op = { 104 .do_one_request = meson_handle_cipher_request, 105 }, 106 }, 107 }; 108 109 static int meson_debugfs_show(struct seq_file *seq, void *v) 110 { 111 struct meson_dev *mc __maybe_unused = seq->private; 112 int i; 113 114 for (i = 0; i < MAXFLOW; i++) 115 seq_printf(seq, "Channel %d: nreq %lu\n", i, 116 #ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG 117 mc->chanlist[i].stat_req); 118 #else 119 0ul); 120 #endif 121 122 for (i = 0; i < ARRAY_SIZE(mc_algs); i++) { 123 switch (mc_algs[i].type) { 124 case CRYPTO_ALG_TYPE_SKCIPHER: 125 seq_printf(seq, "%s %s %lu %lu\n", 126 mc_algs[i].alg.skcipher.base.base.cra_driver_name, 127 mc_algs[i].alg.skcipher.base.base.cra_name, 128 #ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG 129 mc_algs[i].stat_req, mc_algs[i].stat_fb); 130 #else 131 0ul, 0ul); 132 #endif 133 break; 134 } 135 } 136 return 0; 137 } 138 DEFINE_SHOW_ATTRIBUTE(meson_debugfs); 139 140 static void meson_free_chanlist(struct meson_dev *mc, int i) 141 { 142 while (i >= 0) { 143 crypto_engine_exit(mc->chanlist[i].engine); 144 if (mc->chanlist[i].tl) 145 dma_free_coherent(mc->dev, sizeof(struct meson_desc) * MAXDESC, 146 mc->chanlist[i].tl, 147 mc->chanlist[i].t_phy); 148 i--; 149 } 150 } 151 152 /* 153 * Allocate the channel list structure 154 */ 155 static int meson_allocate_chanlist(struct meson_dev *mc) 156 { 157 int i, err; 158 159 mc->chanlist = devm_kcalloc(mc->dev, MAXFLOW, 160 sizeof(struct meson_flow), GFP_KERNEL); 161 if (!mc->chanlist) 162 return -ENOMEM; 163 164 for (i = 0; i < MAXFLOW; i++) { 165 init_completion(&mc->chanlist[i].complete); 166 167 mc->chanlist[i].engine = crypto_engine_alloc_init(mc->dev, true); 168 if (!mc->chanlist[i].engine) { 169 dev_err(mc->dev, "Cannot allocate engine\n"); 170 i--; 171 err = -ENOMEM; 172 goto error_engine; 173 } 174 err = crypto_engine_start(mc->chanlist[i].engine); 175 if (err) { 176 dev_err(mc->dev, "Cannot start engine\n"); 177 goto error_engine; 178 } 179 mc->chanlist[i].tl = dma_alloc_coherent(mc->dev, 180 sizeof(struct meson_desc) * MAXDESC, 181 &mc->chanlist[i].t_phy, 182 GFP_KERNEL); 183 if (!mc->chanlist[i].tl) { 184 err = -ENOMEM; 185 goto error_engine; 186 } 187 } 188 return 0; 189 error_engine: 190 meson_free_chanlist(mc, i); 191 return err; 192 } 193 194 static int meson_register_algs(struct meson_dev *mc) 195 { 196 int err, i; 197 198 for (i = 0; i < ARRAY_SIZE(mc_algs); i++) { 199 mc_algs[i].mc = mc; 200 switch (mc_algs[i].type) { 201 case CRYPTO_ALG_TYPE_SKCIPHER: 202 err = crypto_engine_register_skcipher(&mc_algs[i].alg.skcipher); 203 if (err) { 204 dev_err(mc->dev, "Fail to register %s\n", 205 mc_algs[i].alg.skcipher.base.base.cra_name); 206 mc_algs[i].mc = NULL; 207 return err; 208 } 209 break; 210 } 211 } 212 213 return 0; 214 } 215 216 static void meson_unregister_algs(struct meson_dev *mc) 217 { 218 int i; 219 220 for (i = 0; i < ARRAY_SIZE(mc_algs); i++) { 221 if (!mc_algs[i].mc) 222 continue; 223 switch (mc_algs[i].type) { 224 case CRYPTO_ALG_TYPE_SKCIPHER: 225 crypto_engine_unregister_skcipher(&mc_algs[i].alg.skcipher); 226 break; 227 } 228 } 229 } 230 231 static int meson_crypto_probe(struct platform_device *pdev) 232 { 233 struct meson_dev *mc; 234 int err, i; 235 236 mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); 237 if (!mc) 238 return -ENOMEM; 239 240 mc->dev = &pdev->dev; 241 platform_set_drvdata(pdev, mc); 242 243 mc->base = devm_platform_ioremap_resource(pdev, 0); 244 if (IS_ERR(mc->base)) { 245 err = PTR_ERR(mc->base); 246 dev_err(&pdev->dev, "Cannot request MMIO err=%d\n", err); 247 return err; 248 } 249 mc->busclk = devm_clk_get(&pdev->dev, "blkmv"); 250 if (IS_ERR(mc->busclk)) { 251 err = PTR_ERR(mc->busclk); 252 dev_err(&pdev->dev, "Cannot get core clock err=%d\n", err); 253 return err; 254 } 255 256 for (i = 0; i < MAXFLOW; i++) { 257 mc->irqs[i] = platform_get_irq(pdev, i); 258 if (mc->irqs[i] < 0) 259 return mc->irqs[i]; 260 261 err = devm_request_irq(&pdev->dev, mc->irqs[i], meson_irq_handler, 0, 262 "gxl-crypto", mc); 263 if (err < 0) { 264 dev_err(mc->dev, "Cannot request IRQ for flow %d\n", i); 265 return err; 266 } 267 } 268 269 err = clk_prepare_enable(mc->busclk); 270 if (err != 0) { 271 dev_err(&pdev->dev, "Cannot prepare_enable busclk\n"); 272 return err; 273 } 274 275 err = meson_allocate_chanlist(mc); 276 if (err) 277 goto error_flow; 278 279 err = meson_register_algs(mc); 280 if (err) 281 goto error_alg; 282 283 if (IS_ENABLED(CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG)) { 284 struct dentry *dbgfs_dir; 285 286 dbgfs_dir = debugfs_create_dir("gxl-crypto", NULL); 287 debugfs_create_file("stats", 0444, dbgfs_dir, mc, &meson_debugfs_fops); 288 289 #ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG 290 mc->dbgfs_dir = dbgfs_dir; 291 #endif 292 } 293 294 return 0; 295 error_alg: 296 meson_unregister_algs(mc); 297 error_flow: 298 meson_free_chanlist(mc, MAXFLOW - 1); 299 clk_disable_unprepare(mc->busclk); 300 return err; 301 } 302 303 static int meson_crypto_remove(struct platform_device *pdev) 304 { 305 struct meson_dev *mc = platform_get_drvdata(pdev); 306 307 #ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG 308 debugfs_remove_recursive(mc->dbgfs_dir); 309 #endif 310 311 meson_unregister_algs(mc); 312 313 meson_free_chanlist(mc, MAXFLOW - 1); 314 315 clk_disable_unprepare(mc->busclk); 316 return 0; 317 } 318 319 static const struct of_device_id meson_crypto_of_match_table[] = { 320 { .compatible = "amlogic,gxl-crypto", }, 321 {} 322 }; 323 MODULE_DEVICE_TABLE(of, meson_crypto_of_match_table); 324 325 static struct platform_driver meson_crypto_driver = { 326 .probe = meson_crypto_probe, 327 .remove = meson_crypto_remove, 328 .driver = { 329 .name = "gxl-crypto", 330 .of_match_table = meson_crypto_of_match_table, 331 }, 332 }; 333 334 module_platform_driver(meson_crypto_driver); 335 336 MODULE_DESCRIPTION("Amlogic GXL cryptographic offloader"); 337 MODULE_LICENSE("GPL"); 338 MODULE_AUTHOR("Corentin Labbe <clabbe@baylibre.com>"); 339