xref: /openbmc/linux/drivers/clocksource/timer-milbeaut.c (revision 95d5dc712634901e6707d3178e6170aa6e0a43ce)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2018 Socionext Inc.
4  */
5 
6 #include <linux/clk.h>
7 #include <linux/interrupt.h>
8 #include <linux/irq.h>
9 #include <linux/irqreturn.h>
10 #include <linux/sched_clock.h>
11 #include "timer-of.h"
12 
13 #define MLB_TMR_TMCSR_OFS	0x0
14 #define MLB_TMR_TMR_OFS		0x4
15 #define MLB_TMR_TMRLR1_OFS	0x8
16 #define MLB_TMR_TMRLR2_OFS	0xc
17 #define MLB_TMR_REGSZPCH	0x10
18 
19 #define MLB_TMR_TMCSR_OUTL	BIT(5)
20 #define MLB_TMR_TMCSR_RELD	BIT(4)
21 #define MLB_TMR_TMCSR_INTE	BIT(3)
22 #define MLB_TMR_TMCSR_UF	BIT(2)
23 #define MLB_TMR_TMCSR_CNTE	BIT(1)
24 #define MLB_TMR_TMCSR_TRG	BIT(0)
25 
26 #define MLB_TMR_TMCSR_CSL_DIV2	0
27 #define MLB_TMR_DIV_CNT		2
28 
29 #define MLB_TMR_SRC_CH  (1)
30 #define MLB_TMR_EVT_CH  (0)
31 
32 #define MLB_TMR_SRC_CH_OFS	(MLB_TMR_REGSZPCH * MLB_TMR_SRC_CH)
33 #define MLB_TMR_EVT_CH_OFS	(MLB_TMR_REGSZPCH * MLB_TMR_EVT_CH)
34 
35 #define MLB_TMR_SRC_TMCSR_OFS	(MLB_TMR_SRC_CH_OFS + MLB_TMR_TMCSR_OFS)
36 #define MLB_TMR_SRC_TMR_OFS	(MLB_TMR_SRC_CH_OFS + MLB_TMR_TMR_OFS)
37 #define MLB_TMR_SRC_TMRLR1_OFS	(MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR1_OFS)
38 #define MLB_TMR_SRC_TMRLR2_OFS	(MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR2_OFS)
39 
40 #define MLB_TMR_EVT_TMCSR_OFS	(MLB_TMR_EVT_CH_OFS + MLB_TMR_TMCSR_OFS)
41 #define MLB_TMR_EVT_TMR_OFS	(MLB_TMR_EVT_CH_OFS + MLB_TMR_TMR_OFS)
42 #define MLB_TMR_EVT_TMRLR1_OFS	(MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR1_OFS)
43 #define MLB_TMR_EVT_TMRLR2_OFS	(MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR2_OFS)
44 
45 #define MLB_TIMER_RATING	500
46 
47 static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id)
48 {
49 	struct clock_event_device *clk = dev_id;
50 	struct timer_of *to = to_timer_of(clk);
51 	u32 val;
52 
53 	val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
54 	val &= ~MLB_TMR_TMCSR_UF;
55 	writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
56 
57 	clk->event_handler(clk);
58 
59 	return IRQ_HANDLED;
60 }
61 
62 static int mlb_set_state_periodic(struct clock_event_device *clk)
63 {
64 	struct timer_of *to = to_timer_of(clk);
65 	u32 val = MLB_TMR_TMCSR_CSL_DIV2;
66 
67 	writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
68 
69 	writel_relaxed(to->of_clk.period, timer_of_base(to) +
70 				MLB_TMR_EVT_TMRLR1_OFS);
71 	val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE |
72 		MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
73 	writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
74 	return 0;
75 }
76 
77 static int mlb_set_state_oneshot(struct clock_event_device *clk)
78 {
79 	struct timer_of *to = to_timer_of(clk);
80 	u32 val = MLB_TMR_TMCSR_CSL_DIV2;
81 
82 	writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
83 	val |= MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
84 	writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
85 	return 0;
86 }
87 
88 static int mlb_set_state_shutdown(struct clock_event_device *clk)
89 {
90 	struct timer_of *to = to_timer_of(clk);
91 	u32 val = MLB_TMR_TMCSR_CSL_DIV2;
92 
93 	writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
94 	return 0;
95 }
96 
97 static int mlb_clkevt_next_event(unsigned long event,
98 				   struct clock_event_device *clk)
99 {
100 	struct timer_of *to = to_timer_of(clk);
101 
102 	writel_relaxed(event, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
103 	writel_relaxed(MLB_TMR_TMCSR_CSL_DIV2 |
104 			MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_INTE |
105 			MLB_TMR_TMCSR_TRG, timer_of_base(to) +
106 			MLB_TMR_EVT_TMCSR_OFS);
107 	return 0;
108 }
109 
110 static int mlb_config_clock_source(struct timer_of *to)
111 {
112 	writel_relaxed(0, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
113 	writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMR_OFS);
114 	writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS);
115 	writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS);
116 	writel_relaxed(BIT(4) | BIT(1) | BIT(0), timer_of_base(to) +
117 		MLB_TMR_SRC_TMCSR_OFS);
118 	return 0;
119 }
120 
121 static int mlb_config_clock_event(struct timer_of *to)
122 {
123 	writel_relaxed(0, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
124 	return 0;
125 }
126 
127 static struct timer_of to = {
128 	.flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
129 
130 	.clkevt = {
131 		.name = "mlb-clkevt",
132 		.rating = MLB_TIMER_RATING,
133 		.cpumask = cpu_possible_mask,
134 		.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT,
135 		.set_state_oneshot = mlb_set_state_oneshot,
136 		.set_state_periodic = mlb_set_state_periodic,
137 		.set_state_shutdown = mlb_set_state_shutdown,
138 		.set_next_event = mlb_clkevt_next_event,
139 	},
140 
141 	.of_irq = {
142 		.flags = IRQF_TIMER | IRQF_IRQPOLL,
143 		.handler = mlb_timer_interrupt,
144 	},
145 };
146 
147 static u64 notrace mlb_timer_sched_read(void)
148 {
149 	return ~readl_relaxed(timer_of_base(&to) + MLB_TMR_SRC_TMR_OFS);
150 }
151 
152 static int __init mlb_timer_init(struct device_node *node)
153 {
154 	int ret;
155 	unsigned long rate;
156 
157 	ret = timer_of_init(node, &to);
158 	if (ret)
159 		return ret;
160 
161 	rate = timer_of_rate(&to) / MLB_TMR_DIV_CNT;
162 	mlb_config_clock_source(&to);
163 	clocksource_mmio_init(timer_of_base(&to) + MLB_TMR_SRC_TMR_OFS,
164 		node->name, rate, MLB_TIMER_RATING, 32,
165 		clocksource_mmio_readl_down);
166 	sched_clock_register(mlb_timer_sched_read, 32, rate);
167 	mlb_config_clock_event(&to);
168 	clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), 15,
169 		0xffffffff);
170 	return 0;
171 }
172 TIMER_OF_DECLARE(mlb_peritimer, "socionext,milbeaut-timer",
173 		mlb_timer_init);
174