1 2874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2 8d8bd7beSOleksij Rempel /*
3 8d8bd7beSOleksij Rempel * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
4 8d8bd7beSOleksij Rempel */
5 8d8bd7beSOleksij Rempel
6 8d8bd7beSOleksij Rempel #include <linux/kernel.h>
7 8d8bd7beSOleksij Rempel #include <linux/init.h>
8 8d8bd7beSOleksij Rempel #include <linux/interrupt.h>
9 8d8bd7beSOleksij Rempel #include <linux/sched.h>
10 8d8bd7beSOleksij Rempel #include <linux/clk.h>
11 8d8bd7beSOleksij Rempel #include <linux/clocksource.h>
12 8d8bd7beSOleksij Rempel #include <linux/clockchips.h>
13 8d8bd7beSOleksij Rempel #include <linux/io.h>
14 8d8bd7beSOleksij Rempel #include <linux/of.h>
15 8d8bd7beSOleksij Rempel #include <linux/of_address.h>
16 8d8bd7beSOleksij Rempel #include <linux/of_irq.h>
17 8d8bd7beSOleksij Rempel #include <linux/bitops.h>
18 8d8bd7beSOleksij Rempel
19 8d8bd7beSOleksij Rempel #define DRIVER_NAME "asm9260-timer"
20 8d8bd7beSOleksij Rempel
21 8d8bd7beSOleksij Rempel /*
22 8d8bd7beSOleksij Rempel * this device provide 4 offsets for each register:
23 8d8bd7beSOleksij Rempel * 0x0 - plain read write mode
24 8d8bd7beSOleksij Rempel * 0x4 - set mode, OR logic.
25 8d8bd7beSOleksij Rempel * 0x8 - clr mode, XOR logic.
26 8d8bd7beSOleksij Rempel * 0xc - togle mode.
27 8d8bd7beSOleksij Rempel */
28 8d8bd7beSOleksij Rempel #define SET_REG 4
29 8d8bd7beSOleksij Rempel #define CLR_REG 8
30 8d8bd7beSOleksij Rempel
31 8d8bd7beSOleksij Rempel #define HW_IR 0x0000 /* RW. Interrupt */
32 8d8bd7beSOleksij Rempel #define BM_IR_CR0 BIT(4)
33 8d8bd7beSOleksij Rempel #define BM_IR_MR3 BIT(3)
34 8d8bd7beSOleksij Rempel #define BM_IR_MR2 BIT(2)
35 8d8bd7beSOleksij Rempel #define BM_IR_MR1 BIT(1)
36 8d8bd7beSOleksij Rempel #define BM_IR_MR0 BIT(0)
37 8d8bd7beSOleksij Rempel
38 8d8bd7beSOleksij Rempel #define HW_TCR 0x0010 /* RW. Timer controller */
39 8d8bd7beSOleksij Rempel /* BM_C*_RST
40 8d8bd7beSOleksij Rempel * Timer Counter and the Prescale Counter are synchronously reset on the
41 8d8bd7beSOleksij Rempel * next positive edge of PCLK. The counters remain reset until TCR[1] is
42 8d8bd7beSOleksij Rempel * returned to zero. */
43 8d8bd7beSOleksij Rempel #define BM_C3_RST BIT(7)
44 8d8bd7beSOleksij Rempel #define BM_C2_RST BIT(6)
45 8d8bd7beSOleksij Rempel #define BM_C1_RST BIT(5)
46 8d8bd7beSOleksij Rempel #define BM_C0_RST BIT(4)
47 8d8bd7beSOleksij Rempel /* BM_C*_EN
48 8d8bd7beSOleksij Rempel * 1 - Timer Counter and Prescale Counter are enabled for counting
49 8d8bd7beSOleksij Rempel * 0 - counters are disabled */
50 8d8bd7beSOleksij Rempel #define BM_C3_EN BIT(3)
51 8d8bd7beSOleksij Rempel #define BM_C2_EN BIT(2)
52 8d8bd7beSOleksij Rempel #define BM_C1_EN BIT(1)
53 8d8bd7beSOleksij Rempel #define BM_C0_EN BIT(0)
54 8d8bd7beSOleksij Rempel
55 8d8bd7beSOleksij Rempel #define HW_DIR 0x0020 /* RW. Direction? */
56 8d8bd7beSOleksij Rempel /* 00 - count up
57 8d8bd7beSOleksij Rempel * 01 - count down
58 8d8bd7beSOleksij Rempel * 10 - ?? 2^n/2 */
59 8d8bd7beSOleksij Rempel #define BM_DIR_COUNT_UP 0
60 8d8bd7beSOleksij Rempel #define BM_DIR_COUNT_DOWN 1
61 8d8bd7beSOleksij Rempel #define BM_DIR0_SHIFT 0
62 8d8bd7beSOleksij Rempel #define BM_DIR1_SHIFT 4
63 8d8bd7beSOleksij Rempel #define BM_DIR2_SHIFT 8
64 8d8bd7beSOleksij Rempel #define BM_DIR3_SHIFT 12
65 8d8bd7beSOleksij Rempel #define BM_DIR_DEFAULT (BM_DIR_COUNT_UP << BM_DIR0_SHIFT | \
66 8d8bd7beSOleksij Rempel BM_DIR_COUNT_UP << BM_DIR1_SHIFT | \
67 8d8bd7beSOleksij Rempel BM_DIR_COUNT_UP << BM_DIR2_SHIFT | \
68 8d8bd7beSOleksij Rempel BM_DIR_COUNT_UP << BM_DIR3_SHIFT)
69 8d8bd7beSOleksij Rempel
70 8d8bd7beSOleksij Rempel #define HW_TC0 0x0030 /* RO. Timer counter 0 */
71 8d8bd7beSOleksij Rempel /* HW_TC*. Timer counter owerflow (0xffff.ffff to 0x0000.0000) do not generate
72 8d8bd7beSOleksij Rempel * interrupt. This registers can be used to detect overflow */
73 8d8bd7beSOleksij Rempel #define HW_TC1 0x0040
74 8d8bd7beSOleksij Rempel #define HW_TC2 0x0050
75 8d8bd7beSOleksij Rempel #define HW_TC3 0x0060
76 8d8bd7beSOleksij Rempel
77 8d8bd7beSOleksij Rempel #define HW_PR 0x0070 /* RW. prescaler */
78 8d8bd7beSOleksij Rempel #define BM_PR_DISABLE 0
79 8d8bd7beSOleksij Rempel #define HW_PC 0x0080 /* RO. Prescaler counter */
80 8d8bd7beSOleksij Rempel #define HW_MCR 0x0090 /* RW. Match control */
81 8d8bd7beSOleksij Rempel /* enable interrupt on match */
82 8d8bd7beSOleksij Rempel #define BM_MCR_INT_EN(n) (1 << (n * 3 + 0))
83 8d8bd7beSOleksij Rempel /* enable TC reset on match */
84 8d8bd7beSOleksij Rempel #define BM_MCR_RES_EN(n) (1 << (n * 3 + 1))
85 8d8bd7beSOleksij Rempel /* enable stop TC on match */
86 8d8bd7beSOleksij Rempel #define BM_MCR_STOP_EN(n) (1 << (n * 3 + 2))
87 8d8bd7beSOleksij Rempel
88 8d8bd7beSOleksij Rempel #define HW_MR0 0x00a0 /* RW. Match reg */
89 8d8bd7beSOleksij Rempel #define HW_MR1 0x00b0
90 8d8bd7beSOleksij Rempel #define HW_MR2 0x00C0
91 8d8bd7beSOleksij Rempel #define HW_MR3 0x00D0
92 8d8bd7beSOleksij Rempel
93 8d8bd7beSOleksij Rempel #define HW_CTCR 0x0180 /* Counter control */
94 8d8bd7beSOleksij Rempel #define BM_CTCR0_SHIFT 0
95 8d8bd7beSOleksij Rempel #define BM_CTCR1_SHIFT 2
96 8d8bd7beSOleksij Rempel #define BM_CTCR2_SHIFT 4
97 8d8bd7beSOleksij Rempel #define BM_CTCR3_SHIFT 6
98 8d8bd7beSOleksij Rempel #define BM_CTCR_TM 0 /* Timer mode. Every rising PCLK edge. */
99 8d8bd7beSOleksij Rempel #define BM_CTCR_DEFAULT (BM_CTCR_TM << BM_CTCR0_SHIFT | \
100 8d8bd7beSOleksij Rempel BM_CTCR_TM << BM_CTCR1_SHIFT | \
101 8d8bd7beSOleksij Rempel BM_CTCR_TM << BM_CTCR2_SHIFT | \
102 8d8bd7beSOleksij Rempel BM_CTCR_TM << BM_CTCR3_SHIFT)
103 8d8bd7beSOleksij Rempel
104 8d8bd7beSOleksij Rempel static struct asm9260_timer_priv {
105 8d8bd7beSOleksij Rempel void __iomem *base;
106 8d8bd7beSOleksij Rempel unsigned long ticks_per_jiffy;
107 8d8bd7beSOleksij Rempel } priv;
108 8d8bd7beSOleksij Rempel
asm9260_timer_set_next_event(unsigned long delta,struct clock_event_device * evt)109 8d8bd7beSOleksij Rempel static int asm9260_timer_set_next_event(unsigned long delta,
110 8d8bd7beSOleksij Rempel struct clock_event_device *evt)
111 8d8bd7beSOleksij Rempel {
112 8d8bd7beSOleksij Rempel /* configure match count for TC0 */
113 8d8bd7beSOleksij Rempel writel_relaxed(delta, priv.base + HW_MR0);
114 8d8bd7beSOleksij Rempel /* enable TC0 */
115 8d8bd7beSOleksij Rempel writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG);
116 8d8bd7beSOleksij Rempel return 0;
117 8d8bd7beSOleksij Rempel }
118 8d8bd7beSOleksij Rempel
__asm9260_timer_shutdown(struct clock_event_device * evt)119 3465f609SViresh Kumar static inline void __asm9260_timer_shutdown(struct clock_event_device *evt)
120 8d8bd7beSOleksij Rempel {
121 8d8bd7beSOleksij Rempel /* stop timer0 */
122 8d8bd7beSOleksij Rempel writel_relaxed(BM_C0_EN, priv.base + HW_TCR + CLR_REG);
123 3465f609SViresh Kumar }
124 8d8bd7beSOleksij Rempel
asm9260_timer_shutdown(struct clock_event_device * evt)125 3465f609SViresh Kumar static int asm9260_timer_shutdown(struct clock_event_device *evt)
126 3465f609SViresh Kumar {
127 3465f609SViresh Kumar __asm9260_timer_shutdown(evt);
128 3465f609SViresh Kumar return 0;
129 3465f609SViresh Kumar }
130 3465f609SViresh Kumar
asm9260_timer_set_oneshot(struct clock_event_device * evt)131 3465f609SViresh Kumar static int asm9260_timer_set_oneshot(struct clock_event_device *evt)
132 3465f609SViresh Kumar {
133 3465f609SViresh Kumar __asm9260_timer_shutdown(evt);
134 3465f609SViresh Kumar
135 3465f609SViresh Kumar /* enable reset and stop on match */
136 3465f609SViresh Kumar writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0),
137 3465f609SViresh Kumar priv.base + HW_MCR + SET_REG);
138 3465f609SViresh Kumar return 0;
139 3465f609SViresh Kumar }
140 3465f609SViresh Kumar
asm9260_timer_set_periodic(struct clock_event_device * evt)141 3465f609SViresh Kumar static int asm9260_timer_set_periodic(struct clock_event_device *evt)
142 3465f609SViresh Kumar {
143 3465f609SViresh Kumar __asm9260_timer_shutdown(evt);
144 3465f609SViresh Kumar
145 8d8bd7beSOleksij Rempel /* disable reset and stop on match */
146 8d8bd7beSOleksij Rempel writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0),
147 8d8bd7beSOleksij Rempel priv.base + HW_MCR + CLR_REG);
148 8d8bd7beSOleksij Rempel /* configure match count for TC0 */
149 8d8bd7beSOleksij Rempel writel_relaxed(priv.ticks_per_jiffy, priv.base + HW_MR0);
150 8d8bd7beSOleksij Rempel /* enable TC0 */
151 8d8bd7beSOleksij Rempel writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG);
152 3465f609SViresh Kumar return 0;
153 8d8bd7beSOleksij Rempel }
154 8d8bd7beSOleksij Rempel
155 8d8bd7beSOleksij Rempel static struct clock_event_device event_dev = {
156 8d8bd7beSOleksij Rempel .name = DRIVER_NAME,
157 8d8bd7beSOleksij Rempel .rating = 200,
158 3465f609SViresh Kumar .features = CLOCK_EVT_FEAT_PERIODIC |
159 3465f609SViresh Kumar CLOCK_EVT_FEAT_ONESHOT,
160 8d8bd7beSOleksij Rempel .set_next_event = asm9260_timer_set_next_event,
161 3465f609SViresh Kumar .set_state_shutdown = asm9260_timer_shutdown,
162 3465f609SViresh Kumar .set_state_periodic = asm9260_timer_set_periodic,
163 3465f609SViresh Kumar .set_state_oneshot = asm9260_timer_set_oneshot,
164 3465f609SViresh Kumar .tick_resume = asm9260_timer_shutdown,
165 8d8bd7beSOleksij Rempel };
166 8d8bd7beSOleksij Rempel
asm9260_timer_interrupt(int irq,void * dev_id)167 8d8bd7beSOleksij Rempel static irqreturn_t asm9260_timer_interrupt(int irq, void *dev_id)
168 8d8bd7beSOleksij Rempel {
169 8d8bd7beSOleksij Rempel struct clock_event_device *evt = dev_id;
170 8d8bd7beSOleksij Rempel
171 8d8bd7beSOleksij Rempel evt->event_handler(evt);
172 8d8bd7beSOleksij Rempel
173 8d8bd7beSOleksij Rempel writel_relaxed(BM_IR_MR0, priv.base + HW_IR);
174 8d8bd7beSOleksij Rempel
175 8d8bd7beSOleksij Rempel return IRQ_HANDLED;
176 8d8bd7beSOleksij Rempel }
177 8d8bd7beSOleksij Rempel
178 8d8bd7beSOleksij Rempel /*
179 8d8bd7beSOleksij Rempel * ---------------------------------------------------------------------------
180 8d8bd7beSOleksij Rempel * Timer initialization
181 8d8bd7beSOleksij Rempel * ---------------------------------------------------------------------------
182 8d8bd7beSOleksij Rempel */
asm9260_timer_init(struct device_node * np)183 be5eb33dSDaniel Lezcano static int __init asm9260_timer_init(struct device_node *np)
184 8d8bd7beSOleksij Rempel {
185 8d8bd7beSOleksij Rempel int irq;
186 8d8bd7beSOleksij Rempel struct clk *clk;
187 8d8bd7beSOleksij Rempel int ret;
188 8d8bd7beSOleksij Rempel unsigned long rate;
189 8d8bd7beSOleksij Rempel
190 8d8bd7beSOleksij Rempel priv.base = of_io_request_and_map(np, 0, np->name);
191 be5eb33dSDaniel Lezcano if (IS_ERR(priv.base)) {
192 2a4849d2SRob Herring pr_err("%pOFn: unable to map resource\n", np);
193 be5eb33dSDaniel Lezcano return PTR_ERR(priv.base);
194 be5eb33dSDaniel Lezcano }
195 8d8bd7beSOleksij Rempel
196 8d8bd7beSOleksij Rempel clk = of_clk_get(np, 0);
197 *6e001f6aSChuhong Yuan if (IS_ERR(clk)) {
198 *6e001f6aSChuhong Yuan pr_err("Failed to get clk!\n");
199 *6e001f6aSChuhong Yuan return PTR_ERR(clk);
200 *6e001f6aSChuhong Yuan }
201 8d8bd7beSOleksij Rempel
202 8d8bd7beSOleksij Rempel ret = clk_prepare_enable(clk);
203 be5eb33dSDaniel Lezcano if (ret) {
204 be5eb33dSDaniel Lezcano pr_err("Failed to enable clk!\n");
205 be5eb33dSDaniel Lezcano return ret;
206 be5eb33dSDaniel Lezcano }
207 8d8bd7beSOleksij Rempel
208 8d8bd7beSOleksij Rempel irq = irq_of_parse_and_map(np, 0);
209 8d8bd7beSOleksij Rempel ret = request_irq(irq, asm9260_timer_interrupt, IRQF_TIMER,
210 8d8bd7beSOleksij Rempel DRIVER_NAME, &event_dev);
211 be5eb33dSDaniel Lezcano if (ret) {
212 be5eb33dSDaniel Lezcano pr_err("Failed to setup irq!\n");
213 be5eb33dSDaniel Lezcano return ret;
214 be5eb33dSDaniel Lezcano }
215 8d8bd7beSOleksij Rempel
216 8d8bd7beSOleksij Rempel /* set all timers for count-up */
217 8d8bd7beSOleksij Rempel writel_relaxed(BM_DIR_DEFAULT, priv.base + HW_DIR);
218 8d8bd7beSOleksij Rempel /* disable divider */
219 8d8bd7beSOleksij Rempel writel_relaxed(BM_PR_DISABLE, priv.base + HW_PR);
220 8d8bd7beSOleksij Rempel /* make sure all timers use every rising PCLK edge. */
221 8d8bd7beSOleksij Rempel writel_relaxed(BM_CTCR_DEFAULT, priv.base + HW_CTCR);
222 8d8bd7beSOleksij Rempel /* enable interrupt for TC0 and clean setting for all other lines */
223 8d8bd7beSOleksij Rempel writel_relaxed(BM_MCR_INT_EN(0) , priv.base + HW_MCR);
224 8d8bd7beSOleksij Rempel
225 8d8bd7beSOleksij Rempel rate = clk_get_rate(clk);
226 8d8bd7beSOleksij Rempel clocksource_mmio_init(priv.base + HW_TC1, DRIVER_NAME, rate,
227 8d8bd7beSOleksij Rempel 200, 32, clocksource_mmio_readl_up);
228 8d8bd7beSOleksij Rempel
229 8d8bd7beSOleksij Rempel /* Seems like we can't use counter without match register even if
230 8d8bd7beSOleksij Rempel * actions for MR are disabled. So, set MR to max value. */
231 8d8bd7beSOleksij Rempel writel_relaxed(0xffffffff, priv.base + HW_MR1);
232 8d8bd7beSOleksij Rempel /* enable TC1 */
233 8d8bd7beSOleksij Rempel writel_relaxed(BM_C1_EN, priv.base + HW_TCR + SET_REG);
234 8d8bd7beSOleksij Rempel
235 8d8bd7beSOleksij Rempel priv.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ);
236 8d8bd7beSOleksij Rempel event_dev.cpumask = cpumask_of(0);
237 8d8bd7beSOleksij Rempel clockevents_config_and_register(&event_dev, rate, 0x2c00, 0xfffffffe);
238 be5eb33dSDaniel Lezcano
239 be5eb33dSDaniel Lezcano return 0;
240 8d8bd7beSOleksij Rempel }
241 17273395SDaniel Lezcano TIMER_OF_DECLARE(asm9260_timer, "alphascale,asm9260-timer",
242 8d8bd7beSOleksij Rempel asm9260_timer_init);
243