1*3fde0e16SJolly Shah /* SPDX-License-Identifier: GPL-2.0 */ 2*3fde0e16SJolly Shah /* 3*3fde0e16SJolly Shah * Copyright (C) 2016-2018 Xilinx 4*3fde0e16SJolly Shah */ 5*3fde0e16SJolly Shah 6*3fde0e16SJolly Shah #ifndef __LINUX_CLK_ZYNQMP_H_ 7*3fde0e16SJolly Shah #define __LINUX_CLK_ZYNQMP_H_ 8*3fde0e16SJolly Shah 9*3fde0e16SJolly Shah #include <linux/spinlock.h> 10*3fde0e16SJolly Shah 11*3fde0e16SJolly Shah #include <linux/firmware/xlnx-zynqmp.h> 12*3fde0e16SJolly Shah 13*3fde0e16SJolly Shah /* Clock APIs payload parameters */ 14*3fde0e16SJolly Shah #define CLK_GET_NAME_RESP_LEN 16 15*3fde0e16SJolly Shah #define CLK_GET_TOPOLOGY_RESP_WORDS 3 16*3fde0e16SJolly Shah #define CLK_GET_PARENTS_RESP_WORDS 3 17*3fde0e16SJolly Shah #define CLK_GET_ATTR_RESP_WORDS 1 18*3fde0e16SJolly Shah 19*3fde0e16SJolly Shah enum topology_type { 20*3fde0e16SJolly Shah TYPE_INVALID, 21*3fde0e16SJolly Shah TYPE_MUX, 22*3fde0e16SJolly Shah TYPE_PLL, 23*3fde0e16SJolly Shah TYPE_FIXEDFACTOR, 24*3fde0e16SJolly Shah TYPE_DIV1, 25*3fde0e16SJolly Shah TYPE_DIV2, 26*3fde0e16SJolly Shah TYPE_GATE, 27*3fde0e16SJolly Shah }; 28*3fde0e16SJolly Shah 29*3fde0e16SJolly Shah /** 30*3fde0e16SJolly Shah * struct clock_topology - Clock topology 31*3fde0e16SJolly Shah * @type: Type of topology 32*3fde0e16SJolly Shah * @flag: Topology flags 33*3fde0e16SJolly Shah * @type_flag: Topology type specific flag 34*3fde0e16SJolly Shah */ 35*3fde0e16SJolly Shah struct clock_topology { 36*3fde0e16SJolly Shah u32 type; 37*3fde0e16SJolly Shah u32 flag; 38*3fde0e16SJolly Shah u32 type_flag; 39*3fde0e16SJolly Shah }; 40*3fde0e16SJolly Shah 41*3fde0e16SJolly Shah struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id, 42*3fde0e16SJolly Shah const char * const *parents, 43*3fde0e16SJolly Shah u8 num_parents, 44*3fde0e16SJolly Shah const struct clock_topology *nodes); 45*3fde0e16SJolly Shah 46*3fde0e16SJolly Shah struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id, 47*3fde0e16SJolly Shah const char * const *parents, 48*3fde0e16SJolly Shah u8 num_parents, 49*3fde0e16SJolly Shah const struct clock_topology *nodes); 50*3fde0e16SJolly Shah 51*3fde0e16SJolly Shah struct clk_hw *zynqmp_clk_register_divider(const char *name, 52*3fde0e16SJolly Shah u32 clk_id, 53*3fde0e16SJolly Shah const char * const *parents, 54*3fde0e16SJolly Shah u8 num_parents, 55*3fde0e16SJolly Shah const struct clock_topology *nodes); 56*3fde0e16SJolly Shah 57*3fde0e16SJolly Shah struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id, 58*3fde0e16SJolly Shah const char * const *parents, 59*3fde0e16SJolly Shah u8 num_parents, 60*3fde0e16SJolly Shah const struct clock_topology *nodes); 61*3fde0e16SJolly Shah 62*3fde0e16SJolly Shah struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, 63*3fde0e16SJolly Shah u32 clk_id, 64*3fde0e16SJolly Shah const char * const *parents, 65*3fde0e16SJolly Shah u8 num_parents, 66*3fde0e16SJolly Shah const struct clock_topology *nodes); 67*3fde0e16SJolly Shah 68*3fde0e16SJolly Shah #endif 69