1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2ba3fae06SLinus Walleij /*
3ba3fae06SLinus Walleij * linux/arch/arm/common/icst307.c
4ba3fae06SLinus Walleij *
5ba3fae06SLinus Walleij * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
6ba3fae06SLinus Walleij *
7ba3fae06SLinus Walleij * Support functions for calculating clocks/divisors for the ICST307
8*5f1d8970SAlexander A. Klimov * clock generators. See https://www.idt.com/ for more information
9ba3fae06SLinus Walleij * on these devices.
10ba3fae06SLinus Walleij *
11ba3fae06SLinus Walleij * This is an almost identical implementation to the ICST525 clock generator.
12ba3fae06SLinus Walleij * The s2div and idx2s files are different
13ba3fae06SLinus Walleij */
14ba3fae06SLinus Walleij #include <linux/module.h>
15ba3fae06SLinus Walleij #include <linux/kernel.h>
16ba3fae06SLinus Walleij #include <asm/div64.h>
17ba3fae06SLinus Walleij #include "icst.h"
18ba3fae06SLinus Walleij
19ba3fae06SLinus Walleij /*
20ba3fae06SLinus Walleij * Divisors for each OD setting.
21ba3fae06SLinus Walleij */
22ba3fae06SLinus Walleij const unsigned char icst307_s2div[8] = { 10, 2, 8, 4, 5, 7, 3, 6 };
23ba3fae06SLinus Walleij const unsigned char icst525_s2div[8] = { 10, 2, 8, 4, 5, 7, 9, 6 };
24ba3fae06SLinus Walleij EXPORT_SYMBOL(icst307_s2div);
25ba3fae06SLinus Walleij EXPORT_SYMBOL(icst525_s2div);
26ba3fae06SLinus Walleij
icst_hz(const struct icst_params * p,struct icst_vco vco)27ba3fae06SLinus Walleij unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco)
28ba3fae06SLinus Walleij {
29ba3fae06SLinus Walleij u64 dividend = p->ref * 2 * (u64)(vco.v + 8);
30ba3fae06SLinus Walleij u32 divisor = (vco.r + 2) * p->s2div[vco.s];
31ba3fae06SLinus Walleij
32ba3fae06SLinus Walleij do_div(dividend, divisor);
33ba3fae06SLinus Walleij return (unsigned long)dividend;
34ba3fae06SLinus Walleij }
35ba3fae06SLinus Walleij
36ba3fae06SLinus Walleij EXPORT_SYMBOL(icst_hz);
37ba3fae06SLinus Walleij
38ba3fae06SLinus Walleij /*
39ba3fae06SLinus Walleij * Ascending divisor S values.
40ba3fae06SLinus Walleij */
41ba3fae06SLinus Walleij const unsigned char icst307_idx2s[8] = { 1, 6, 3, 4, 7, 5, 2, 0 };
42ba3fae06SLinus Walleij const unsigned char icst525_idx2s[8] = { 1, 3, 4, 7, 5, 2, 6, 0 };
43ba3fae06SLinus Walleij EXPORT_SYMBOL(icst307_idx2s);
44ba3fae06SLinus Walleij EXPORT_SYMBOL(icst525_idx2s);
45ba3fae06SLinus Walleij
46ba3fae06SLinus Walleij struct icst_vco
icst_hz_to_vco(const struct icst_params * p,unsigned long freq)47ba3fae06SLinus Walleij icst_hz_to_vco(const struct icst_params *p, unsigned long freq)
48ba3fae06SLinus Walleij {
49ba3fae06SLinus Walleij struct icst_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max };
50ba3fae06SLinus Walleij unsigned long f;
51ba3fae06SLinus Walleij unsigned int i = 0, rd, best = (unsigned int)-1;
52ba3fae06SLinus Walleij
53ba3fae06SLinus Walleij /*
54ba3fae06SLinus Walleij * First, find the PLL output divisor such
55ba3fae06SLinus Walleij * that the PLL output is within spec.
56ba3fae06SLinus Walleij */
57ba3fae06SLinus Walleij do {
58ba3fae06SLinus Walleij f = freq * p->s2div[p->idx2s[i]];
59ba3fae06SLinus Walleij
60ba3fae06SLinus Walleij if (f > p->vco_min && f <= p->vco_max)
61ba3fae06SLinus Walleij break;
62ba3fae06SLinus Walleij i++;
63ba3fae06SLinus Walleij } while (i < 8);
64ba3fae06SLinus Walleij
65ba3fae06SLinus Walleij if (i >= 8)
66ba3fae06SLinus Walleij return vco;
67ba3fae06SLinus Walleij
68ba3fae06SLinus Walleij vco.s = p->idx2s[i];
69ba3fae06SLinus Walleij
70ba3fae06SLinus Walleij /*
71ba3fae06SLinus Walleij * Now find the closest divisor combination
72ba3fae06SLinus Walleij * which gives a PLL output of 'f'.
73ba3fae06SLinus Walleij */
74ba3fae06SLinus Walleij for (rd = p->rd_min; rd <= p->rd_max; rd++) {
75ba3fae06SLinus Walleij unsigned long fref_div, f_pll;
76ba3fae06SLinus Walleij unsigned int vd;
77ba3fae06SLinus Walleij int f_diff;
78ba3fae06SLinus Walleij
79ba3fae06SLinus Walleij fref_div = (2 * p->ref) / rd;
80ba3fae06SLinus Walleij
81ba3fae06SLinus Walleij vd = (f + fref_div / 2) / fref_div;
82ba3fae06SLinus Walleij if (vd < p->vd_min || vd > p->vd_max)
83ba3fae06SLinus Walleij continue;
84ba3fae06SLinus Walleij
85ba3fae06SLinus Walleij f_pll = fref_div * vd;
86ba3fae06SLinus Walleij f_diff = f_pll - f;
87ba3fae06SLinus Walleij if (f_diff < 0)
88ba3fae06SLinus Walleij f_diff = -f_diff;
89ba3fae06SLinus Walleij
90ba3fae06SLinus Walleij if ((unsigned)f_diff < best) {
91ba3fae06SLinus Walleij vco.v = vd - 8;
92ba3fae06SLinus Walleij vco.r = rd - 2;
93ba3fae06SLinus Walleij if (f_diff == 0)
94ba3fae06SLinus Walleij break;
95ba3fae06SLinus Walleij best = f_diff;
96ba3fae06SLinus Walleij }
97ba3fae06SLinus Walleij }
98ba3fae06SLinus Walleij
99ba3fae06SLinus Walleij return vco;
100ba3fae06SLinus Walleij }
101ba3fae06SLinus Walleij
102ba3fae06SLinus Walleij EXPORT_SYMBOL(icst_hz_to_vco);
103